JP2000032366A - Automatic gain control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform the voltage transformation of a PWM signal up to the voltage level required on the side of a tuner without damaging characteristics in simple configuration. SOLUTION: The power supply terminal of a digital amplifier circuit 81 composed of a CMOS gate circuit or the like is connected between a power supply terminal 85, to which a power supply voltage is supplied, and the ground. The input terminal of the digital amplifier circuit 81 and an AGC output terminal 45 of a demodulation circuit 42 are connected. By supplying the output of this digital amplifier circuit 81 through smoothing circuits 82 and 84 and a resistor 83 to an AGC input terminal 32 of a tuner 31, the circuit can be simplified without damaging the characteristics of the tuner 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control (hereinafter, referred to as "AGC") circuit for forming an AGC signal by smoothing a PWM signal suitable for, for example, a digital television.

[0002]

2. Description of the Related Art For example, in digital television,
The transmitting side digitally modulates the high-frequency carrier signal with the video signal and transmits the television signal. On the receiver side, the television signal is converted into an intermediate frequency signal by a tuner, and this intermediate frequency signal is digitally processed by a demodulation circuit formed into an IC to demodulate the video signal. When a television signal is received, AGC is performed on the tuner. However, digital (binary) processing must be performed inside the demodulation circuit. PW whose pulse width changes according to the level
A PWM signal generation circuit for generating the M signal is provided. This PWM signal is converted into a DC voltage by a smoothing circuit and supplied to the tuner as an AGC signal.

The voltage range of the AGC signal is naturally defined by the range of the power supply voltage of the tuner, and the demodulation circuit at the subsequent stage must supply the AGC signal within the voltage amplitude range. However, in recent years, where low power consumption is required, the voltage of the circuit has been reduced and the voltage of the IC process has been reduced, so that the AGC voltage range required on the tuner side may not be supplied from the demodulation circuit side. . In such a case, a voltage is raised using a pull-up resistor or the like at the expense of characteristics, or a voltage level is converted using an operational amplifier.

FIG. 6 shows a circuit diagram of A using the above-described pull-up resistor.
1 shows an example of a GC circuit. FIG. 7 shows an example of an AGC circuit using an operational amplifier. 6 and FIG.
A tuner 31 has, for example, an AGC input terminal 132 having a voltage range of 0 to 5 V. Also,
Reference numeral 142 denotes a digital demodulation circuit. The demodulation circuit 142 is, for example, 0-2.5V or 0-3.3.
AGC output terminal 14 for outputting a PWM signal oscillating at V
The AGC output terminal is connected to a smoothing circuit including a resistor 111 and a capacitor 112.

[0005] In the case of using a pull-up resistor,
As shown in FIG. 6, resistors 114 and 115 connected in series between the power supply terminal 116 and the ground are inserted.
A connection point between the resistor 115 and the resistor 115 is connected to the AGC input terminal 132 of the tuner 131, and is also connected to the smoothing circuits 111 and 112 via the resistor 113.

In the case of using an operational amplifier, an operational amplifier 121 is inserted between a power supply terminal 116 and the ground as shown in FIG. 7, and a positive input terminal of the operational amplifier 121 is connected to the smoothing circuits 111 and 112 via a resistor 122. Connected. Also, the output terminal of the operational amplifier 121 is grounded via a resistor 123 and a resistor 124 connected in series,
The connection point between the resistors 123 and 124 and the operational amplifier 1
21 is connected to the-input terminal. Therefore, a non-inverting amplifier circuit is configured. Output terminal of operational amplifier 121 and AG
A smoothing circuit including a resistor 125 and a capacitor 126 is connected between the input terminal 132 and the C input terminal 132.

[0007]

However, the conventional AGC circuit using the pull-up resistor has a problem that the dynamic range does not change and the characteristics are not sufficient. Further, in the AGC circuit using the operational amplifier, the operational amplifier needs to have a configuration corresponding to a single power supply, and it is necessary to take a sufficient noise countermeasure.

It is therefore an object of the present invention to provide an AGC circuit capable of converting a PWM signal to a voltage level required by the tuner with a simple configuration without deteriorating characteristics. Another object of the present invention is to provide an A / D converter that does not require adjustment and can be easily integrated into an IC and an LSI.
It is to provide a GC circuit.

[0009]

According to a first aspect of the present invention, in order to solve the above-mentioned problems, a PWM signal whose pulse width changes in accordance with the level of an input signal is obtained by demodulating an input signal supplied from a tuner. A demodulation circuit having a PWM signal generation circuit for generating a signal; a digital amplification circuit for amplifying the PWM signal from the demodulation circuit in a binary manner and outputting a PWM signal having a larger amplitude than the input PWM signal; The PWM signal from the amplifier circuit is smoothed, and A
An AGC circuit comprising: a smoothing circuit that supplies a GC signal.

According to the present invention, a power supply terminal of a digital amplifier circuit such as a CMOS gate circuit is connected between a power supply terminal to which a power supply voltage is supplied and a ground, an input terminal of the digital amplifier circuit is connected to an AGC output terminal, The output of this digital amplifier circuit is supplied to AG via a smoothing circuit and a resistor.
Since the tuner is supplied to the C input terminal, the tuner is controlled by the AGC signal in a predetermined amplitude range, so that the characteristics are not impaired. Further, since an AGC signal having a desired amplitude range can be obtained by a circuit having high noise resistance, it is not necessary to take measures against noise in the tuner, and the circuit as a whole can be simplified.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a digital television set-top box will be described below with reference to the drawings. The set-top box is an adapter dedicated to digital television broadcasting which is separately mounted and used on a television receiver. FIG. 1 shows a configuration of a digital cable television network that uses a cable television network for distributing television broadcasts via a coaxial cable as it is.

In FIG. 1, reference numeral 1 denotes a video database in which digitized video information is stored. The video information in the video database 1 is 64 QAM
(Quadrature Amplitude Modulation) The signal is supplied to one input terminal of the mixer 4 via the modulator 3. In FIG. 1, reference numeral 2 denotes an existing analog cable.
A television station, and an analog cable television broadcast signal from an analog cable television station 2
Is supplied to the other input terminal. In the mixer 4, the digital QAM modulation output and the analog cable television broadcast signal are mixed, and the output of the mixer 4 is supplied to the optical transmitter 5. The output of the mixer 4 is modulated by a predetermined modulation method in the optical transmitter 5 and supplied to the optical receiver 6 via an optical fiber. The received output is demodulated in the optical receiver 6, and this demodulated output is distributed to each contracted home via a plurality of amplifiers 7 as repeaters and a coaxial cable connecting the amplifiers.

Each video device is connected to a coaxial cable drawn into the home. For example, as one connection form, as shown in FIG. 1, a coaxial cable is connected to the VTR 9, and further, a television receiver 10a is connected to the VTR 9. As another connection form, as shown in FIG. 1, a coaxial cable is connected to the set-top box 8, and further, the television receiver 10 b is connected to the set-top box 8. This set top box 8
, It is possible to selectively watch conventional analog cable television broadcasting and digital television broadcasting.

FIG. 2 shows the set-top box 8 described above.
1 shows an example of the internal configuration of the device. As shown in FIG. 2, the set-top box 8 includes a tuner 31, a QAM receiver 32, an error correction circuit 11, an MPEG (Moving Picture Experts Gr
oup) decoder 12, graphics circuit 13, RF modulator 14, switch circuit 15, system memory 16, microprocessor 17, input / output interface 18,
It comprises an audio signal processing circuit 19, a D / A converter 20, and the like.

The above-mentioned coaxial cable is connected to an input terminal indicated by 21 in FIG. 2, and a signal obtained by mixing conventional analog cable television broadcasting and digital television broadcasting is transmitted via the coaxial cable. Supplied.

A signal via the coaxial cable and the input terminal 21 is supplied to the tuner 31 and the switch circuit 15. In the tuner 31, a desired channel is tuned, and the tuned output is converted into an intermediate frequency signal and supplied to the QAM receiver 32. In the QAM receiver 32, QAM demodulation is performed on the intermediate frequency signal to form baseband digital data. This QAM receiver 32
Is supplied to the error correction circuit 11. At this time, in the QAM receiver 32, an AGC signal having an amplitude range according to the necessity of the tuner 31 is formed and supplied to the tuner 31. A from this QAM receiver 32
The tuner 31 is controlled by the GC signal so that the tuning output is controlled to a predetermined level.

In the error correction circuit 11, the digital data from the QAM demodulator 32 is subjected to an error correction process, and the error-corrected digital data is supplied to the MPEG decoder 12 and the audio signal processing circuit 19. Supplied. The MPEG decoder 12 performs a decoding process and outputs the decoded output to the graphics circuit 1.
3, a reproduced video signal is formed. The reproduced video signal formed in the graphics circuit 13 is R
The signal is supplied to the F modulator 14.

On the other hand, a digital audio signal is formed in the audio signal processing circuit 19, and this digital audio signal is converted into an analog left and right channel reproduced audio signal by passing through the D / A converter 20. The reproduced audio signal is output from an output terminal 23,
24 and supplied to the RF modulation circuit 14.

In the RF modulator 14, the reproduced video signal and the reproduced audio signal are RF-modulated to form a reproduced television signal, and the reproduced television signal is extracted from the output terminal 22 via the switch circuit 15. The reproduced television signal extracted from the output terminal 22 is supplied to the above-described antenna terminal of the television receiver 10b.

In FIG. 2, reference numeral 17 denotes a microprocessor. Microprocessor 17
And an error correction circuit 11, an MPEG decoder 12, an RF modulator 14, a system memory 16, an input / output interface 18, and an audio signal processing circuit 19, which are connected by a bus. It is possible to give and receive. Therefore, the microprocessor 17
Reads out the data stored in the system memory 16 as needed to form a control signal, and supplies this control signal to each unit to centrally manage each unit.

FIG. 3 shows an example of the internal configuration of the last stage of the QAM receiver 32 and the tuner 31 described above. In FIG. 3, reference numeral 41 denotes an IF front end provided at the last stage of the tuner 31, and reference numeral 42 denotes a Q front end.
This is a demodulation circuit that is a main part of the AM receiver 32.

The terminal 51 of the IF front end 41 has
In the preceding stage, an output frequency-converted to an intermediate frequency signal (43.75 MHz) is supplied. This signal is amplified by passing through the amplifier 52, and the amplified output is supplied to the mixer 53. The mixer 53 is supplied with a signal of a predetermined frequency from a variable frequency oscillator 56, is further frequency-converted in the mixer 53, and outputs the converted output to the A / D converter 55 via the low-pass filter 54. Supplied. A / D
The converter 55 is supplied with a sampling clock of a predetermined frequency from a variable frequency oscillator 57, and the A / D converter 55 performs analog / digital conversion. A
The output of the / D converter 55 is supplied to each of the multipliers 61 and 62 constituting the demodulation circuit 42.

The cos πn / 2 signal is supplied to the multiplier 61, the amplitude of which is demodulated in the multiplier 61, and the demodulated output is passed through the Nyquist filter 63 to the phase shifter 65.
Supplied to On the other hand, the signal sin πn / 2 is supplied to the multiplier 62, the amplitude is demodulated in the multiplier 62, and the demodulated output is supplied to the phase shifter 65 via the Nyquist filter 64.

The phase shifter 65 is supplied with a cos ωn signal and a sin ωn signal which are read out from the ROM 67 as necessary and formed. The output of the equalizer 65 is supplied to the equalizer 66.
The restoration process of the carrier is completed through the equalizer 66. The output of the equalizer 66 is added to the adders 69 and 70 and the quantizer 7
1,72 and DFE (Decision-Feedback Equalizer)
The signal is supplied to an adaptive filter comprising a circuit 73, and through this filter, the QAM demodulation process is completed to form baseband digital data. The output is taken out via two output terminals 74 and 75. .

In FIG. 3, reference numeral 68 denotes a synchronization processing circuit. The output of the A / D converter 55 of the IF front end 41 is supplied to the synchronization processing circuit 68. In the synchronization processing circuit 68, control signals for the variable frequency oscillators 56 and 57 and the ROM 67 are formed, and a voltage of 0 to 2.5 V or 0 to the tuner 31 is supplied to the tuner 31.
A PWM signal amplitude of 3.3V is formed. The PWM signal formed in the synchronization processing circuit 68 is supplied to the AGC signal forming circuit 43. In the AGC signal forming circuit 43, the amplitude range of the tuner 31 is set to A as required.
A GC signal is formed, and the AGC signal is supplied to the tuner 31.

FIG. 4 shows the AGC signal forming circuit 43 described above.
The following shows a specific configuration. As shown in FIG. 4, the AGC signal forming circuit 43 includes a digital amplifying circuit 81, a smoothing circuit including a resistor 82 and a capacitor 84, and a resistor 83. In addition, what is indicated by 32 in FIG. 4 is, for example, an AGC input terminal provided in the tuner 31 and having a voltage range of 0 to 5V. Reference numeral 45 denotes an AGC output terminal provided in the demodulation circuit for outputting, for example, a PWM signal having an amplitude of 0 to 2.5 V or 0 to 3.3 V.

As shown in FIG. 4, for example, a power supply terminal of a digital amplifier 81 is connected between a power supply terminal 85 to which a voltage of 5 V is supplied and ground, and an input terminal of the digital amplifier 81 and an AGC output terminal 45 are connected. ing. One end of a resistor 82 is connected to the output terminal of the digital amplifying circuit 81, the other end of the resistor 82 is grounded via a capacitor 84, and connected to the AGC input terminal 32 via a resistor 83.

As the digital amplifying circuit 81, for example, a TTL input CMOS gate circuit is used. Specifically, the input terminals of the AND circuit and the OR circuit are commonly used, the input terminals of the NAND circuit and the NOR circuit are commonly used as a two-stage connection, and the inverter circuit is used as a two-stage connection. The TTL input level is
For example, the L level is set to 0.8 V or less, and the H level is set to 2.0 or more. In the digital amplifying circuit 81, a PWM having an amplitude of 0 to 2.5 V or 0 to 3.3 V
The signal is voltage converted to form a PWM signal that oscillates at 0-5V. The PWM signal is converted into a DC voltage by the smoothing circuits 82 and 84 to form an AGC signal, and the AGC signal is supplied to the AGC input terminal 32 via the resistor 83.
Therefore, since the tuner 31 is controlled by the AGC signal in the predetermined amplitude range, the characteristics are not deteriorated. In addition, the circuit having a high noise resistance has an amplitude A of 0 to 5V.
Since the GC signal is formed, it is not necessary to take measures against noise on the tuner 31 side, and the circuit as a whole can be simplified.

The TTL input CMOS gate circuit used as the above-described digital amplifying circuit 81 can be easily formed into an IC and an LSI, and the demodulating circuit 42 and the digital amplifying circuit 81 are integrated into one chip as indicated by 44 in FIG. The integrated LSI is actually used, and this dedicated LSI
A resistor 8 as an external component between the tuner 31 and 44
2, 83 and a capacitor 84 are provided.

In the above description, one embodiment in which the present invention is applied to a set-top box has been described. However, it goes without saying that the present invention may be incorporated in a television receiver.

In the above description, an embodiment has been described in which a reproduced television signal is supplied to a television receiver. However, digital data may be supplied to another information device. Further, the present invention can be applied not only to the transmission of television signals but also to the transmission of digital data in both directions. In this case, the configuration after the QAM receiver 32 is configured as shown in FIG. 5, for example.

In FIG. 5, reference numeral 91 denotes an error correction and framing processing circuit, and reference numeral 92 denotes a media access control circuit.
Reference numeral 3 denotes a RAM, and reference numeral 94 denotes a bus interface. Baseband digital data from the QAM receiver 32 is supplied to an error correction and framing processing circuit 91. The output processed by the error correction and framing processing circuit 91 is supplied to, for example, a personal computer via a bus interface 94. The output subjected to the predetermined processing by the error correction and framing processing circuit 91 is supplied to another external information device via an upstream transmitter. Conversely, digital data is supplied to the tuner 31 from another external information device, and data can be exchanged bidirectionally.

[0033]

According to the present invention, the digital amplifier and the smoothing circuit are provided between the demodulator and the tuner. Therefore, according to the present invention, the PWM level can be increased to a voltage level required by the tuner side with a simple configuration without deteriorating characteristics.
The signal can be voltage converted. Further, since an AGC signal having a desired amplitude range can be obtained by a circuit having high noise resistance, it is not necessary to take measures against noise in the tuner, and the circuit can be simplified as a whole. Further, according to the present invention, since a digital amplifying circuit including a CMOS gate circuit or the like is used, there is no need for adjustment, and it is easy to implement an IC and an LSI.
It is possible to reduce the size and cost of the entire circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a connection relationship of a set-top box to which the present invention is applied.

FIG. 2 is a block diagram showing an internal configuration of a set-top box to which the present invention is applied.

FIG. 3 is a block diagram showing a configuration of a demodulation circuit in a set-top box to which the present invention is applied.

FIG. 4 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 5 is a block diagram used for describing another embodiment of the present invention.

FIG. 6 is a circuit diagram used for describing a conventional AGC circuit.

FIG. 7 is a circuit diagram used for describing a conventional AGC circuit.

[Explanation of symbols]

8 ... set-top box, 31 ... tuner,
32 QAM receiver, 42 demodulation circuit, 81
..Digital amplifier circuits, 82, 84...
83 ... resistance

Claims (2)

[Claims] An input signal supplied from a tuner is demodulated, and a pulse width of which is changed according to the level of the input signal.
A demodulation circuit having a PWM signal generation circuit for generating a WM signal; a digital amplification circuit for amplifying the PWM signal from the demodulation circuit in a binary manner and outputting a PWM signal having a larger amplitude than the input PWM signal; Smoothing the PWM signal from the digital amplifier circuit,
An automatic gain control circuit comprising: a smoothing circuit that supplies the tuner as an AGC signal. 2. The automatic gain control circuit according to claim 1, wherein at least the demodulation circuit and the digital amplification circuit are integrated on one chip.