JP3373431B2 - Digital broadcast receiver - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital broadcast receiver for receiving digital broadcast modulated by the OFDM system.

[0002]

2. Description of the Related Art Terrestrial TV broadcasting is one of the digital TV broadcasting that enables more TV programs to be transmitted using the same frequency band than analog TV broadcasting. . In addition, as one of the terrestrial television broadcasting systems, an analog video signal and an audio signal are digitized and compressed, and the compressed digital signal is converted into an Orthogonal Frequency Di
Vision Multiplexing method (hereinafter referred to as O
There is a method of digitally modulating and transmitting by the FDM method).

FIG. 3 shows a conventional technique for receiving a television broadcast digitally modulated by the OFDM system. That is, the terminal 51 to which the signal from the antenna is guided
Is connected to the tuner circuit 11 in the UHF band or V
A first intermediate frequency signal is generated by performing amplification and frequency conversion of the HF band television signal. The first intermediate frequency signal is amplified by the first intermediate frequency amplifier circuit 12 and then converted into a second intermediate frequency signal by the second frequency conversion circuit 13. Then, the second intermediate frequency signal is guided to the A / D conversion circuit 15 via the second intermediate frequency signal circuit 14 and converted into a digital signal. The digital signal output from the A / D conversion circuit 15 is demodulated by the OFDM demodulation circuit 16 and error-corrected. The digital data obtained as a result is transmitted from the terminal 52 as transport stream data.
The transport stream data sent from the terminal 52 is converted into a video signal and an audio signal by MPEG demodulation processing (this is referred to as a first conventional technique).

Further, as a conventional technique using a digital signal processing circuit as a demodulating means for obtaining a demodulated signal, Japanese Patent Laid-Open No. 1-245720 has been proposed. In this conventional technique, the frequency ratio between the operation clock of the digital signal processing circuit and the reference frequency signal is an integer ratio. Further, the operation clock and the reference frequency signal are synchronized in phase. Therefore, the number of beats between the operation clock and the reference frequency signal is reduced, and the deterioration of the S / N ratio and the deterioration of the reception sensitivity are suppressed (this is referred to as the second conventional technique).

[0005]

However, when the above technique is used, the following problems occur. That is, in the first conventional technique, the local oscillating circuit of the tuner circuit 11 has the PLL synthesizer 22. Therefore, the reference signal generating circuit 17 for sending the reference signal to the PLL synthesizer 22 is provided. Further, a crystal oscillation element 41 is used for the oscillation element of the reference signal generation circuit 17 in order to satisfy the accuracy and stability of the oscillation frequency.
Further, since the OFDM demodulation circuit 16 requires a reference clock that serves as a reference for operation, a reference clock generation circuit 91 that supplies the reference clock to the OFDM demodulation circuit 16 is provided. Further, as the oscillation element of the reference clock generation circuit 91, the crystal oscillation element 92 is used in order to satisfy the accuracy and stability of the oscillation frequency. That is, each of the reference signal generation circuit 17 and the reference clock generation circuit 91
Since it has a configuration in which a crystal oscillator element whose component price is extremely expensive is provided, it causes an increase in the component cost of the device and
There is a problem that the mounting area increases. Also, OF
Since the reference clock of the DM demodulation circuit 16 has a frequency close to the frequency of the first intermediate frequency signal, radiation interference has been a problem.

Further, in the second conventional technique, a frequency dividing circuit is used as a means for obtaining an operation clock phase-synchronized with the reference frequency signal. Therefore, in order to generate an operation clock having a high frequency (40 MHz) required by the OFDM demodulation circuit, it is necessary to set the frequency of the reference frequency signal supplied to the frequency dividing circuit to a frequency that is an integral multiple of 40 MHz. . The crystal oscillator element used to generate such a high frequency is extremely expensive. Therefore, from the viewpoint of reducing the cost of parts, it is not preferable to apply the second conventional technique.

The present invention was devised to solve the above problems, and an object of the present invention is to demodulate a signal obtained by multiplying a reference signal for a local oscillator circuit by OFDM demodulation. By using as a reference clock for the circuit, a crystal oscillator for generating the reference clock for the OFDM demodulation circuit is not required, thereby reducing the cost of parts, reducing the mounting area, and avoiding radiation interference. To provide a receiving device.

In addition to the above object, an object of the present invention as set forth in claim 2 is to provide a P oscillator using an LC oscillator circuit as a voltage controlled oscillator circuit.
An object of the present invention is to provide a digital broadcast receiving device capable of reducing the cost of parts of a frequency multiplication circuit by performing frequency multiplication by an LL synthesizer.

In addition to the above object, an object of the invention of claim 3 is to reproduce digital data indicating a video signal and an audio signal from a digitally modulated television signal with a structure in which parts cost is low. An object of the present invention is to provide a digital broadcast receiving device capable of doing the above.

In addition to the above object, an object of the invention of claim 4 is to provide digital data representing a video signal and an audio signal from a digitally modulated terrestrial television signal with a structure in which parts cost is low. An object of the present invention is to provide a digital broadcast receiving device capable of reproducing.

[0011]

In order to solve the above problems, a digital broadcast receiving apparatus according to claim 1 of the present invention comprises:
In a digital broadcast receiving apparatus for receiving a digital broadcast modulated by the OFDM system, a PLL synthesizer provided in a frequency conversion circuit for converting a received radio wave into a first intermediate frequency signal and generating a local oscillation signal, and the PLL synthesizer. A reference signal generation circuit for transmitting a reference signal to
An A / D conversion circuit for A / D converting the second intermediate frequency signal obtained by frequency-converting the first intermediate frequency signal;
An OFD by multiplying the OFDM demodulation circuit that demodulates the transmitted digital data based on the digital signal transmitted from the A / D conversion circuit and the reference signal
And a multiplication circuit for generating a reference clock of the M demodulation circuit. That is, since the multiplication circuit generates the reference clock by multiplying the reference signal, the frequency accuracy and stability of the reference clock correspond to the frequency accuracy and stability of the reference signal. Therefore, OF
The DM demodulation circuit performs the same operation as when the reference clock is supplied from the dedicated oscillation circuit using the crystal oscillation element.

According to a second aspect of the present invention, in addition to the above configuration, the digital broadcast receiving apparatus further includes a voltage control oscillation circuit in which the oscillation frequency is determined by a resonance circuit including a coil and a capacitor. With the above configuration, based on the result of phase comparison between the divided signal obtained by dividing the reference signal and the divided signal obtained by dividing the output of the voltage controlled oscillator circuit, while controlling the oscillation frequency of the voltage controlled oscillator circuit, The output of the voltage controlled oscillator circuit is used as the reference clock. That is, the coil and the capacitor that are the oscillation elements of the voltage controlled oscillation circuit are inexpensive elements. Therefore, the voltage controlled oscillator circuit is composed of only inexpensive parts. As a result, the multiplication circuit is also composed of only inexpensive elements.

Further, in addition to the above configuration, a digital broadcast receiving apparatus according to a third aspect of the present invention is configured to receive a radio wave of a digitally modulated television signal. Therefore, the digital data indicating the video signal and the audio signal can be reproduced from the digitally modulated television signal with the configuration that the parts cost is low.

In addition to the above configuration, the digital broadcast receiving apparatus according to a fourth aspect of the present invention is configured to receive a terrestrial television signal. Therefore, digital data indicating a video signal and an audio signal can be reproduced from a digitally modulated terrestrial television signal with a configuration in which the cost of parts is low.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an electrical configuration of an embodiment of a digital broadcast receiving apparatus according to the present invention, showing a receiving apparatus for receiving a digitally modulated terrestrial television signal. . It should be noted that the same reference numerals as those in FIG. 3 are given to blocks having the same configuration as that of the conventional technique shown in FIG.

In the figure, the tuner circuit 11 has a terminal 5
By amplifying and frequency-converting the UHF band or VHF band television signal guided through
It is a block for generating the first intermediate frequency signal. Therefore, a UHF amplifier circuit 3 that amplifies signals in the UHF band
1 and a VHF amplifier circuit 33 that amplifies a signal in the VHF band
And the signal or V amplified by the UHF amplifier circuit 31.
A frequency conversion circuit 21 for converting the signal amplified by the HF amplifier circuit 33 into a first intermediate frequency signal.

Further, the frequency conversion circuit 21 converts the signal amplified by the UHF amplification circuit 31 into a first intermediate frequency signal and the UHF mixing circuit 32, and the signal amplified by the VHF amplification circuit 33 as a first intermediate frequency signal. Convert to VHF
A mixing circuit 34, a UHF local oscillation circuit 35 that supplies a local oscillation signal to the UHF mixing circuit 32, and a VHF mixing circuit 3
VHF local oscillation circuit 36 for supplying a local oscillation signal to 4
And a PLL frequency control circuit 37 for controlling the oscillation frequency of the UHF local oscillation circuit 35 and the VHF local oscillation circuit 36.
It has and.

The PLL frequency control circuit 37 has terminals 53,
The signal of the local oscillation signal is controlled in response to the input indicating the receiving channel introduced via 54. That is,
When receiving in the UHF band, a signal obtained by dividing the local oscillation signal 351 transmitted from the UHF local oscillation circuit 35 and the reference signal 17 transmitted from the reference signal generation circuit 17 are used.
Phase comparison with a signal obtained by dividing 1 is performed. Then, the control signal 371 based on the result of the phase comparison is sent to the UHF local oscillation circuit 35 to set the oscillation frequency of the UHF local oscillation circuit 35 to the frequency corresponding to the reception channel. Further, the reception frequency of the UHF amplifier circuit 31 is set to the frequency of the reception channel.

When receiving in the VHF band,
Local oscillation signal 3 transmitted from VHF local oscillation circuit 36
A phase comparison is performed between the signal obtained by dividing 61 and the signal obtained by dividing the reference signal 171. Then, by sending the control signal 372 based on the result of the phase comparison to the VHF local oscillation circuit 36, the oscillation signal of the VHF local oscillation circuit 36 is set to the frequency corresponding to the reception channel. Also, VHF
The reception frequency of the amplifier circuit 33 is set to the frequency of the reception channel.

As is clear from the above description, UH
The block 22 including the F local oscillation circuit 35, the VHF local oscillation circuit 36, and the PLL frequency control circuit 37 is a PLL synthesizer described in the claims.

The reference signal generation circuit 17 includes a crystal oscillation element 4
It is a block that supplies the reference signal 171 generated by using 1 to the PLL synthesizer 22. The crystal oscillation element 41 is an element having a vibration frequency of 4 MHz. Therefore, the frequency of the reference signal 171 is also 4 MHz.
It is z.

The first intermediate frequency amplifier circuit 12 is a block composed of a bandpass filter that allows only a signal in a predetermined band to pass and an amplifier capable of changing the amplification factor. Band limiting and amplification of the transmitted first intermediate frequency signal are performed.

The second frequency conversion circuit 13 is a block composed of a local oscillation circuit and a mixing circuit into which the output of the local oscillation circuit and the first intermediate frequency signal are guided.
The first intermediate frequency signal amplified by the first intermediate frequency amplifier circuit 12 is frequency-converted into a second intermediate frequency signal.

The second intermediate frequency signal circuit 14 is a block having only a narrow band filter, and has no amplifier. Therefore, the second intermediate frequency signal circuit 14
Only the band limitation of the second intermediate frequency signal output from the second frequency conversion circuit 13 is performed, and the band limited second intermediate frequency signal is sent to the A / D conversion circuit 15.

The A / D conversion circuit 15 is a block for sampling the second intermediate frequency signal at the timing according to the sampling clock supplied from the OFDM demodulation circuit 16. Then, the digital signal obtained by sampling is sent to the OFDM demodulation circuit 16.

The OFDM demodulation circuit 16 is a block that performs OFDM demodulation of the digital signal output from the A / D conversion circuit 15. Further, error correction is performed on the data obtained by performing the OFDM demodulation. Then, the digital data for which error correction has been completed is transmitted from the terminal 52 as transport stream data.

Further, the OFDM demodulation circuit 16 sends a sampling clock obtained by dividing the reference clock 101 to the A / D conversion circuit 15. And A /
The level of the second intermediate frequency signal is detected based on the digital signal sent from the D conversion circuit 15, and the detection result is sent to the second AGC circuit 19. The transport stream data sent from the terminal 52 is guided to a demodulation circuit (not shown), subjected to MPEG demodulation processing, and converted into a video signal and an audio signal.

The first AGC circuit 18 detects the signal level at a predetermined location in the first intermediate frequency amplifier circuit 12, and
It is a block that generates an AGC signal corresponding to the detection result. Then, with the generated AGC signal, UH
By controlling the amplification factors of the F amplification circuit 31 and the VHF amplification circuit 33, the level of the first intermediate frequency signal is made constant.

The second AGC circuit 19 is a block which generates an AGC signal according to the detection output sent from the OFDM demodulation circuit 16. Then, the level of the second intermediate frequency signal guided to the A / D conversion circuit 15 is made constant by controlling the amplification factor of the first intermediate frequency amplification circuit 12 with the generated AGC signal.

The multiplication circuit 10 uses a reference signal 17 of 4 MHz.
It is a block that supplies the OFDM demodulation circuit 16 with the 40 MHz reference clock 101 obtained by multiplying 1 by 10. In detail, as shown in FIG.
It has two frequency dividing circuits 61 and 62, a phase comparison circuit 63, a charge pump 64, a loop filter 65, and a voltage controlled oscillation circuit 66, and has a known configuration as a PLL synthesizer.

The detailed configuration of the frequency multiplying circuit 10 will be described with reference to FIG. 2. The frequency dividing circuit 61 divides the 4 MHz reference signal 171 to generate a signal serving as a reference for comparison. Has become. In addition, the frequency dividing circuit 62
Is a block that divides the output of the voltage controlled oscillator circuit 66 to generate a signal to be subjected to phase comparison. Therefore, the dividing ratio of the dividing circuit 61 and the dividing circuit 6
The division ratio of 2 is 1:10.

The phase comparison circuit 63 is a block for performing a phase comparison between the output of the frequency dividing circuit 61 and the output of the frequency dividing circuit 62, and generates a pulse corresponding to the phase comparison result.
Output. In addition, the charge pump 64 is a block that absorbs and discharges current according to the pulse sent from the phase comparison circuit 63. The loop filter 65 is a block that removes high frequency components generated by the operation of the charge pump 64.

The voltage controlled oscillator 66 is a VCO using LC resonance in order to reduce the cost of the element. That is, the oscillation frequency determined by the combined capacitance of the two capacitors C1 and C2 and the varicap diode D1 and the inductance of the coil L1 is the VCO set to 40 MHz. The resistor R1 is an element for applying the output of the loop filter 65 to the varicap diode D1, and the capacitor C3 is an element for removing the high frequency component leaking from the resistor R1.

Since the oscillation frequency in the phase-locked state is constant at 40 MHz, the variation range of the oscillation frequency may be narrow.
The FM noise component is extremely small, and a clap circuit capable of obtaining an oscillation output with high signal purity is used.

The multiplication circuit 10 has such a structure. Therefore, the frequency of the reference clock 101 is 40 times 4 MHz which is the frequency of the reference signal 171 multiplied by 10.
As the frequency becomes MHz, the frequency accuracy and stability also become high according to the accuracy of the reference signal 171. Regarding the signal purity of the reference clock 101, the voltage controlled oscillator circuit 6
Although no crystal oscillator is used in 6,
The signal has very little signal noise and very high signal purity.

Next, the operation of the digital broadcast receiving apparatus having the above configuration will be described. The reference signal generation circuit 17 is a reference signal (reference signal having high frequency accuracy and stability and high signal purity) 171 generated using the crystal oscillation element 41.
Is sent to the PLL frequency control circuit 37 and the multiplication circuit 10. In addition, the multiplier circuit 10 has a 40M obtained by multiplying the reference signal 171 by 10 as described above.
Hz reference clock (40 MHz reference clock with high signal purity, with frequency accuracy and stability conforming to the accuracy of the reference signal 171, with very few FM noise components) 1
01 is generated and sent to the OFDM demodulation circuit 16.

Therefore, the OFDM demodulation circuit 16 can perform the same operation as when the reference clock 101 is directly supplied from the oscillation circuit using the crystal oscillation element. Further, the OFDM demodulation circuit 16 uses the reference clock 10
The sampling clock generated by dividing 1 is supplied to the A / D conversion circuit 15.

On the other hand, the tuner circuit 11 has terminals 53, 5
The radio wave of the channel according to the input from 4 is received, and the received radio wave is converted into the first intermediate frequency signal. The first intermediate frequency signal is amplified by the first intermediate frequency amplifier circuit 12, and then converted into a second intermediate frequency signal by the second frequency conversion circuit 13. Then, the second intermediate frequency signal is the second
After being band-limited by the intermediate frequency signal circuit 14, A /
It is given to the D conversion circuit 15.

The A / D conversion circuit 15 supplied with the second intermediate frequency signal converts the second intermediate frequency signal into a digital signal by sampling at the timing according to the sampling clock. Then, the converted digital signal is sent to the OFDM demodulation circuit 16. Further, the OFDM demodulation circuit 16 performs OFDM demodulation on the digital signal sent from the A / D conversion circuit 15 and also performs error correction on the data obtained by the demodulation. Then, the error-corrected data is compressed digital data (transport stream data) indicating a video signal and an audio signal.
Is sent from the terminal 52.

The present invention is not limited to the above-mentioned embodiment, and the inventions of claims 1 and 2 can be applied to a digital broadcast receiving apparatus showing only an audio signal.

Regarding the multiplication rate of the multiplication circuit 10, since the frequency of the reference clock 101 is 10 times the frequency of the reference signal 171, the multiplication rate is 10 times, but the frequency of the reference signal 171 is set. And reference clock 101
When the relationship with the frequency of is different, it is possible to set the magnification corresponding to the different relationship. For example, when the relationship between the frequency of the reference signal 171 and the frequency of the reference clock 101 is N to M (N and M are integers), the multiplication rate is M / N.

Further, the reference signal generating circuit 17, the PLL frequency control circuit 37 and the multiplication circuit 10 (excluding the coil L1, the capacitors C1, C2 and C3, the resistor R1 and the varicap diode D1) are integrated in one IC. in case of,
Since the mounting area on the printed wiring board is reduced,
It is possible to downsize the device.

[0044]

According to the digital broadcast receiving apparatus of the present invention, a PLL synthesizer for generating a local oscillation signal is provided in a frequency conversion circuit for converting a received radio wave into a first intermediate frequency signal, and a PLL. A reference signal generating circuit for sending a reference signal to the synthesizer, and a second intermediate frequency signal obtained by frequency-converting the first intermediate frequency signal
A / D conversion circuit for D / D conversion, an OFDM demodulation circuit for demodulating transmitted digital data based on a digital signal sent from the A / D conversion circuit, and an OFDM demodulation circuit for multiplying a reference signal And a multiplication circuit for generating a reference clock. That is, since the multiplier circuit generates the reference clock by multiplying the reference signal, the frequency accuracy and stability of the reference clock correspond to the frequency accuracy and stability of the reference signal. Therefore, since the OFDM demodulation circuit can execute the predetermined operation without any trouble, the dedicated crystal oscillation element for generating the reference clock of the OFDM demodulation circuit becomes unnecessary. In other words, it is not necessary to separately provide a crystal oscillation element for each of the PLL synthesizer and the OFDM demodulation circuit.
Since two crystal oscillators can be shared, the cost of parts can be reduced by that amount, the mounting area of the circuit can be reduced, and the interference due to radiation can be avoided.

Further, in addition to the above configuration, a digital broadcast receiving apparatus according to a second aspect of the present invention includes a multiplication circuit, and a voltage controlled oscillation circuit whose oscillation frequency is determined by a resonance circuit including a coil and a capacitor. In addition to controlling the oscillation frequency of the voltage controlled oscillator circuit based on the result of phase comparison between the divided signal obtained by dividing the reference signal and the divided signal obtained by dividing the output of the voltage controlled oscillator circuit, The output of the oscillation circuit is used as the reference clock. That is, since the coil and the capacitor forming the oscillation element of the voltage controlled oscillation circuit are inexpensive elements, the voltage controlled oscillation circuit is composed of only inexpensive parts. As a result, since the multiplication circuit is also composed of only inexpensive elements, the cost of parts of the multiplication circuit can be reduced.

In addition to the above configuration, the digital broadcast receiving apparatus according to a third aspect of the present invention is configured to receive the radio waves of a digitally modulated television signal. Therefore, it is possible to reproduce digital data indicating a video signal and an audio signal from a digitally modulated television signal with a configuration in which the cost of parts is low.

Further, in addition to the above configuration, the digital broadcast receiving apparatus according to a fourth aspect of the present invention is configured to receive a terrestrial television signal. Therefore, it is possible to reproduce digital data indicating a video signal and an audio signal from a digitally modulated terrestrial television signal with a configuration in which the cost of parts is low.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of an embodiment of a digital broadcast receiving apparatus according to the present invention.

FIG. 2 is a block diagram showing a detailed electrical configuration of a multiplication circuit.

FIG. 3 is a block diagram showing an electrical configuration of a conventional technique.

[Explanation of symbols]

10 multiplication circuit 11 Tuner circuit 15 A / D conversion circuit 16 OFDM demodulation circuit 17 Reference signal generation circuit 21 Frequency conversion circuit 22 PLL Synthesizer 66 Voltage controlled oscillator 101 Reference clock 171 Reference signal C1 Capacitor forming a resonance circuit L1 Resonant circuit coil

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Claims (4)

(57) [Claims] 1. A digital synthesizer for receiving a digital broadcast modulated by an OFDM system, a PLL synthesizer provided in a frequency conversion circuit for converting a received radio wave into a first intermediate frequency signal and generating a local oscillation signal. A reference signal generation circuit for transmitting a reference signal to the PLL synthesizer; an A / D conversion circuit for A / D converting the second intermediate frequency signal obtained by frequency-converting the first intermediate frequency signal; An OFDM demodulation circuit that demodulates the transmitted digital data based on the digital signal transmitted from the A / D conversion circuit, and a multiplication circuit that generates a reference clock of the OFDM demodulation circuit by multiplying the reference signal. A digital broadcast receiving device characterized by being provided. 2. The frequency multiplying circuit includes a voltage controlled oscillator circuit whose oscillation frequency is determined by a resonance circuit composed of a coil and a capacitor, wherein a divided signal obtained by dividing the reference signal and an output of the voltage controlled oscillator circuit. Based on the result of phase comparison with the divided signal obtained by dividing the
2. The digital broadcast receiving apparatus according to claim 1, wherein the output of the voltage controlled oscillator circuit is the reference clock. 3. The digital broadcast receiving apparatus according to claim 1, wherein the radio wave is a digitally modulated television signal. 4. The digital broadcast receiving apparatus according to claim 3, wherein the radio wave is a terrestrial television signal.