JP2000031949A - System and method for adjusting phase angle of data clock signal reproduced from received data signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To digitally detect the change of a transmission data clock edge part and to perform adjustment to accurately follow a transmission clock by allowing a phase state machine to receive a signal transmitted by each counter and to adjust the phase angle of a data clock signal reproduced based on the signal received from each counter. SOLUTION: An-FM IN data string is transmitted to three binary counters, i.e., a centroid counter 400, a quadrature phase 1 counter 410 and a quadrature phase 2 counter 420. In such a case, the counters 400 to 420 compare with each threshold that is preliminarily determined after performing each calculation. The threshold is suitably counted by each counter 400 to 420. It is preferable to be a numeric value representing about half of the number of FM-IN samples. A state machine 440 uses data from the counters 400 to 420 to adjust the timing and phase angle of wideband data clock.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates generally to the field of wireless communications, and more particularly, to the field of adjusting the phase angle of a data clock signal recovered from a data signal.

[0002]

2. Description of the Related Art In wireless communications, clock information for data is usually embedded in a data signal and is usually encoded in analog data so that it is transmitted together with the data. Sent in the air in the form of a format. A commonly used encoding scheme is Manchester encoding, in which case a data transmission clock operating at twice the frequency of the data signal clock is embedded in the data signal. When using Manchester encoding, changes in the data transmission clock are inserted during each data signal period and the transmission clock can be recovered by processing the received data sequence.

[0003] Manchester-encoded data
One method for reproducing the transmission clock in the sequence is to detect a change in the clock at the center of each signal bit. This method uses a specific bit
In some patterns, each single data signal bit is
The problem arises because two data transmission clock edges may have a change. Also, due to noise often mixed in the transmission data signal, each data signal bit may not include the above clock change. further,
The change in the transmit clock may not be fast enough for the clock edge detection circuit to detect the change, or the change may be too fast for the clock edge detection circuit to detect the change. Therefore, a clock recovery method based on detecting a change in clock change
A problem arises because it depends heavily on the quality of the received signal.

[0004] Other digital transmission clock recovery techniques use the detection of the presence of synchronization bits, which are used to clarify the leading bits of the data signal bits, and the signal distance within a bit is longer than the maximum signal distance within a bit. Including case detection. However, this method must add at least one synchronization bit. Therefore, the data transmission throughput decreases and the circuit becomes complicated.

[0005] Therefore, there is a need in the industry for a system that addresses the above and other related and unrelated problems.

[0006]

SUMMARY OF THE INVENTION The present invention provides a system for adjusting the timing and phase angle of a data clock signal recovered from a received data signal. The system includes a plurality of counters and a phase state machine. Each counter of the plurality of counters determines the number of samples having a logical (1) value included in a particular portion of one cycle of the received data signal. Thereafter, each counter compares the number to a predetermined threshold. Each counter transmits a signal indicating whether the number of samples having a logical value of (1) in each part of the period of the received data signal is greater than, less than, or equal to a predetermined threshold. I do. The phase state machine receives the signal transmitted by each counter and adjusts the phase angle of the reproduced data clock signal based on the signal received from each counter.

In a first preferred embodiment of the invention, the first counter counts a centrally digitally sampled data sample of the data period of the received data signal.

[0008] In a first preferred embodiment of the invention, the second counter comprises a digitally sampled data portion of a data period having a sample detected before the sample of the central portion. -Count the sample.

In a first preferred embodiment of the invention, the third counter comprises a digitally sampled data portion of the data period having the sample detected after the central sample. -Count the sample.

In the first preferred embodiment of the present invention, the effective counting windows of the second and third counters are slightly superimposed near the expected position of the transmit clock, and one counter changes Is counted, the other counters can reliably count the change.

In a second preferred embodiment of the invention, the effective counting windows of the second and third counters do not overlap.

Therefore, the present invention provides a method that can digitally detect changes in the transmit data clock edge and make adjustments to accurately follow the transmit clock. The present invention does not rely on the actual detection of clock edge changes, which can be difficult to detect.
A method for digitally detecting a clock edge is provided.

[0013] The objects, features and advantages of the present invention will become apparent upon reading and understanding the specification of the present invention with reference to the accompanying drawings.

[0014]

BRIEF DESCRIPTION OF THE DRAWINGS Referring now to the drawings in greater detail, like components are numbered similarly. FIG. 1 is a block diagram of a dual mode wireless telephone 10 that can operate in both digital and analog modes according to a first preferred embodiment of the present invention. The above block diagram is
Further, the invention also applies to wireless telephones of other embodiments of the present invention, including dual mode cellular and personal communication system (PCS) telephones. The radio telephone 10 can operate in both the digital mode and the analog mode. Hereinafter, the radio telephone 10 that operates in the analog mode will be described.

In a first preferred embodiment of the present invention, a radio signal is received by an antenna 12, filtered by a radio frequency transmit / receive (RF TX / RX) circuit 14, mixed, and mixed at a lower frequency. , And the signal subjected to the automatic gain control and the frequency modulation (FM) is demodulated, and then the analog front end (AFE) circuit 18
Is converted from analog to digital and sent to a CDMA modem circuit (CMC) 22. Central processing unit (CPU)
23, the CMC 22 demodulates the input digital data stream and converts the data to a digital signal processor (DS).
P) 26, where the coder / decoder (CODE)
Prior to decoding into an audio signal according to C), the digital data is Viterbi and digitally speech decoded. The decoded audio signal is
It is amplified so that it can be controlled by the controller 34 and output through the telephone speaker 36. Similarly, when the telephone microphone 38 detects the user's voice, the operation of the wireless telephone 10 follows the reverse path. Keypad 39 and display 40 provide conventional user input and output.

Referring to FIG. 2, FIG.
1 is a block diagram of an analog front end (AFE) circuit 18 of FIG. The configuration of the AFE 18 is divided into three parts. That is, the transmitting unit 190 and the receiving unit 19
5, and auxiliary parts (not shown). The auxiliary unit provides a basic management function, generates an error flag and a control flag based on data being processed by the AFE 18, includes a power supply circuit and a control circuit, and controls the entire function of the AFE 18. .

The transmitting section 190 performs necessary conversion for transmitting an output signal. The transmitting unit 190 can operate in either the analog mode or the digital mode depending on the operation mode of the wireless telephone 10 (FIG. 1). Transmission section 190
Transmits several low-pass filters (LP) to the transmitter 200.
F) (not shown), data latches (not shown), several buffers (not shown), and several digital-to-analog converters (DACs) (not shown). The input to the transmitter 200 is a transmission data sequence (TX DATA) and a transmission strobe (TX TX / FM STROB).
E). The TX IQ / FM STROBE is
The transmitter 200 is used to supply a clock to a DAC (not shown) and a data latch (not shown). In transmitter 200, analog TX DA
TA is set to a digital TX D by a DAC (not shown).
After being converted to ATA, the above digital TX DATA
Passes through an LPF (not shown) and RF TX / RX1
4 (FIG. 1) and antenna 12 (FIG. 1).

The receiving section 195 of the AFE 18 is divided into a digital section 196 and an analog section 197. The digital section 196 converts the received digital signal into CMC22 data.
The data is converted into a form suitable for the processing according to FIG. 1, but the description is omitted here. The analog section 197 includes the RF TX / R
X14 (FIG. 1), demodulated analog signal (FMDE
M) and decode the audio data signal and the wideband data signal. The band data signal is transmitted to the radio telephone 10
This is control data for FIG. The control data is transmitted along with the voice data signal when the wireless telephone 10 (FIG. 1) is operating in the analog mode.
Sent to. The input to the analog section 197 is RF T
FM DEM from X / RX14 circuit (FIG. 1) and RX from CMC 22 (FIG. 1) of radiotelephone 10 (FIG. 1)
Includes both FM SYNC and RX FM CLK. RX FM SYNC is used as an input strobe signal for the serial analog-to-digital converter (ADC) 270 to initiate a conversion cycle. RX
FM CLK is used as an input clock signal for clock FM control of FM reception data from serial ADC 270.

The FM DEM signal enters the analog section 197, which separates the signal into two different signal streams, a voice data signal and a wideband data signal stream. The audio data signal is sent to an audio signal unit, and the wideband data signal is sent to a wideband data demodulator unit. The audio data signal sent to the audio signal section is simply filtered by the low-pass filter 260 and then converted to a digital signal by the serial ADC 270. Under the control of the RX FM SYNC signal, the output of the serial ADC 270 is sent to the CMC 22 (FIG. 1) for further processing of the audio data signal.

The wideband data signal is sent to a wideband demodulation unit and then converted into a digital signal.
During the digital conversion process, noise and errors injected into the wideband data signal during the transmission and reception process are removed. The noise and error introduced into the wideband data signal is reduced by the noise and error rejection (N
ER) is removed by the circuit 250. After all noise and errors have been removed and the analog wideband data signal has been converted to a digital signal, the digital wideband data signal is converted to a wideband data demodulator 2.
Sent to 40. Wideband data demodulator 240
Processes the digital wideband data signal and outputs as wideband data (WBDATA) as output processed wideband data flag (WBDATA FLAG) regarding the validity of WBDATA and wideband data clock (WBDATA). WB DATA CL
K). WB DATA is the actual wideband data transmitted with the audio data signal. The WB DATA FLAG is a flag that specifies whether WB DATA is valid.
TA CLK provides timing information regarding WBDATA data boundaries. The WB DATA FLAG and WB DATA CLK are actually generated by the wideband data demodulator 240 (FIG. 2) from the decoded wideband data sequence.

Referring to FIG. 3, FIG.
E18 (FIG. 2) of the wideband data demodulator 240
It is a block diagram. Wideband data demodulator 240
The input to is digitized from NER250 (Figure 2)
Demodulated and demodulated FM signal (FM IN), and appropriate
Data, which is the system clock divided into operating frequencies
Data clock (CLK). FM IN and C
LK is an input to the synchronization circuit 300. Synchronous circuit 30
0 means that the FM_IN signal is processed by the gate, IN is C
Check that it matches the LK input. Consistent
FM The IN signal has three different circuit blocks, namely
The wideband data clock generator 32
0, wideband data generator 330, and
Sent to wideband data flag generator 340
Can be The above wideband data generator 330
Is, as its input, a matching FM Receives IN signal
Data to generate wideband data
Decode a column. Other than actual wideband data generation
In addition, the wideband data generator 330
Generating an indicator 331, the quality indicator
Is the wideband data flag generator 340
Sent to The quality indicator 331 is itself
The accuracy of wideband data
Of the wideband data generator 330
It is a function of reality. The quality indicator 331 is wide
Sent to the band data flag generator 340
You. Wideband data flag generator 340
From the wideband data generator 330
W indicating whether wideband data is valid
In order to generate BDATA FLAG, the quality indicator
Data 331 and matching FM Use IN signal
I do.

The wideband data clock generator 320 has as input an FM matched from the synchronization circuit 300. IN signal and low bandwidth counter 310
Receives a set of control signals / counter values from In this regard, wideband data demodulator 240 can operate in two modes, a low bandwidth mode and a high bandwidth mode. Low bandwidth counter 310
Provides compensation to ensure that the appropriate wideband data clock is generated when the wideband data demodulator 240 is operating in the low bandwidth mode. FM matching By using the IN signal and a set of control signals / counter values from the low bandwidth counter 310, the wideband data clock generator 32
0 is embedded in the wideband data before transmission,
Generate a wideband data clock corresponding to the transmission clock.

Referring to FIG. 4, this is a block diagram of the wideband data clock generator 320 of the wideband data demodulator 240 (FIG. 3). The input to the wideband data clock generator 320 is a digital wideband data stream (FM). IN), a system clock (CLK), and a bandwidth selector (BW-SEL). The CLK input is a wideband data clock generator 32.
0 circuit, while the BW-S
The EL input, either high bandwidth or low bandwidth, specifies the mode of operation of the wideband data clock generator 320. FM The IN data stream is sent to three binary counters, a centroid counter 400, a quadrature 1 counter 410, and a quadrature 2 counter 420. Each counter is designated to count the value of a digital data stream during a particular portion of one data period. After each count, the counters 400, 41
0 and 420 compare the value to each predetermined threshold. The predetermined threshold is preferably
Each counter 400, 410 and 420 counts, F
M It is preferably a number representing about half the number of IN samples, and each counter 400, 410 and 420 preferably counts half of the samples during one data period.

For illustrative purposes, assume that there are 32 samples for each data period. Therefore, each counter 400, 410 and 420 counts 16 samples of the data period at a predetermined threshold of 8. Based on the result of the above comparison, each counter will draw a "greater" line if the value is greater than 8, a "less" line if less than 8, and a Activate both wires. State machine 440 uses the data from counters 400, 410 and 420 to adjust the timing and phase angle of the wideband data clock.

The centroid counter 400 counts digital stream values for samples near the center of one data period, ie, near the expected position of the data transmission clock edge. The quadrature phase 1 counter 410
The numerical value of the digital data sequence for the sample immediately after the start of one data period is counted. On the other hand, the quadrature phase 2 counter counts the numerical value of the digital data sequence for the sample immediately after the center of the data period.
In the case of the first preferred embodiment of the invention, the quadrature 1
The counter 410 starts counting data samples a few samples after the beginning of the data period to help reliably count changes in the data transmission clock edge.

Referring to FIG. 5, this figure shows one data period of a wideband data signal and a centroid counter, quadrature 1 counter and quadrature 2 counter 400, 410, and 420 (all FIG. 4).
FIG. Line 500 is
The normal data period is shown, together with the change in the data transmission clock, in the middle of the normal data period (divided into four quadrants). Window 510 shows a time window in which centroid counter 400 (FIG. 4) counts digital data samples. On the other hand, time window 5
20 and 530 are quadrature 1 counters, respectively.
And a time window for quadrature 2 counters 410 and 420. Windows 510, 520 and 5
30 is constant and does not change from one another, but the exact position between the windows 510, 520 and 530 and the line 500 for the data period is determined by the wideband data clock generator 320 (FIG. 3). When adjusted, it changes accordingly. Referring again to FIG. 4, quadrature 1 counter 410 and quadrature 2 counter 420 send their outputs to state machine 440, as well as their outputs to comparator 430. The comparator 430 has two counters:
The values of the quadrature phase 1 counter 410 and the quadrature phase 2 counter 420 are compared, and the comparison result is used as the state machine 440
Send to The state machine 440 has three counters 400,
410, 420 and comparator 430, and BW
After receiving input from SEL, the state machine 440 performs a control process (not shown) to adjust the timing and phase angle of the wideband data clock, if necessary.

Referring to FIG. 6, there is shown a flowchart 599 for explaining the state machine 440 (FIG. 4) for adjusting the timing and phase angle of the wideband data clock. The state machine 440 (FIG. 4) executes once every wideband data period, after the three counters 400, 410 and 420 (all FIG. 4) have finished their respective counting and comparing. As previously described, the state machine 440 (FIG. 4) comprises a centroid counter 400 (FIG. 4), a quadrature 1 counter 410 (FIG. 4), a quadrature 2
Inputs are received from counter 420 (FIG. 4), comparator 430 (FIG. 4), and BW-SEL. Each of the three counters 400, 410 and 420 (all FIG. 4) sends two control lines to the state machine 440 (FIG. 4). If the value of the counter is greater than 8, the counter activates the "greater" control line; if the value of the counter is less than 8, the counter activates the "less than" control line and the counter is activated. If the number is equal to 8, activate both control lines.

The state machine 440 (FIG. 4) begins at decision block 600. In this block, the state machine 440 (FIG. 4) stores the centroid counter 4
Check whether the number counted at 00 (FIG. 4) is equal to a predetermined threshold value, eight. If the value of the centroid counter 400 (FIG. 4) is equal to eight, the state machine 440 (FIG. 4) will determine the timing and phase angle of the wideband data clock (state put block 605). Aborts execution without adjusting. Centroid cycle 400 (Fig. 4)
Is less than 8, the state machine 440
(FIG. 4) similarly checks the value of quadrature 2 counter 420 (FIG. 4) at decision block 610. If the value of quadrature 2 counter 420 (FIG. 4) is greater than 8, then adjust the timing and phase angle of the wideband data clock and execute after one sampling time period, as shown in block 615. Abort. The adjustment of the timing and phase angle of the wideband data clock is controlled by three counters 400, 410 and 42.
This is done by moving the position of 0 (all FIG. 4). For example, counters 400, 410 and 420
By relocating the positions (all FIG. 4) by one sampling time period, the wideband data clock generated from the data supplied by the counter is temporally moved back by one sampling time period. In a first preferred embodiment of the present invention, each wideband data period is sampled 32 times. Therefore, the wideband data clock generator 32
0 (FIG. 4) can fine tune the timing and phase angle of the wideband data clock by 1/32 of one period at a time. Quadrature phase 2 counter 420
If the value of (FIG. 4) is not greater than 8, state machine 440 (FIG. 4) checks the value of quadrature 1 counter 410 (FIG. 4) at decision block 620.
If the value of quadrature phase 1 counter 410 (FIG. 4) is not less than 8, state machine 440 (FIG. 4) advances the timing and phase angle of the wideband data clock by one sampling time period. Adjust and abort execution, as indicated by block 635. If the value of quadrature 1 counter 410 (FIG. 4) is less than 8, state machine 440 (FIG. 4) returns to decision block 6
At 25, the value of the quadrature phase 2 counter 420 (FIG. 4) is
Check if it is less than 8. If the value of the quadrature 2 counter 420 (FIG. 4) is not less than 8, the state machine 440 (FIG. 4) will be one sampling time period later to reduce the timing and phase angle of the wideband data clock. Adjust and stop execution.
If the value of quadrature 2 counter 420 (FIG. 4) is less than 8, state machine 440 (FIG. 4) determines at decision block 630 that quadrature 1 counter 410 (FIG. 4)
And the two values counted by the quadrature phase 2 counter 420 (FIG. 4). The actual comparison of the two numbers is made by comparator 430 (FIG. 4) and the result is sent to state machine 440 (FIG. 4). The value of the state machine 440 (FIG. 4) is
If less than or equal to (FIG. 4), state machine 440 (FIG. 4) adjusts the timing and phase angle of the wideband data clock late by one sampling time period and aborts execution. I do. Quadrature phase 1
If the value of the counter 410 (FIG. 4) is greater than the value of the quadrature 2 counter 420 (FIG. 4), the state machine 440 (FIG. 4) will advance one wide sampling clock cycle to the wideband data clock. Adjust the timing and phase angle of and stop the execution.

At decision block 600, if the value of centroid counter 400 (FIG. 4) is greater than 8, state machine 440 (FIG. 4) returns to decision block 6
At 40, the value of the quadrature phase 2 counter 420 (FIG. 4) is checked. If the value of quadrature 2 counter 420 (FIG. 4) is less than 8, state machine 440 (FIG. 4) adjusts the timing and phase angle of the wideband data clock by one sampling time period later. And abort the run. Quadrature phase 2 counter 420
If the value of (FIG. 4) is not less than 8, state machine 440 (FIG. 4) checks at decision block 645 the value of quadrature 1 counter 410 (FIG. 4).
If the value of the quadrature phase 1 counter is not greater than 8, the state machine 440 (FIG. 4) adjusts the timing and phase angle of the wideband data clock, one sample time period later, and executes. Abort.
If the value of quadrature 1 counter 410 (FIG. 4) is greater than 8, state machine 440 (FIG. 4) checks at decision block 650 the value of quadrature 2 counter 420 (FIG. 4). If the value of quadrature 2 counter 420 (FIG. 4) is not greater than 8, state machine 440 (FIG. 4) will delay one sampling time period to reduce the timing and phase angle of the wideband data clock. Adjust and stop execution. If the value of quadrature 2 counter 420 (FIG. 4) is greater than 8,
The state machine 440 (FIG. 4)
When sent from (FIG. 4) to the state machine 440 (FIG. 4), at decision block 655, the quadrature 1 counter 410
(FIG. 4) and the two values counted by the quadrature 2 counter 420 (FIG. 4). The value of the quadrature phase 1 counter 410 (FIG. 4) is
If it is less than or equal to (Figure 4)
The state machine 440 (FIG. 4) adjusts the timing and phase angle of the wideband data clock earlier by one sampling time period and stops executing. If the value of the quadrature 1 counter 410 (FIG. 4) is greater than the value of the quadrature 2 counter 420 (FIG. 4), the state machine 440 (FIG. 4) is one sampling time period later and Adjust the timing and phase angle of the data clock and stop execution.

Referring to FIG. 7, which illustrates exemplary timing and phase angle measurements performed by the wideband data clock generator 320 (FIG. 4) according to a first preferred embodiment of the present invention. It is a drawing which shows adjustment. Line 700 is the wideband data demodulator 240
FIG. 4 shows a digital wideband data input stream encoded by Manchester encoding as input to FIG. A group of three lines 703 includes three counters 40
0, 410 and 420 (all FIG. 4) show that portion of the wideband data input stream where counting is taking place. Line 706 is the centroid counter 400
(FIG. 4) shows the counted parts, lines 709 and 712
Indicates the portions counted by the quadrature phase 1 counter 410 (FIG. 4) and the quadrature phase 2 counter 420 (FIG. 4), respectively. Group 703 shows the possible initial positions of counters 400, 410 and 420 (all FIG. 4), and thus the possible initial positions of the wideband data clock. When the counter is at the position shown by line 706, the value of the counter is as follows. Centroid counter = 0, Quadrature phase 1 counter =
0, and quadrature 2 counter = 0. Flowchart 5
The counts from state machine 440 (FIG. 4) and counters 400, 410 and 420 (all FIG. 4) executing the algorithm shown in FIG.
As shown at 15, the timing and phase angle of the wideband data clock are adjusted one sample time period later. If the counter is at the position shown by line 715, the value of the counter is: Centroid counter = 0, quadrature 1 counter = 0, and quadrature 2 counter = 1. Within the next data cycle, the counts from counters 400, 410 and 420 (all FIG. 4) are used to indicate to state machine 440, as shown in group 718.
FIG. 4 again adjusts the timing and phase angle of the wideband data clock one sample time period later. If the counter is at the position shown by line 718, the value of the counter is: Centroid counter = 0, quadrature 1 counter = 0, and quadrature 2 counter = 2.
Adjustment of the timing and phase angle of the wideband data clock continues in a similar manner for groups 721-757. However, the counter 40
If 0, 410 and 420 (all FIG. 4) are in the positions shown in group 759, the value of centroid counter 400 (FIG. 4) will be equal to eight. Therefore, execution of the algorithm shown in flowchart 599 (FIG. 5) immediately goes to block 605, the status maintenance block. This means that wideband data
This means that the clock has been correctly adjusted for the wideband data input stream and no further adjustment is required.

The embodiments of the present invention described so far are as follows:
Although a preferred embodiment, one of ordinary skill in the art, in view of the present specification, will be able to come up with other embodiments of the method and apparatus of the present invention. Therefore, it should be understood that various changes and modifications can be made without departing from the spirit and scope of the invention and that the scope of the invention is limited only by the following claims. . Furthermore, corresponding structures, materials, acts, and all means or steps and functional elements, which are described in the above claims, are combined with other claimed elements as expressly recited in the claims. Includes all structures, materials or acts that, in combination, perform the claimed functions.

[Brief description of the drawings]

FIG. 1 shows a CDMA according to a first preferred embodiment of the present invention.
It is a block diagram of a radio telephone.

FIG. 2 is a block diagram of the analog front end (AFE) circuit of FIG. 1 according to a first preferred embodiment of the present invention.

FIG. 3 is a block diagram of the wideband data demodulator of FIG. 2 according to the first preferred embodiment of the present invention;

FIG. 4 is a block diagram of the wideband data clock generator circuit of FIG. 3 according to a first preferred embodiment of the present invention.

FIG. 5 is a diagram illustrating a relationship between a counter window and a received data signal according to the first preferred embodiment of the present invention.

FIG. 6 is a flowchart illustrating the configuration of a process used to adjust the wideband data clock of the present invention.

FIG. 7 is a diagram illustrating timing and phase angle adjustments performed by a wideband data clock generator of the wideband data demodulator of FIG. 2 according to a first preferred embodiment of the present invention.

Claims (40)

[Claims] 1. A system for adjusting a phase angle of a clock signal, wherein each of the plurality of counters determines a number of samples having a particular logical value over a portion of one period of the data signal. And a plurality of counters each comprising a counter configured to transmit a comparison signal indicating a comparison between a predetermined threshold value and the number to a plurality of counters corresponding to different portions of the cycle. And a phase state machine configured to receive the comparison signal from the plurality of counters and adjust a phase angle of a clock signal based on the comparison signal. 2. The system of claim 1, wherein said particular logical value is a binary one. 3. The system of claim 1, wherein the comparison signal indicates whether the number exceeds a predetermined number. 4. The system according to claim 1, wherein said predetermined threshold value corresponds to approximately one-half of the number of samples located in said part of said period. 5. The system of claim 3, wherein said number of samples located in said portion of said period corresponds to approximately one-half of the number of samples in said period. 6. A method for adjusting a phase angle of the clock signal, the method comprising: determining a number of samples having a particular logical value for each of a plurality of different portions of a data signal period; A method comprising: comparing the number from each different part to a predetermined threshold; and adjusting a phase angle of the clock signal based on the comparing step. 7. The method of claim 6, wherein the particular logical value is a binary one. 8. The method of claim 6, wherein said comparing step further comprises determining whether said number of samples having said particular logical value exceeds said predetermined number. Method. 9. The method of claim 6, wherein the predetermined threshold value corresponds to one half of a sum of samples located in each of the plurality of different portions. 10. The method of claim 9, wherein the sum of the samples corresponds to one half of the total number of samples in the data signal period. 11. A means for determining a number of samples having a particular logical value for a plurality of different portions of a data signal period, the number from the plurality of different portions, and a predetermined threshold. A system for adjusting the phase angle of the clock signal, comprising: means for comparing a value with a value; and means for adjusting a phase angle of the clock signal based on the comparing step. 12. The system of claim 11, wherein the particular logical value is a binary one. 13. The system of claim 11, wherein said comparing means further comprises: determining whether said number of samples having said particular logical value exceeds said predetermined numerical value. A system comprising means. 14. The system according to claim 11, wherein said predetermined threshold value corresponds to one half of the total number of samples located in each of said plurality of different portions. 15. The method of claim 14, wherein said total number of samples corresponds to one-half of a number of samples in said data signal period. 16. A system for adjusting the phase angle of a data clock recovered from a received data signal, comprising: a digital sampling device for sampling the received data signal; and the received data signal. In the first part of one cycle of
Configured to count a first number of samples of the received data signal having a particular logical value, and wherein the first number exceeds a first predetermined threshold. A first counter configured to transmit a first signal, indicating whether the received data signal has the particular logical value in a second portion of the period of the received data signal, Transmitting a second signal, configured to count a second number of samples, and indicating whether the second number exceeds a second predetermined threshold. A second counter configured, wherein the third portion of the period of the received data signal has the particular logical value, and counts a third number of samples of the received data signal. And the third number is a third predetermined number. A third counter configured to transmit a third signal indicating whether the threshold value has been exceeded, and the first signal, the second signal, and the third signal. And a phase state machine configured to receive and configured to adjust the phase angle based on the first signal, the second signal, and the third signal. 17. The system of claim 16, wherein the particular logical value is a binary one. 18. The system of claim 16, wherein a number of the first, second, and third predetermined thresholds are matched. 19. The system of claim 16, wherein said first portion of said period is located at a central portion of said period, and a second portion of said period is located at said first portion of said period. A sample comprising a sample detected prior to the detection of the contained sample, wherein the third part of the cycle is the sample detected after the sample contained in the first part of the cycle is detected. Including system. 20. The system of claim 19, wherein said first portion of said period, said second portion of said period, and said third portion of said period comprise a total number of samples in said period. System with multiple samples corresponding to one half of 21. The system of claim 19, wherein a portion of the first portion of the cycle overlaps a second portion and the third portion. 22. The system of claim 20, wherein the number of the first, second, and third predetermined thresholds corresponds to about one-fourth of the total number of samples in the period. system. 23. The system according to claim 21, wherein said second portion and said third portion of said period partially overlap. 24. The system of claim 21, wherein the second portion and the third portion of the cycle do not overlap. 25. A method for adjusting the phase angle of a recovered data clock signal, comprising the steps of: receiving a data signal having a period; and having a specific logical value in a first portion of the period. Counting a first number of samples; counting a second number of samples having a particular logical value in a second part of the period; Counting a third number of samples having a value; comparing the first number to a first predetermined threshold; and Comparing the third number with a third predetermined threshold value; and adjusting the time and phase angle of the data signal based on the comparing step. And a method comprising: 26. The method of claim 25, wherein the particular logical value is a binary one. 27. The method of claim 25, wherein the first part of the period is located at a central part of the period, and the second part of the period is the first part of the period. Wherein the third portion of the period is detected after the sample included in the first portion of the period is detected, including the sample detected before the sample is detected. Methods involving samples. 28. The method of claim 27, wherein the first portion of the period, the second portion of the period,
And the third portion of the period comprises a number of samples of the received data signal corresponding to one half of the sum of the samples in the period. 29. The method of claim 27, wherein a portion of the first portion of the period overlaps a second portion and the third portion. 30. The method according to claim 28, wherein said first, second and third predetermined thresholds correspond to about one-fourth of said total number. 31. The method according to claim 29, wherein the second portion and the third portion of the period partially overlap. 32. The method of claim 29, wherein the second portion and the third portion of the period do not overlap. 33. A system for adjusting the phase angle of a recovered data clock signal, comprising: means for receiving a data signal having a period; Means for counting a first number of samples having a value; and means for counting a second number of samples having a particular logical value in a second portion of the period. Means for counting a third number of samples having a particular logical value, and means for comparing said first number with a first predetermined threshold. Means for comparing the second number to a second predetermined threshold; and means for comparing the third number to a third predetermined threshold. Adjusting the time and phase angle of the data signal based on the comparing step; System and means. 34. The system of claim 33, wherein the particular logical value is a binary one. 35. The system of claim 33, wherein the first part of the cycle is located at a central part of the cycle, and the second part of the cycle is the first part of the cycle. A sample detected before the sample is detected, wherein the third part of the cycle is included in the first part of the cycle, detected after the sample is detected. System containing the processed samples. 36. The system according to claim 35, wherein the first portion of the period, the second portion of the period, and the third portion of the period comprise: 1/2 of the total number of samples in the period
A system containing a large number of samples corresponding to. 37. The system of claim 35, wherein a portion of the first portion of the period overlaps a second portion and the third portion of the period. 38. The system according to claim 36, wherein the number of said first, second and third predetermined thresholds corresponds to about one fourth of said total number. 39. The system of claim 37, wherein the second portion and the third portion of the cycle partially overlap. 40. The system of claim 37, wherein the second and third portions of the cycle do not overlap.