JP2000031827A - Current output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-accuracy current output circuit, which does no depend on a current amplification factor, capable of reducing influences caused by the variations of transistors. SOLUTION: Through (n) pieces of switching circuits to be controlled by digital codes Dn, Dn-1...D2 and D1, (n) pieces of weighted currents are selected and the total value of selected currents is found by a current source IC 21. Corresponding to the total current, a corrected current obtd. by regulating a current value with the magnification set corresponding to a current amplification factor hfe of the transistor is generated as the base current of a transistor Q15 and added to the total current. Thus, the error caused by the base current of the transistor can be corrected, the error of an output current is reduced and the error caused by the low current amplification factor and the variations of the current amplification factor can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a current addition type digital / analog conversion circuit (hereinafter, referred to as a DAC) to reduce the influence of variations in elements and to output a current with high accuracy in accordance with a digital code. And a current output circuit.

[0002]

2. Description of the Related Art In a current addition type DAC, a current weighted according to each bit of an input digital code is generated, the generated currents are added, and the added current is obtained by digital / analog conversion. It is output as an analog signal. Further, by converting the added current into a voltage signal, an analog voltage signal having a level corresponding to the digital code can be obtained.

FIG. 6 shows an example of a commonly used current addition type DAC. The DAC has n (n is an integer of 1 or more) digital codes Dn, Dn-
1, ..., and outputs a current I _out corresponding to D2, D1. In the digital codes Dn, Dn-1,..., D2 and D1, Dn is the most significant bit MSB and D1 is the least significant bit L
SB respectively. The voltage level of the signal indicating each bit corresponds to data “0” or “1”. For example, when the LSB is "1", the bit D1 is kept higher than the voltage _VTH . Conversely, when LSB is “0”, bit D
1 is a level lower than the voltage V _TH , for example, the ground potential GND.
Is held. Other bits of the digital code are set similarly.

As shown in the figure, the current value of a current source IS1 is represented by I
Then, the emitter current of the transistor Q4 corresponding to the bit D1 of the LSB is I / 2 ⁿ , and the emitter current of the transistor Q4 corresponding to the bit D2 is I / 2 ⁿ⁻¹ , which corresponds to the bit Dn of the MSB Transistor Q1
Has an emitter current of I / 2. Note that the emitter current of the transistor Q5 is the same as the emitter current of the transistor Q4. Thereby, the transistors Q1, Q
The sum of the emitter currents of 2,..., Q5 becomes equal to the current I of the current source IS1.

The transistors Q6 and Q7, Q8 and Q9, Q
10 and Q11 or Q12 and Q13 each constitute a differential circuit. Digital code Dn, Dn-
The current path in each differential circuit is switched in accordance with the value of each bit of 1,..., D2, D1. As a result, the added current Ia flowing through the current source IS21 becomes a current corresponding to the digital codes Dn, Dn-1,..., D2, D1.

For example, digital codes Dn, Dn-
Of the bits 1, 1,..., D2 and D1, when only the Dn of the MSB is “1” and all the other bits are “0”, in the differential circuit including the transistors Q6 and Q7, the transistor Q6 is turned on and the transistor Q7 is turned on. Is turned off. Since the current I / 2 of the transistor Q1 flows through the transistor Q6, it is added to the addition current Ia. At this time, the addition current Ia = I / 2, and the output current Ia of the operational amplifier OPA is
_out becomes 0. Other bits Dn-1,...
Similarly, in D2 and D1, a current corresponding to the value of each bit is added to the addition current Ia. As a result, the digital codes Dn, Dn-1,..., D2, D1 have the minimum value “000”.
.. 00, a negative maximum current (−I / 2) is output from the operational amplifier OPA, and a positive maximum current (I / 2−I) is output from the operational amplifier OPA according to the maximum value “111.
/ 2 ⁿ ) is output. As described above, when the digital code is “100... 00”, the output current of the operational amplifier is 0.

[0007] Since the current sources IS21 and IS22 form a current mirror, the added current Ia is output from the current source IS22 and input to the operational amplifier OPA. That is, the output current I _out of the operational amplifier OPA is equal to the difference current (Ia−I / 2) between the addition current and the current of the current source IS3. The output voltage _Vout of the operational amplifier OPA is controlled by the output current _Iout .

FIG. 7 is an equivalent circuit showing the principle of the DAC shown in FIG. That is, the digital codes Dn, Dn-
, D2, D1 and n switches SWn, SWn−1,.
The current I / 2, I / 2 of n weighted by SW1
^{2, ..., I / 2 n} -1, I / 2 n are selected and input to the current adder ADD1. The difference current between the addition current Ia obtained by the current adder ADD1 and the fixed current I / 2 is obtained by the current subtractor ADD2, and the difference current (I _out = I
a-I / 2) is output. Here, the switches SWn,
SWn-1,..., SW2 and SW1 have the functions of transistors Q6 and Q7, Q8 and Q9, Q10 and Q1, respectively.
1 and a differential circuit constituted by Q12 and Q13.

[0009]

By the way, the above-mentioned D
In the current output circuit used for AC, the addition current is obtained based on the collector current of each transistor.
There is a disadvantage that an error is caused by the base current of each transistor.

[0010] For example, considering the transistor Q1 corresponding to Dn of the MSB, the emitter current i _e is I / 2. Here, the grounded emitter current amplification factor of the transistor Q1 (hereinafter, simply referred to as current amplification factor) as the h _fe, the base current i _b, when the collector and i _c, the collector current i _c is obtained by the following equation.

[0011]

[Number 1] _{i c = i e -i b =} (1-1 / (1 + h fe)) I / 2 ... (1)

When transistor Q6 turns off, its emitter current is equal to the collector current _{ic of} transistor Q1 shown in equation (1). Assuming that the current amplification factor of the transistor Q6 is h _fe similarly to the transistor Q1, the collector current of the transistor Q6, that is, the current Ir added to the addition current Ia is obtained by the following equation.

[0013]

## EQU2 ## Ir = (1-1 / (1 + h _fe )) ² I / 2 (2)

Digital codes Dn, Dn-1,..., D
Of 2, D1, when MSBDn only is "1", although ideally the output current becomes zero, the output current I _out of the current output circuit shown in FIG. 6 can be calculated by the following equation.

[0015]

I _out = (− 2 / (1 + h _fe ) + (1 / (1 + h _fe ) ² )) I / 2 (3)

In the conventional current output circuit shown in FIG.
Assuming that an ideal addition current based on the digital codes Dn, Dn-1,..., D2, D1 is Id, an error δ of the addition current caused by the current amplification factor of the transistor is expressed by the following equation.

[0017]

Δ = (− 2 / (1 + h _fe ) + (1 / (1 + h _fe ) ² )) Id (4)

FIG. 8 shows a 4-bit digital code D
FIG. 7 is a diagram showing a comparison between a current value output by the current output circuit shown in FIG. 6 and an ideal output current according to D4, D3, D2, and D1. It is assumed that the current amplification factor h _fe of all the transistors in FIG.

As shown in FIG. 8, when the digital code is "0000", the addition current is 0 and the output current I
_out becomes I / 2. In this case, there is no error in the output current because no current is added. As the digital code increases, the error in the output current I _out also increases. FIG. 9 shows the equivalent circuit of FIG. 6 when the influence of the base current of the transistor, which is the cause of the error, is considered. As described above, in the current output circuit used in the conventional DAC, the current amplification factor h _fe of the transistor affects the accuracy of the output current, and when a transistor having a low h _fe is used, or when the current amplification factor h _fe of the transistor is low. When the variation is large, there is a disadvantage that the accuracy of the DAC is reduced.

The present invention has been made in view of the above circumstances, and an object of the present invention is to improve the accuracy of a current output circuit used in a DAC and reduce the effects of variations in transistors constituting the current output circuit. Another object of the present invention is to provide a current output circuit independent of a current amplification factor.

[0021]

In order to achieve the above object, a current output circuit according to the present invention comprises a first transistor in which an emitter current flows through an emitter based on a predetermined bias condition, and a control signal applied to a base. , An emitter is connected to the collector of the first transistor, a predetermined reference voltage is applied to a second transistor and a base whose collector is connected to a first node, and the emitter is connected to the first transistor.
A third transistor connected to the collector of the first transistor and having the collector connected to the power supply voltage;
A first current source connected to the first node and generating an output current in accordance with the current flowing through the first node; and a current from the first current source being connected to a common emitter current of the first and second transistors. A correction circuit that adjusts at a ratio set according to the amplification factor (β) and feeds back the adjusted current as a correction current to the first node.

Further, in the current output circuit of the present invention, a first transistor in which an emitter current flows to an emitter based on a predetermined bias condition, and a control signal are applied to a base,
An emitter is connected to a collector of the first transistor, a second transistor having a collector connected to the first node, a predetermined reference voltage applied to a base, and an emitter connected to a collector of the first transistor. And a third transistor having a collector connected to the power supply voltage, and setting a bias condition of the first transistor so that n weight currents given a predetermined weight are added to the control signal. A first current source connected to the first node for generating an output current in response to a current flowing through the first node; The current of the first current source is adjusted at a ratio set in accordance with the common emitter current amplification factor (β) of the first and second transistors, and the current obtained by the adjustment is supplemented. And a correction circuit for feeding back to the first node as a current.

In the present invention, preferably, the current correction circuit includes a second current source for supplying a current obtained by multiplying the current of the first current source by a predetermined multiple, for example, twice. And a base connected to the first node. The output current of the first current source is changed according to a total current of a base current and a weight current output from the n bias current generating circuits. A fourth transistor to control.

Further, in the present invention, preferably, the n weight currents generated by the n weight current generation circuits are weighted by a power of two, and the first, second and second weight currents are generated. The four transistors are controlled so that their common emitter current amplification factors are substantially equal.

According to the present invention, under a predetermined bias condition,
For example, a current is generated by a plurality of transistors to which a predetermined bias is applied between the base and the emitter. By controlling the size of the emitter region of these transistors, the emitter current of each transistor is
For example, it is weighted to a power of two. The collector current of each transistor is selected by a switching circuit composed of the second and third transistors according to a control signal applied to the base of the second transistor and a reference voltage applied to the base of the third transistor. Then, the selected weight current is output to the first node. The current of the first current source is controlled accordingly.

In accordance with the current of the first current source, a correction current adjusted by a ratio set according to the grounded emitter current amplification factor of the first and second transistors is generated by the correction circuit, and Returned to the node. That is, the current flowing through the first current source is an addition current of the selected weight current and the correction current. Therefore, an error in the output current caused by the base currents of the first and second transistors is corrected, and a highly accurate current output circuit can be realized.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a current output circuit according to the present invention. As shown in the figure, the current output circuit of the present embodiment includes n-bit digital codes Dn, Dn−1,
, D2, and D1, the weighted n currents are switched, and the selected currents are added and output.

As shown, transistors Q1, Q2,
, Q5 generate currents I / 2, I / 2 ² ,..., I / 2 ⁿ⁻¹ , I / 2 ⁿ weighted by a power of 2, respectively. That is, these transistors constitute a current generating circuit for generating a weighted current. The size of the emitter region of each transistor is set according to the desired weighting current. For example, if the emitter size of the transistor Q5 and s _0, the emitter size of the transistor Q4 2s _0, the emitter size of the transistor Q1 is set respectively 2 ^n-1 s _0.

, R5 are connected to the emitters of the transistors Q1, Q2,..., Q5, respectively. Assuming that the resistance value of these resistance elements is 2r,
The resistance values of the resistance elements R6, R7, R8 are set to r.
By setting the resistance value of each resistance element in this way,
All the transistors Q1, Q2,..., Q5 have the same base-emitter voltage. Therefore, the emitter current of the transistors Q1, Q2,..., Q5 is determined by the size of the emitter region of each transistor. Since the sizes of the emitter regions of the transistors Q1, Q2,..., Q5 are set to the power of two as described above, the emitter currents of these transistors are also weighted to the power of two.

The collector current of each of the transistors Q1, Q2,..., Q5 is switched by a switch composed of a differential circuit. The changeover switch selects a current according to the digital codes Dn, Dn-1,..., D2, D1, and the selected current is added to the current Ia.
The output current I _out is controlled according to the addition current Ia.

A switching circuit comprising transistors Q6 and Q7 is connected to the collector of transistor Q1.
The emitters of the transistors Q6 and Q7 are connected to each other, and the connection point is connected to the collector of the transistor Q1. The collector of transistor Q6 is connected to node ND1, and the collector of transistor Q7 is connected to power supply voltage V _CC . The bit Dn is connected to the base of the transistor Q6.
And the bias voltage V _TH is applied to the base of the transistor Q7. When bit Dn indicates data "0", its voltage level is lower than bias voltage _VTH , and is held at, for example, the ground potential GND level. Conversely, when bit Dn indicates data "1", the voltage is It is kept higher than the bias voltage V _TH .

As described above, when the bit Dn is "0",
In the differential circuit including the transistors Q6 and Q7, since the transistor Q6 is turned off and the transistor Q7 is turned on, the collector current of the transistor Q1 is not added to the addition current Ia. Conversely, when bit Dn is "1", transistor Q
6 turns on and Q7 turns off, so that the collector current of the transistor Q1 is added to the addition current Ia.

As in the case of the bit Dn described above, the transistors Q in response to the other bits Dn-1,.
2, Q3 and Q4 are switched by a differential circuit including transistors Q8 and Q9, Q10 and Q11 and Q12 and Q13, respectively, and the selected current is added to the addition current Ia. Since the emitter current of transistor Q5 is set to I / 2 ⁿ like the emitter current of transistor Q4, transistors Q1 and Q
The emitter currents of 2,..., Q5 total I and become equal to the current value of the current source IS1.

The transistors Q6, Q8,..., Q10, Q
Twelve collectors are both connected to the node ND1. A current source IS2 between the node ND1 and the power supply voltage V _CC
1 is connected. The current sources IS21, IS22
And IS23 constitute a current mirror, and an addition current Ia flows through each current source. Current source IS31
And the current source IS22 are connected in series, so that the addition current Ia also flows through the current source IS31. Further, the current source IS31 and the current source IS32 constitute a current mirror, and the current of the current source IS32 is set to twice the current of the current source IS31 in the current mirror. That is, the current 2Ia flows through the current source IS32.

The base of transistor Q15 is connected to node ND.
Connected to one, the collector is connected to the power source voltage V _CC, an emitter connected to a current source IS32. The current Ia of the current source IS23 and the current source IS are supplied by the operational amplifier OPA1.
4 is output as a difference current from the current (I / 2). That is, the output current I _out is (Ia−I / 2).

Here, transistors Q1 to Q4 and Q
Similarly, it is assumed that the current amplification factors of 6 to Q12 are all _hfe . In response to this, assuming that the total value of the currents selected by the switching circuit is I _a0 , the current I a is _calculated based on the equation (2).
_a0 is obtained by the following equation.

[0037]

I _a0 = (1-1 / (1 + h _fe )) ² Id (5)

In the equation (5), Id is the transistor Q
It is the total value of the transistor emitter current selected from 1 to Q4. As can be seen from equation (5), ideally, it is most desirable that the total current I _a0 coincides with the total value Id of the emitter currents of the selected transistors. However, the transistors Q1 to Q4 and the transistors Q6, Q8,
Due to the influence of the base currents of Q10 and Q12, the actually obtained total current I _a0 is the current amplification factor h _{fe of} each transistor.
It fluctuates by If the transistor current amplification factor h _fe is small or if the transistor current amplification factor h _fe varies, the error of the total current I _a0 increases.

In this embodiment, the current sources IS31, I
The current mirror composed of S32 and the transistor Q1
5 is provided to correct for an error generated in the total current _Ia0 . That is, a current correction circuit is constituted by the current mirror including the current sources IS31 and IS32 and the transistor Q15.

In the current correction circuit, the transistor Q1
Since the emitter current of No. 5 is 2Ia, its base current Ib is obtained by the following equation.

[0041]

Ib = (1 / (1 + h _fe )) 2Ia (6)

The addition current Ia is the sum of the total current _Ia0 shown in the equation (5) and the base current Ib of the transistor Q15. That is, the following relationship holds.

[0043]

Ia = _Ia0 + Ib (7)

By substituting equations (5) and (6) into equation (7), the following equation is obtained.

[0045]

Ia = (1 + 1 / (h _fe ² -1)) Id (8)

[0046] Here, when _{δ 1 = Id / (h fe} 2 -1), δ 1 is the error of the added current Ia according to the present embodiment. That is, the error of the current output by the current output circuit of the present embodiment is on the order of (1 / h _fe ² ). On the other hand, in the conventional current output circuit shown in FIG.
Assuming that the ideal output current is also Id and that the error in the added current is δ ₂ , δ ₂ is obtained by the following equation based on equation (4).

[0047]

Δ ₂ = (− 2 / (1 + h _fe ) + (1 / (1 + h _fe ) ² )) Id (9)

As shown in equation (9), the error δ ₂ generated in the added current in the conventional current output circuit is of the order of (1 / h _fe ). error [delta] ₁ of the summing current is greatly reduced.

The emitter current of the transistor Q15, ie, the current of the current source IS32, is set according to the number of base current errors that occur until the selected weight current is added, and is not limited to twice. .

FIG. 2 is a diagram showing an equivalent circuit of the current output circuit of this embodiment shown in FIG. As compared with the equivalent circuit of the conventional current output circuit shown in FIG. 9, current multiplying circuits MUL1 and MUL2 are newly provided between the current adding circuits ADD1 and ADD2. The addition current Ia is amplified twice by the current multiplication circuit MUL2,
The result of multiplication by 1 / (1 + h _fe ) is obtained by UL1, and is fed back to the current addition circuit ADD1. In the equivalent circuit, the function of the current multiplication circuit MUL2 is as shown in FIG.
Is achieved by a current mirror composed of current sources IS31 and IS32, and the function of the current multiplication circuit MUL1 is
This is realized by the transistor Q15 in FIG.

FIG. 3 shows a 4-bit digital code D4, D3, D input by the current output circuit of this embodiment.
2, the output current _Iout obtained according to D1. In FIG. 3, the input 4-bit digital code indicates the output current I _out at each value from the minimum value “0000” to the maximum value “1111”. The current amplification factor h _{fe of} each transistor constituting the current output circuit
Are all 50.

As shown in FIG. 3, the symbols indicating the ideal current output characteristics and the current output characteristics of the present embodiment almost overlap. That is, with the current output circuit of the present embodiment, a current output characteristic substantially matching an ideal current output characteristic can be obtained.
Highly accurate output current can be generated. As shown in equation (8), the error of the added current in the current output circuit of the present embodiment can be reduced to almost (1 / h _fe ² ) order.
Compared with the characteristics of the conventional current output circuit shown in FIG. 8, high-precision current output was realized.

As described above, according to the present embodiment, the digital codes Dn, Dn-1,..., D2, D1
Switches SW1, SW2, controlled according to
.., SWn−1, and SWn, the current of n weighted is selected, and the total value of the selected currents is obtained. An error caused by the base current of the transistor is generated by generating a correction current in which the current amount is adjusted at a magnification set according to the current amplification factor h _fe of the transistor according to the total current and adding the correction current to the total current. to correct. Thereby, the error in the addition current is reduced, and the influence of the error caused by the low current amplification factor and the variation in the current amplification factor can be reduced.

Second Embodiment FIG. 4 is a circuit diagram showing a current output circuit according to a second embodiment of the present invention. As shown in the drawing, the current output circuit of the present embodiment is different from the above-described current output circuit of the first embodiment in the conductivity of the transistor, but the other configurations are almost the same. That is, the npn transistors Q1 to Q5 and Q6 to Q1 in the first embodiment shown in FIG.
5 are the corresponding pnp in the second embodiment.
Replaced by transistors P1-P5 and P6-P15. Accordingly, the bias state of the power supply voltage is newly set, and the direction of the current is different from that of the first embodiment.

As shown, the currents I / 2, 2 weighted by the powers of 2 by the transistors P1 to P5, respectively.
^{I / 2 2, ..., I} / 2 n-1, I / 2 n are generated. As in the first embodiment, the size of the emitter region of each transistor is set according to the desired weighting current that occurs. For example, the emitter size of the transistor P3 is set to twice the emitter size of the transistor P4,
The emitter size of the transistor P1 is
4 is set to 2 ^{n -1} times the emitter size.

Transistors P6 and P7, P8 and P9, P
A switching circuit for switching the collector currents of the transistors P1, P2, P3, and P4 is constituted by 10 and P11 and P12 and P13. Since the current selected by these switching circuits flows through the node ND1, it flows a total current I _a0 of the selected current to the current source IS21. For this reason, the total current I _a0 in the current output circuit of the present embodiment is obtained by Expression (5), similarly to the current output circuit of the first embodiment. In this case, both h _fe the current amplification factor of the pnp transistor P1~P4 and P6, P8, P10, P12 in FIG. 4
Assume that

In this embodiment, the current sources IS31, I
The current mirror composed of S32 and the pnp transistor P15 constitute a current correction circuit for correcting an error of the total current _Ia0 . As shown in FIG. 4, a current mirror is formed by current sources IS21, IS22, and IS23, and an addition current Ia flows through each current source. Since the current sources IS31 and IS22 are connected in series, the current also becomes Ia. In the current mirror constituted by the current sources IS31 and IS32, the current of the current source IS32 is set to twice the current of the current source IS31. That is, the current of the current source IS32 is 2Ia. Here, assuming that the current amplification factor of the pnp transistor P15 is h _fe , the base current Ib is obtained by Expression (6), similarly to the current output circuit of the first embodiment. Similarly, a current source IS constituting a current mirror
Since the current flowing through 21 is obtained by equation (7),
The addition current is also as shown in Expression (8).

The operational amplifier OPA2 allows the current source IS4
, And a difference current I _out1 between the current I / 2 and the addition current Ia is output. Based on FIG. 4, the output current I _out2 is given by the following equation.

[0059]

I _out2 = I / 2−Ia (10)

As described above, in the present embodiment, by providing the current correction circuit, the error current caused by the base current of the transistor can be reduced, and based on the same principle as the current output circuit of the first embodiment. , The error occurring in the added current is reduced to the order of (1 / h _fe ² ).

FIG. 5 is a diagram showing an equivalent circuit of the current output circuit shown in FIG. As shown, the equivalent circuit of the current output circuit of the present embodiment is almost the same as the equivalent circuit of the current output circuit of the first embodiment shown in FIG. However, in the present embodiment, the output current I _out2 is output in a different direction from the output current I _out of the first embodiment. Except for this point, the other points are almost the same as the current output circuit shown in the first embodiment.

[0062]

As described above, according to the current output circuit of the present invention, it is possible to reduce the error of the output current due to the base current of the transistor constituting the current generating circuit for generating the current and the switching circuit for selecting the current. In addition, it is possible to maintain high accuracy of the output current when a transistor having a low current amplification factor is used or when there is a variation in the current amplification factor of the transistor. For this reason, there is an advantage that a highly accurate digital / analog conversion circuit can be configured by the current output circuit of the present invention.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a current output circuit according to the present invention.

FIG. 2 is a diagram showing an equivalent circuit of the current output circuit of FIG.

FIG. 3 is a diagram illustrating output characteristics of the current output circuit of FIG. 1;

FIG. 4 is a circuit diagram showing a second embodiment of the current output circuit according to the present invention.

5 is a diagram showing an equivalent circuit of the current output circuit of FIG.

FIG. 6 is a circuit diagram showing a configuration example of a conventional current output circuit.

FIG. 7 is a diagram showing an equivalent circuit of an ideal current output circuit.

FIG. 8 is a diagram illustrating output characteristics of the current output circuit of FIG. 6;

9 is a diagram showing an equivalent circuit of the current output circuit of FIG.

[Explanation of symbols]

ADD1, ADD2: current addition circuit, MUL1, MUL
2: current multiplying circuit, OPA: operational amplifier, Q1 to Q15
... npn transistors, P1 to P15 ... pnp transistors, R1 to R9 ... resistance elements, IS1, IS3, IS
4 ... current sources, VS1, VS2 ... voltage source, V _CC ... power supply voltage, GND ... ground potential.

Claims (9)

[Claims] A first transistor in which an emitter current flows to an emitter based on a predetermined bias condition; a control signal applied to a base; an emitter connected to a collector of the first transistor; A second transistor connected to the node, a third transistor having a base applied with a predetermined reference voltage, an emitter connected to the collector of the first transistor, and a collector connected to the power supply voltage; A first current source connected to the first node and generating an output current in accordance with a current flowing through the first node; and a current of the first current source is connected to the first and second transistors. A correction circuit that adjusts at a ratio set according to the grounded emitter current amplification factor (β) and feeds back the adjusted current as a correction current to the first node. Current output circuit. 2. The current correction circuit according to claim 1, wherein the emitter is the first
Is connected to a second current source that supplies a current obtained by multiplying the current of the current source by a predetermined multiplier, a base is connected to the first node, and a sum of a base current and a collector current of the second transistor is provided. The current output circuit according to claim 1, further comprising a fourth transistor that controls an output current of the first current source according to a current. 3. The current output circuit according to claim 2, wherein said multiplication factor is twice. 4. The current output circuit according to claim 2, wherein said first, second and fourth transistors are controlled such that their common emitter current gains are substantially equal. 5. A first transistor in which an emitter current based on a predetermined bias condition flows through an emitter, a control signal applied to a base, an emitter connected to a collector of the first transistor, and a collector connected to the first transistor. A second transistor connected to the node, and a third transistor having a base to which a predetermined reference voltage is applied, an emitter connected to the collector of the first transistor, and a collector connected to the power supply voltage. Have
Setting a bias condition of the first transistor to output n weight currents weighted with a predetermined weight to the first node in accordance with the control signal; n bias current generating circuits; A first current source connected to the first node and generating an output current in response to a current flowing through the first node; and a current source of the first current source being connected to a common emitter of the first and second transistors. A current adjustment circuit that adjusts the current at a ratio set according to the current amplification factor (β), and feeds back the adjusted current as a correction current to the first node. 6. The current correction circuit according to claim 1, wherein the emitter is the first type.
Is connected to a second current source that supplies a current obtained by multiplying the current of the current source by a predetermined multiple, a base is connected to the first node, and a base current and an output from the n bias current generating circuits are provided. 6. The current output circuit according to claim 5, further comprising a fourth transistor for controlling an output current of the first current source according to a total current with the weighted current. 7. The current output circuit according to claim 6, wherein said multiplication factor is twice. 8. The current output circuit according to claim 6, wherein said first, second and fourth transistors are controlled so that their common emitter current gains are substantially equal. 9. The current output circuit according to claim 5, wherein the n weight currents generated by said n weight current generation circuits are weighted by a power of two.