JP2000031377A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can have larger memory capacity than conventional chips without increasing the chip size. SOLUTION: Semiconductor chips 11, 12 having connecting parts for connecting the semiconductor integrated circuit and leads 14, 16-18 on both its upper and lower surfaces, and having the upper and lower surfaces only at two opposed sides of four peripheral sides connected with leads, are bonded on the upper and lower surfaces of a base 13. At this time the leads 14, 16 connected to the connecting parts of semiconductor chip 11 on the upper side of the base 13 and the leads 17, 18 connected to the connecting parts of the lower side semiconductor chip 12 are provided perpendicularly to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a structure of a semiconductor device in which a semiconductor chip is packaged with an insulator, and more particularly to a structure of a semiconductor device using a semiconductor chip having semiconductor integrated circuits on both sides.

[0002]

2. Description of the Related Art In the field of computer-related technology in recent years, the storage capacity used is steadily increasing.
Accordingly, the storage capacity of a storage element (memory) including a semiconductor integrated circuit used for storage has been expanded. FIG.
FIG. 4 is a perspective view showing an example of a connection configuration between an internal semiconductor chip and leads in a conventional semiconductor device. The conventional semiconductor device shown in FIG. 4 includes a semiconductor chip 1, leads 2, thin metal wires 3, and a sealing material 4 for them. The semiconductor chip 1 has a memory or the like formed by a semiconductor integrated circuit formed on an upper surface thereof, and a connection electrode (pad) formed on a part of the surface. The lead 2 is a metal terminal that enables connection to the outside of the semiconductor device. Generally, the lead 2 is separated from the lead frame after the semiconductor chip is packaged and becomes a lead. The thin metal wire 3 is a thin metal wire such as gold used for wire bonding. The sealing material 4 is, for example, a molding material such as an epoxy resin or a silicon resin. The structure in which the leads are arranged as shown in FIG. 4 is a structure called a dual in-line package (DIP), and the leads come out from only two opposing sides of the four outer peripheral sides. Since this DIP is limited to only two sides from which leads are led out,
The number of pins that can be used for input / output also decreases, and as a result, in general, the internal circuit cannot be complicated, but instead the outer diameter increases, so the external dimensions (occupied volume required for mounting, etc. This is disadvantageous in terms of area and other efficiency, but it is easier to handle in mounting etc. because of its larger outer shape compared to a high-efficiency, small-pin-count package. It is often used for memory packages because of its advantages such as being able to be placed and inserted into a hole or an insertion hole.

It is also known that, in the case of a memory formed in a general semiconductor integrated circuit, when the current process rules are used, the chip size must be increased as the storage capacity of the memory increases. I have. However, for a memory LSI, it is not necessary to increase the number of pins required for input / output according to the increase in the storage capacity. No need to increase. General IC and L
In an SI package, the number of pins increases as the size of a chip increases. However, in the case of a memory LSI, the number of pins to be used is reduced even if the number of pins increases due to the increase in the size of the chip. Since there is no need to increase the number of pins, the number of unused pins or the number of pins connected to the same input / output increases when the chip size increases, resulting in an excessive number of pins (unmatch) as the specified chip size I do. If the number of unnecessary pins increases, it is not preferable because it causes a failure, such as erroneous connection or the possibility that the unnecessary pins are bent and come into contact with other components.

In order to eliminate the mismatch between the chip size and the number of pins, various efforts have been made to reduce the chip size by improving the current process rules. For example, in order to reduce the apparent component size, a method of forming integrated circuits on the upper and lower surfaces of a semiconductor chip, a method of arranging a semiconductor chip having an integrated circuit on one side on both sides of a lead frame, and a method of integrating on both sides 2. Description of the Related Art A semiconductor device using a method of bonding a semiconductor chip on which a circuit is formed to a lead frame or the like is known. As a specific example, JP-A-5-75016 discloses a semiconductor chip having a semiconductor integrated circuit and a connection electrode (connection portion) on one side.
A semiconductor device is disclosed in which individual semiconductor chips are die-bonded to the front and back surfaces, and wire bonding is performed from each semiconductor chip to the lead frame. In Japanese Patent Application Laid-Open No. 5-55446, a pair of semiconductor chips (having a semiconductor integrated circuit and a connection electrode on one side) are arranged on both sides of a lead frame, and these semiconductor chips and leads or between the pair of semiconductor chips is disposed. A semiconductor device having a configuration in which connecting members to be connected are connected by wire bonding is disclosed. Further, Japanese Patent Application Laid-Open No. 8-181165 discloses a semiconductor device in which a semiconductor chip having a semiconductor integrated circuit and connection electrodes formed by wire bonding on both upper and lower surfaces is bonded to one surface of a lead frame provided with an opening for a bonding wire. Have been. On the other hand, in the above prior art, the chip and the lead frame are connected by wire bonding, but all electrodes (pads) on the chip are bonded to terminals on the package at once by specific bumps or metal leads without using wires. A method (wireless bonding) is also known. This method includes, for example, a flip chip method in which solder bumps are formed on a chip pad through a thin metal film by plating or vapor deposition, or a lead is formed by photolithography for each frame of a polymer film tape. A tape automated bonding (TAB) system in which a gold bump is bonded to the end of a lead is known. Therefore, instead of connecting the above-mentioned conventional connection parts by wire bonding, it is possible to connect them by, for example, the TAB method.

[0005]

However, no matter which of the above connection methods is used, a chip on which a connection electrode (pad) capable of bonding to a lead in a semiconductor chip of a conventional semiconductor device can be provided. Is limited, and the spacing between the leads cannot be so narrow to avoid interference between the leads. Therefore, it is difficult to increase the storage capacity more than the above-described conventional technology using the same chip size. There was a problem. The present invention has been made to solve the above-described conventional problems, and has as its object to provide a semiconductor device capable of increasing the storage capacity more than before without increasing the chip size.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor device according to the first aspect of the present invention, wherein two semiconductor chips to which leads are connected are sealed by an encapsulant with an insulating base interposed therebetween. In the packaged semiconductor device, each of the semiconductor chips has a connection portion on each of upper and lower surfaces to which a semiconductor integrated circuit and a lead are connected, and the connection is connected to the lead. According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the connecting portion of the semiconductor chip is provided only on upper and lower surfaces of two opposing sides of the four surrounding sides, and the semiconductor chip on the upper side of the base is provided. And a lead connected to a connection portion of the lower semiconductor chip is provided so as to be perpendicular to each other. According to a third aspect of the present invention, in the device of the first or second aspect, the lead is connected to a lead connected to a connection portion provided on an upper surface of the semiconductor chip and to a connection portion provided on a lower surface of the semiconductor chip. The lead is arranged so as to be alternately shifted to be drawn out. According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the base is a ceramic plate. According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the connection between the connection portion and the lead is a connection using a conductive adhesive. The present invention of claim 6 provides the present invention
5. The semiconductor device according to any one of items 4 to 4, wherein the connection between the connection portion and the lead is bonding by a gold bump.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described based on illustrated embodiments. FIG. 1 is a perspective view showing a connection configuration between an internal semiconductor chip and a lead in one embodiment of the semiconductor device of the present invention. FIG. 2 is a sectional view taken along a line aa ′ of FIG.
FIG. 3 is a sectional view taken along the line bb 'of FIG. As shown in FIG.
The semiconductor device according to the present embodiment has a first semiconductor chip 11 having semiconductor integrated circuits and pads formed on both upper and lower surfaces, and a second semiconductor chip 11 having semiconductor integrated circuits and pads formed on both upper and lower surfaces.
Semiconductor chip 12, a gold bump 15 provided on each pad of the first semiconductor chip 11 and on each pad of the second semiconductor chip 12, and connected to each semiconductor chip 11, 12 by the gold bump 15. Lead 1
4, 16, 17, 18, a ceramic frame 13 for electrically insulating between the first semiconductor chip 11 and the second semiconductor chip 12, and a sealing material 19 for them. The semiconductor chips 11 and 12 each have a memory or the like formed by a semiconductor integrated circuit formed on the upper and lower surfaces thereof, and a connection electrode (pad) is formed on a part of the surface. Gold bumps are provided on the pads, and leads 14, 16,
17 and 18 are connected. Leads 14 are connected to the gold bumps on the upper surface of the first semiconductor chip 11, and leads 16 are connected to the gold bumps on the lower surface of the first semiconductor chip 11. The leads 14 and 16 are connected to the first semiconductor chip 11
Are connected to gold bumps provided on the upper and lower surfaces of two opposing sides of the four sides. Further, the pads on the first semiconductor chip 11 and the gold bumps provided on the first semiconductor chip 11 have the upper surface side lead 14 and the lower surface side lead 16 on the two sides to which the respective leads of the first semiconductor chip are connected. Are arranged so as to alternately come out as viewed from above.

[0008] Leads 17 are connected to the gold bumps on the upper surface of the second semiconductor chip 12.
Leads 18 are connected to the gold bumps on the lower surface side of. The leads 17 and 18 are connected to gold bumps provided on the upper and lower surfaces of two opposite sides of the four sides of the second semiconductor chip 12. Further, the pads on the second semiconductor chip 12 and the gold bumps provided on the pads are such that the leads 17 on the upper surface and the leads 18 on the lower surface are formed on two sides of the second semiconductor chip to which the respective leads are connected. Are arranged so as to alternately come out as viewed from above. The ceramic frame 13 is an alumina-based ceramic base, and electrically insulates the first semiconductor chip 11 disposed on the upper side thereof from the second semiconductor chip 12 disposed on the lower side thereof, The dimensions are slightly larger than each semiconductor chip.
The first semiconductor chip 11 and the second semiconductor chip 12
When the ceramic chip 13 is electrically connected and used integrally, the ceramic frame 13 is provided with an electric conduction path such as a through hole or a wiring pattern so that the semiconductor chip arranged on the upper side and the semiconductor chip arranged on the lower side are arranged. Semiconductor chips can be electrically connected and used integrally.

The leads 14, 16 to 18 are metal terminals such as copper or iron or an alloy using them for enabling connection to the outside of the semiconductor device, and are generally provided after a semiconductor chip is packaged. Although the lead is separated from the lead frame, individual leads may be used from the beginning. The gold bump 15 is formed on the first semiconductor chip 1.
The bumps are formed on the upper and lower pads of the upper and lower surfaces of the first and second semiconductor chips 12 and are formed on the upper and lower surfaces of two sides of one semiconductor chip. Arrange them alternately. Gold bumps
Since it has good electrical conductivity, is soft and does not corrode, and has high reliability, it is suitable for a connection portion for transmitting and receiving a high-speed signal. As is well known, the bumps are projections having a spherical shape or another shape before connection, but are shown as flat after being joined by fusion. The sealing material 19 is, for example, a molding material such as an epoxy resin or a silicon resin.

In manufacturing the semiconductor device of the present embodiment, first, a semiconductor device in which leads 14 and 16 are connected to a first semiconductor chip 11 is formed, and then a second semiconductor chip 1 is manufactured.
2 are connected to the leads 17 and 18, and the leads 14 and 16 of both semiconductor chips and the leads 17
And 18 are stacked so that the ceramic frame 13 is sandwiched between the two semiconductor chips so that the semiconductor chips 18 and 18 are oriented at right angles to each other. Each of the semiconductor chips 11 and 12 and the ceramic frame 13 are connected using an adhesive used for general bonding of ceramics. Thereafter, packaging is performed with the sealing material 19, and the shape of each lead is processed into a shape suitable for mounting on a printed circuit board or the like. When a semiconductor device is manufactured using a lead frame, only necessary leads are cut from the lead frame and processed. In the above embodiment, two semiconductor chips are used, but the pitch of the leads can be narrowed. If the leads of each chip are arranged at different positions, the ceramic frame can be arranged between them. It is also possible to use three or more semiconductor chips. In addition, the ceramic frame may be made of a material other than ceramic as long as it has insulation and heat dissipation, and in order to improve heat dissipation,
It may be additionally provided on the uppermost surface or the lowermost surface of the semiconductor device. For gold bumps, a conductive adhesive may be used instead, except when the speed of the transmitted signal is very high. In that case, the thickness of the semiconductor device can be reduced, and the cost can be reduced.

[0011]

According to the above-described semiconductor device of the present invention, the following effects can be obtained. Since two semiconductor chips with semiconductor integrated circuits formed on both sides are used with a ceramic frame interposed therebetween, the use area can be reduced to 1/4 of a semiconductor device using one semiconductor chip on one side. In addition, the thickness of the package of the semiconductor device can be reduced. Since heat can be dissipated by the ceramic frame between the semiconductor chips, heat dissipation can be ensured, and a rise in temperature can be suppressed, so that noise resistance can be obtained. Since the leads of the two semiconductor chips are connected to two opposite sides of each chip, and the leads coming out of each chip are arranged so as to be perpendicular to each other, a packaging structure with good space efficiency. Can be. Adjacent leads are alternately connected to the upper surface side and the lower surface side of each semiconductor chip, so that it is possible to form external terminals having a fixed pitch that does not cause interference between the leads. Since the gold bumps are used, the connection can be made with high conductivity, heat dissipation, and reliability.

[Brief description of the drawings]

FIG. 1 is a perspective view showing a connection structure between internal semiconductor chips and leads in an embodiment of a semiconductor device of the present invention.

FIG. 2 is a sectional view taken along line a-a 'of FIG.

FIG. 3 is a sectional view taken along line b-b 'of FIG.

FIG. 4 is a perspective view showing an example of an internal connection configuration in a conventional semiconductor device.

[Explanation of symbols]

1, 11, 12 ... semiconductor chip, 2, 14, 16-
18 ... lead, 3 ... metal thin wire, 4, 19 ...
Sealing material, 15 ... gold bump

Claims (6)

[Claims] 1. A semiconductor device packaged with a sealing material in a state where a base is sandwiched between two semiconductor chips to which leads are connected, wherein each semiconductor chip has a semiconductor integrated circuit and leads on both upper and lower surfaces, respectively. A semiconductor device having a connection portion to be connected and a configuration in which one end of a lead is connected to the connection portion. 2. A connection portion of the semiconductor chip is provided only on upper and lower surfaces along two opposing sides of four sides around the semiconductor chip, and is connected to a connection portion of the semiconductor chip on the upper side of the base. 2. The semiconductor device according to claim 1, wherein the lead connected to the connecting portion of the lower semiconductor chip is provided so as to be perpendicular to each other. 3. A lead connected to a connecting portion provided on an upper surface of a semiconductor chip and a lead connected to a connecting portion provided on a lower surface of the semiconductor chip are led out to the outside while alternately shifting their positions. 3. The semiconductor device according to claim 1, wherein the semiconductor device is arranged as follows. 4. The semiconductor device according to claim 1, wherein said base is a ceramic plate. 5. The method according to claim 1, wherein the connection between the connection portion and the lead is made by a conductive adhesive.
The semiconductor device according to any one of claims 1 to 4. 6. The method according to claim 1, wherein the connection between the connection portion and the lead is performed by bonding using gold bumps.
The semiconductor device according to claim 1.