JP2000031302A - Semiconductor storage device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of an ultra-micro floating gate semiconductor storage device having areas which function as bit lines on a substrate side and adopting a buried element separating system to an ultra-micro size. SOLUTION: In an Si substrate 1, buried conductor films 2 which function as source-drain areas and bit lines, diffusion layers 3, and buried separating insulating films 7 are provided. On the substrate 1, a gate insulating film 4, floating gate electrodes 5, a capacitor insulating film 8, control gate electrodes 6, gate top insulating films 11, side-wall insulating films 12, tunnel insulating films 10, and an erasing gate electrode 9 are provided. At the intersections between the insulating films 7 and buried conductor films 2, the insulating films 7 are deeper than the conductor films 2. Since the insulating films 7 can be formed in liner shapes, not islandlike shapes, while the functions of both members are maintained and the resolution of photolithography can be improved when separating grooves are formed, the memory cell section of a semiconductor storage device can be formed in an ultra-micro size.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating gate type EEPROM (El
ectrically Erasable and Programable Read Only Memo
ry) and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, an electrically programmable read only memory (EPROM) having a floating gate structure has been used as an electrically writable nonvolatile memory.
y) is well known. The memory cell of this EPROM has a source / drain region and a channel region sandwiched between the source / drain regions in a semiconductor substrate, and further has a gate insulating film and a floating gate electrode on the channel region of the semiconductor substrate. , A capacitor insulating film and a control gate electrode are sequentially laminated. This EP
In the writing of the ROM, hot electrons are generated in a region near the drain region of the channel region by flowing a current between the source and drain regions while applying a high voltage between the drain region and the control gate electrode.
The hot electrons are accelerated and injected into the floating gate electrode which is capacitively coupled to the control gate electrode. Conventionally, erasing of an EPROM has been performed by irradiating ultraviolet rays. However, in recent years, the gate insulating film has been thinned, and a tunneling phenomenon through the thin gate insulating film has been used to remove the floating gate electrode from the source region. A method of electrically erasing by emitting electrons to a drain region, a drain region, or a channel region is employed.

In recent years, floating gate type E
In EPROM, since ultra-miniaturization of each element in an ultra-semiconductor device and high integration and high performance of the entire semiconductor device are required, a buried element isolation formed so that an isolation insulating film is embedded in a semiconductor substrate. 2. Description of the Related Art The structure of a semiconductor memory device based on a system is widely adopted. In particular, in a semiconductor memory device, in addition to the buried element isolation method, a continuous impurity diffusion layer is provided between each memory cell so that the impurity diffusion layer has functions as a source / drain region and a bit line. Is known.

FIG. 20 shows an example of such a conventional floating gate type EEPROM of a buried element isolation type, particularly one having a structure with an erase gate.
This will be described with reference to FIGS.

However, the EEPROM having the erase gate structure has
The OM is electrically provided by separately providing an independent erasing gate electrode and extracting electrons from the floating gate electrode to the erasing gate electrode, as disclosed in, for example, Japanese Patent Application Laid-Open No. 4-340767. It has a memory cell structure for erasing.

FIG. 20 is a plan view of a conventional floating gate type semiconductor memory device with an erase gate of an embedded element isolation system, FIG. 21 is a sectional view taken along the line XXa-XXa of FIG. 20, and FIG. Sectional view along line XXb, FIG.
FIG. 3 is a sectional view taken along line XXc-XXc in FIG.

[0007] As shown in FIGS. 20 to 23, a conventional semiconductor memory device includes a source memory formed in a Si substrate 101.
A diffusion layer 103 serving as a drain region, a gate insulating film 104 formed of a silicon oxide film, a floating gate electrode 105 formed of a polysilicon film,
A control gate electrode 106 composed of a polysilicon film; and a capacitive insulating film 1 interposed between the floating gate electrode 105 and the control gate electrode 106.
08, a buried isolation insulating film 107 for isolating each memory cell, an erase gate electrode 109, and an erase electrode 1
09, a tunnel insulating film 110 interposed between the floating electrode 104, an on-gate insulating film 111 provided on the control gate electrode 106, and a side surface of the control gate electrode 106 and the on-gate insulating film 111. Sidewall insulating film 112. here,
The diffusion layer 3 functions not only as a source / drain region of each memory cell but also as a bit line connecting between the source / drain regions of each memory cell.

[0008]

In such a conventional structure of a semiconductor memory device, as shown in FIG.
In the substrate 101, the buried isolation insulating film 107 and the diffusion layer 10
3 cannot be crossed. That is, in order to prevent the buried isolation insulating film 107 from interrupting the conduction of the diffusion layer 103 which should function as a bit line (see FIG. 22), the buried isolation insulating film 1
07 need to be arranged in an island shape. However, if the buried isolation insulating film 107 is arranged in an island shape, it will not be a line & space pattern, so that it is difficult to control the dimensions in the lithography process in the process for forming the isolation trench, which hinders miniaturization. I was

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to maintain the function of a buried isolation insulating film without interrupting conduction between a source / drain region and a region serving as a bit line. Meanwhile, by taking measures to cross the buried isolation insulating film and the regions functioning as the source / drain regions and the bit lines, it is easy to control the dimensions in lithography and to achieve a super-miniaturized floating gate type semiconductor memory device. And a method for producing the same.

[0010]

Means taken by the present invention for achieving the above object is to provide a buried conductor by forming a source / drain region and a region functioning as a bit line of each memory cell with a buried conductor film. The isolation insulating film and the buried conductor film cross each other without impairing their functions.

A semiconductor memory device according to the present invention is a semiconductor memory device in which memory cells having a gate insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode sequentially provided on a main surface of a semiconductor substrate are arranged in an array. A storage device, comprising: a plurality of linear embedded isolation insulating films extending in one direction on a main surface side of the semiconductor substrate to separate the memory cells from each other; Extending in a direction crossing the isolation insulating film,
A plurality of buried conductor films functioning as a source / drain region and a bit line of each of the memory cells, and the buried element-dividing insulating film is provided deeper than the buried conductor film at a portion intersecting the buried conductor film. Have been.

Thus, even if the buried isolation insulating film and the buried conductor film intersect each other, conduction in the buried isolation film is not interrupted by the buried isolation insulating film, and the buried isolation insulating film is separated. Functions are also retained. Therefore, the buried isolation insulating film can be provided not in the shape of an island but in the shape of a line, and a structure capable of exhibiting high photolithography resolution by a line and space pattern when forming a separation groove. That is, it is possible to achieve ultra-miniaturization of the memory cell portion in combination with the fine structure by the embedded element isolation method.

The semiconductor memory device may further include a tunnel insulating film provided on a side surface of the floating gate electrode and serving as a tunneling medium, and an erase gate electrode opposed to the floating gate electrode with the tunnel insulating film interposed therebetween. This makes it possible to miniaturize a floating gate type semiconductor memory device with an erase gate.

In the semiconductor memory device, an impurity diffusion layer formed by introducing an impurity into a region around the buried conductor film in the semiconductor substrate is formed in the source / drain region of each memory cell. Thus, characteristics of a portion of the memory cell functioning as a switching transistor can be favorably maintained.

The buried conductor film may be made of a refractory metal or polycrystalline silicon containing impurities, or may have a structure in which a refractory metal film is sandwiched between polycrystalline silicon films.

According to a first method of manufacturing a semiconductor memory device of the present invention, a memory cell having a gate insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode sequentially provided on a main surface of a semiconductor substrate is formed in an array. A first step of forming a plurality of linear separation grooves extending in one direction on a main surface side of a semiconductor substrate, and forming a plurality of linear separation grooves in the separation groove. A second method of forming a buried isolation insulating film by burying an insulating material;
A third step of forming a plurality of conductive film grooves extending in a direction intersecting with the separation groove on the main surface side of the semiconductor substrate so as to be shallower than the separation groove; The conductor material is embedded in the
A fourth step of forming a buried conductor film functioning as a drain region and a bit line; and forming a gate insulating film on a main surface of the semiconductor substrate on a region surrounded by the buried isolation insulating film and the buried conductor film. , A floating gate electrode, a capacitor insulating film, and a control gate electrode.

According to this method, in the first step, the line &
By utilizing the high resolution of the photolithography by the space pattern, it is possible to form a fine and highly precise separating groove. Therefore, an ultra-miniaturized semiconductor memory device can be easily formed.

In the first method for manufacturing a semiconductor memory device, the fifth step may include forming a tunnel insulating film which can serve as a tunneling medium on a side surface of the floating gate electrode, and sandwiching the tunnel insulating film. And a step of forming an erase gate electrode opposed to the floating gate electrode. Thus, a semiconductor memory device with an erase gate which is ultra-miniaturized can be formed.

It is preferable that the method further includes a step of introducing an impurity into the buried conductor film, and a step of diffusing the impurity from the buried conductor film to a region in the semiconductor substrate around the buried conductor film.

According to a second method of manufacturing a semiconductor memory device of the present invention, a memory cell having a gate insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode sequentially provided on a main surface of a semiconductor substrate is formed in an array. A first step of forming a plurality of linear separation grooves extending in one direction on a main surface side of a semiconductor substrate, and forming a plurality of linear separation grooves in the separation groove. A second method of forming a buried isolation insulating film by burying an insulating material;
A third step of forming a plurality of conductive film grooves extending in a direction intersecting with the separation groove on the main surface side of the semiconductor substrate, deeper than the separation groove; The conductor material is embedded in the
A fourth step of forming a buried conductor film functioning as a drain region and a bit line; and forming a gate insulating film on a main surface of the semiconductor substrate on a region surrounded by the buried isolation insulating film and the buried conductor film. , A floating gate electrode, a capacitor insulating film, and a control gate electrode.

According to this method, the buried molecular insulating film is finally divided into islands by the buried conductor film. However, in the first step, the buried molecular insulating film is finely divided by utilizing the high resolution of photolithography using a line and space pattern. Separation grooves with good shape accuracy can be formed. Therefore, an ultra-miniaturized semiconductor memory device having an island-shaped buried isolation insulating film can be easily formed.

[0022]

Embodiments of the present invention will be specifically described below with reference to the drawings.

(First Embodiment) The structure of a semiconductor memory device according to a first embodiment of the present invention will be described with reference to FIGS. 1 is a plan view of the semiconductor memory device according to the present embodiment, FIG. 2 is a cross-sectional view taken along line Ia-Ia of FIG. 1, FIG. 3 is a cross-sectional view taken along line Ib-Ib of FIG.
3 is a sectional view taken along line Ic-Ic.

As shown in FIGS. 1 to 4, the semiconductor memory device according to the present embodiment includes a buried conductor film 2 formed in a Si substrate 1 and functioning as a source / drain region and a bit line.
And a diffusion layer 3, a gate insulating film 4 composed of a silicon oxide film, a floating gate electrode 5 composed of a polycrystalline silicon film, a control gate electrode 6 composed of a polycrystalline silicon film, and a floating gate electrode. 5, a capacitive insulating film 8 interposed between the control gate electrode 6, a buried isolation insulating film 7 for isolating between memory cells, an erase gate electrode 9, and a space between the erase electrode 9 and the floating electrode 4. A gate insulating film 11 provided on the control gate electrode 6;
And a sidewall insulating film 12 formed on the side surface of the insulating film 11 on the gate. However, the embedded conductor film 2
Is formed by embedding polycrystalline silicon in a groove formed in the Si substrate 1, and the diffusion layer 3 is formed by introducing impurities into the Si substrate 1.

That is, electrons are extracted (erased) from the floating gate electrode 5 by applying a voltage between the erase gate electrode 9 and the floating gate electrode 5 so that the electrons pass through the tunnel insulating film 10 by tunneling. Then, it is configured to move from the floating gate electrode 5 to the erase gate electrode 9.

The semiconductor memory device according to the present embodiment is characterized in that a buried conductor film 2 functioning as a source / drain region and a bit line is formed in a Si substrate 1 and a buried isolation insulating film 7 is formed in the Si substrate 1. This is a point that is formed not in an island shape but in a linear shape. And, as shown in FIG.
At a portion where the buried conductor film 2 and the buried isolation insulating film 7 intersect, the buried conductor film 2 is
It is formed so as to be embedded in. That is, the buried isolation insulating film 7 is formed to a deeper region than the buried conductor film 2. In a region (see FIG. 2) sandwiched between the buried isolation insulating films 7 in the Si substrate 1, a diffusion layer 3 is formed, and the buried conductor film 2 is surrounded by the diffusion layer 3.

In the semiconductor memory device according to the present embodiment, the buried conductor film 2 is provided in the region to be the source / drain region. Since the buried conductor film 2 is buried in the buried isolation insulating film 7 in the cross section shown in FIG. 3, even if the buried isolation insulating film 7 is linearly continuous, the buried conductor film 2 functioning as a bit line is provided. Is not interrupted. Further, the function of the buried isolation insulating film 7 for electrically isolating the memory cells from each other is maintained. Therefore, the buried isolation insulating film 7 can be formed in a continuous linear shape, and a high resolution by a line & space pattern can be exerted in a photolithography process when forming an isolation groove.
Therefore, ultra-miniaturization of the semiconductor memory device can be achieved.

Although the diffusion layer 3 is not necessarily required, the presence of the diffusion layer 3 makes it possible to appropriately adjust the distance between the source and drain regions of the memory cell. It is preferable to provide the diffusion layer 3 from the viewpoint of improving the characteristics of the lower switching transistor.

In this embodiment, an example of a floating gate type EEPROM having an erase gate electrode has been described. However, a buried conductor film is used in a source / drain region of an EEPROM without an erase gate electrode using a buried element isolation method. It goes without saying that it may be formed.

In this embodiment, an example is shown in which a polycrystalline silicon film is used as the buried conductive film. However, a conductive film made of another material such as titanium silicide or a refractory metal other than polycrystalline silicon is used. It goes without saying that it may be used.

Next, the method of manufacturing the semiconductor memory device according to the present embodiment will be described with reference to FIGS.
The description will be made with reference to the respective drawings from (a) to (c). Here, each of the attached symbols (a)-(c) from FIG. 5 (a)-(c) to FIG. 12 (a)-(c) correspond to the line Ia-Ia in FIG.
The cross-sectional structures taken along lines -Ib and Ic-Ic are shown, respectively.

First, in the steps shown in FIGS. 5A to 5C, a depth 300 extending linearly along the main surface of the Si substrate 1 is set.
A separation groove of about nm is formed, and a silicon oxide film is buried in the separation groove by etch back to form a buried separation insulating film 7. Thereafter, the surface of the Si substrate 1 is thermally oxidized to form a protective oxide film 13 made of a silicon oxide film having a thickness of about 20 nm on the main surface.

Next, in the steps shown in FIGS.
A conductive film mask pattern 14 made of a linear photoresist film extending in a direction orthogonal to the buried isolation insulating film 7 is formed on the substrate, and is buried with the protective oxide film 13 by a known anisotropic dry etching method. The isolation insulating film 7 and the Si substrate 1 are removed by etching to form a conductor film groove 15 having a depth of about 200 nm. In other words, the depth dimension of the conductor film groove 15 is smaller than the thickness dimension of the buried isolation insulating film 7, and the portion where the conductor film groove 15 intersects with the buried isolation insulating film 7 is shown in FIG. Thus, the buried isolation insulating film 7 remains below the bottom of the conductive film groove 15.

Next, in the steps shown in FIGS. 7A to 7C, a first polycrystalline silicon film 16 having a thickness of about 200 nm is deposited on the substrate by a known low-pressure CVD method, and the conductive film groove 15 is formed. Is filled with a polycrystalline silicon film.

Further, in the steps shown in FIGS. 8A to 8C, a known anisotropic dry etching is performed to remove the first polycrystalline silicon film 16 other than the conductive film groove 15. After burying the polysilicon in the conductor film groove 15, the protective oxide film 13 is removed by etching. As a result, the buried conductor film 2 is formed. Thereafter, a wiring mask pattern 17 is formed of a photoresist film, and arsenic ions are implanted into the substrate under the conditions of an acceleration voltage of 40 KeV and an implantation amount of 6 × 10 ¹⁵ cm ^{−2 using} this as a mask.

Next, in the steps shown in FIGS.
The wiring mask pattern 17 is removed, and heat treatment is performed by a known heat treatment method, for example, at a temperature of 950 ° C. under a nitrogen atmosphere.
Heat treatment for about a minute. By this step, the polycrystalline silicon constituting the buried conductor film 2 is reduced in resistance, and at the same time, N-type arsenic is diffused from the buried conductor film 2 in the Si substrate 1 to form a diffusion layer 3.

Next, in the steps shown in FIGS. 10A to 10C, the surface of the Si substrate 1 is oxidized by a known thermal oxidation method to form a gate insulating film having a thickness of about 30 nm on the Si substrate 1. Then, a second polycrystalline silicon film 18 having a thickness of about 300 nm is deposited by a known low pressure CVD method. Next, a second photo-etching method is used.
The predetermined portions of the polycrystalline silicon film 18 and the gate insulating film 4 are selectively removed. Next, a capacitance insulating film 8 made of a silicon oxide film having a thickness of about 15 nm is deposited by a known low-pressure CVD method to a thickness of about 15 nm, and is subjected to a heat treatment at 900 ° C. for densification. Next, a third polycrystalline silicon film 19 having a thickness of about 300 nm is formed by a known low-pressure CVD method.
And an on-gate insulating film 11 made of a silicon oxide film having a thickness of about 300 nm are sequentially formed.

Next, in the steps shown in FIGS. 11A to 11C, the insulating film 11 on the gate is patterned by a known photo-etching method so as to leave a portion that can be the control gate electrode 6, and the gate insulating film 11 is formed on the gate. The control gate electrode 6 is formed by patterning the third polycrystalline silicon film 19 using the insulating film 11 as a mask. Then, after depositing a silicon oxide film having a thickness of about 200 nm by a known low pressure CVD method, a known anisotropic dry etching is performed to form a sidewall insulating film 12 on the side surfaces of the control gate electrode 6 and the on-gate insulating film 11. To form

Next, in the steps shown in FIGS. 12A to 12C, anisotropic dry etching is performed using the on-gate insulating film 11 and the side wall insulating film 12 as a mask to form a second polycrystalline silicon film 18. Is patterned to form a floating gate electrode 5. Then, the side wall of the floating gate electrode 5 exposed in this state is subjected to a treatment by a known thermal oxidation method, for example, thermal oxidation in a steam atmosphere at 900 ° C. to form a tunnel made of a silicon oxide film having a thickness of about 30 nm. An insulating film 10 is formed. Next, a fourth polycrystalline silicon film having a thickness of about 400 nm is deposited by a known low pressure CVD method, and then the fourth polycrystalline silicon film is selectively removed by a known photoetching method. An erase gate electrode 9 is formed so as to cover 10.

The subsequent steps of forming a metal wiring, forming a protective film, and forming a bonding pad are not shown and described, but can be performed by any known method.

According to the manufacturing method of this embodiment, the structure of the semiconductor memory device shown in FIGS. 1 to 4 can be easily realized. Then, in the step shown in FIGS. 5A to 5C, when forming the separation groove, a linear separation groove extending along the main surface of the Si substrate 1 is used instead of the island-shaped groove. Can be formed, the accuracy of the separating groove is improved, and as a result,
The precision of the buried isolation insulating film 7 is improved. That is, the reliability can be improved.

(Second Embodiment) Next, a method of manufacturing a semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIGS. 13 (a)-(c) and 14 (a)-(c). This will be described with reference to FIG. Here, the attached symbols (a)-(c) in FIGS. 13 (a)-(c) and 14 (a)-(c) correspond to the Ia-Ia line, Ib-Ib line, Ic-line in FIG. The cross-sectional structures along the line Ic are shown. FIGS. 13A to 13C and FIGS. 14A to 14C show FIGS. 7A to 9C to FIGS. 9A to 9C in the manufacturing process of the first embodiment.
Only the steps corresponding to (c) are shown.

First, FIG. 5 during the manufacturing process of the first embodiment
The same processing as (a)-(c) and FIGS. 6 (a)-(c) is performed. That is, a depth of 300 n is formed on the main surface of the Si substrate 1.
After forming a linear isolation trench of about m, a silicon oxide film is embedded in the isolation trench to form a buried isolation insulating film 7. Then, a thickness of 20 n is formed on the main surface of the Si substrate 1.
An approximately m protective oxide film 13 is formed by a thermal oxidation method, and a conductive film groove 15 is formed along the main surface of the Si substrate 1 in a direction orthogonal to the buried isolation insulating film 7.

Next, in the steps shown in FIGS. 13A to 13C, 1 × 10 5
The first of about 200 nm thickness containing about ²⁰ atoms / cm ³
Is deposited. Therefore, a treatment by a known heat treatment method, for example, under nitrogen atmosphere at 950 ° C.
Heat treatment is performed for about 0 minutes. At this time, the N-type impurities in first polycrystalline silicon film 20 diffuse into Si substrate 1 to form diffusion layer 3.

Next, in the steps shown in FIGS. 14A to 14C, a known anisotropic dry etching is performed to remove the first polycrystalline silicon film 20 other than the conductive film groove 15. After the polycrystalline silicon is buried in the conductor film groove 15, the protective oxide film 13 is removed by etching. Thereby, the buried conductor film 2 having a low resistance is formed.

Thereafter, the same processes as those shown in FIGS. 10A to 10C to FIGS. 12A to 12C in the manufacturing process of the first embodiment are performed.

According to the manufacturing method of this embodiment, FIGS.
The structure of the semiconductor memory device shown in FIG. 4 can be easily realized. In particular, according to the manufacturing method of the present embodiment, the CV
Since the impurity is introduced into the first polycrystalline silicon film 20 in the step D, the process of forming the buried conductor film 2 and the diffusion layer 3 can be simplified, and the ultra-fine floating gate type semiconductor memory device can be realized. Cost reduction can be easily realized.

Third Embodiment Next, a method of manufacturing a semiconductor memory device according to a fourth embodiment will be described with reference to FIG.
Description will be made with reference to FIGS. 19A to 19C to FIGS. 19A to 19C. Here, FIGS. 15 (a)-(c)
From (a) to (a) to (c) in FIG.
(C) shows a cross-sectional structure taken along line Ia-Ia, line Ib-Ib, and line Ic-Ic in FIG. FIG.
The drawings from (a)-(c) to FIG. 19 (a)-(c) show the manufacturing process of the first embodiment in FIG.
Only steps corresponding to those from FIG. 9C to FIG. 9A to FIG. 9C are shown.

First, FIG. 5 during the manufacturing process of the first embodiment
The same processing as (a)-(c) and FIGS. 6 (a)-(c) is performed. That is, a depth of 300 n is formed on the main surface of the Si substrate 1.
After forming a linear isolation trench of about m, a silicon oxide film is embedded in the isolation trench to form a buried isolation insulating film 7. Then, a thickness of 20 n is formed on the main surface of the Si substrate 1.
An approximately m protective oxide film 13 is formed by a thermal oxidation method, and a conductive film groove 15 is formed along the main surface of the Si substrate 1 in a direction orthogonal to the buried isolation insulating film 7.

Next, in the steps shown in FIGS. 15A to 15C, an N-type impurity is reduced to 1 × 10 5 by a known low pressure CVD method.
^A first polycrystalline silicon film 20 having a thickness of about 200 nm containing about ²⁰ atoms / cm ³ is deposited. At this time, the thickness of the first polycrystalline silicon film 20 has reached 500 nm in the portion of the conductive film groove 15. Thereafter, a treatment by a known heat treatment method, for example, a heat treatment for about 40 minutes in a nitrogen atmosphere at 950 ° C. is performed. At this time, the first polycrystalline silicon film 2
The N-type impurity in the O is diffused into the Si substrate 1 to form a diffusion layer 3.

Next, in the steps shown in FIGS. 16A to 16C, the first polycrystalline silicon film 20 is removed by a known anisotropic dry etching method. At that time, the conductive film groove 1
The first polycrystalline silicon film 20 in the region other than the region 5 is entirely removed, and the conductive film groove 15 is removed by a thickness of 420 nm from above. The film 21 is left for a thickness of 80 nm. Next, a second polycrystalline silicon film 22 having a thickness of about 80 nm is deposited on the substrate by a known low-pressure CVD method.

Next, in the steps shown in FIGS. 17A to 17C, the second polycrystalline silicon film 22 is removed by a known anisotropic dry etching method, and the side wall of the conductive film groove 15 is formed. Then, the trench side wall polycrystalline silicon film 23 is left. Then, the known C
A refractory metal film 24 (a tungsten film in this embodiment) having a thickness of about 400 nm is deposited on the substrate by the VD method.

Next, in the steps shown in FIGS. 18A to 18C, the refractory metal film 24 in a region other than the conductor film groove 15 is removed by a known anisotropic dry etching method. The high melting point metal wiring layer 25 is left in the film groove 15. Then
A third polycrystalline silicon film 26 having a thickness of about 300 nm is deposited on the substrate by a known low-pressure CVD method.

Next, in steps shown in FIGS. 19A to 19C, the third polycrystalline silicon film 26 in a region other than the conductive film groove 15 is removed by a known anisotropic dry etching method. Then, the trench upper polycrystalline silicon film 27 is left above the conductor film trench 15. Thereby, the polycrystalline silicon film 2 for the groove bottom is formed.
1, a buried conductor film 2 composed of a polycrystalline silicon film 23 for the groove side wall, a high melting point metal wiring layer 25 and a polycrystalline silicon film 27 for the upper part of the groove is formed.

Thereafter, the same processes as those shown in FIGS. 10A to 10C to FIGS. 12A to 12C in the manufacturing process of the first embodiment are performed.

According to the method of manufacturing the semiconductor memory device of the present embodiment, the resistance of the buried conductive film 2 is greatly reduced to one-tenth or less as compared with the manufacturing methods of the first and second embodiments. And the performance of the ultrafine floating gate type semiconductor memory device can be further improved.

(Fourth Embodiment) Next, a method of manufacturing a semiconductor memory device according to a fourth embodiment will be described with reference to FIG.
The description will be made with reference to FIGS. 26A to 26C. Here, FIGS. 24 (a)-(c)
From (a) to (a) to (c) in FIG.
(C) shows a cross-sectional structure taken along line Ia-Ia, line Ib-Ib, and line Ic-Ic in FIG.

First, in the steps shown in FIGS. 24A to 24C, a depth 300 extending linearly along the main surface of the Si substrate 1 is set.
A separation groove of about nm is formed, and a silicon oxide film is buried in the separation groove by etch back to form a buried separation insulating film 7. Thereafter, the surface of the Si substrate 1 is thermally oxidized to form a protective oxide film 13 made of a silicon oxide film having a thickness of about 20 nm on the main surface.

Next, in steps shown in FIGS. 25A to 25C, a conductor film mask pattern 14 made of a linear photoresist film extending in a direction orthogonal to the buried isolation insulating film 7 is formed on the substrate. Then, the protective oxide film 13, the buried isolation insulating film 7, and the Si substrate 1 are removed by etching by a known anisotropic dry etching method to have a depth of 350 nm.
The conductive film groove 15 is formed. In other words, the depth dimension of the conductor film groove 15 is larger than the thickness dimension of the buried isolation insulating film 7, and the conductor film groove 15 and the buried isolation insulating film 7
25, the buried isolation insulating film 7 is separated by the conductor film groove 15, as shown in FIG. Further, arsenic ions are introduced into the substrate at an acceleration voltage of 40 Ke.
V is implanted under the conditions of an implantation amount of 6 × 10 ¹⁵ cm ⁻² .

Next, in the steps shown in FIGS. 26A to 26C, a first polycrystalline silicon film 16 having a thickness of about 200 nm is deposited on the substrate by a known low pressure CVD method, and the conductive film groove 15 is formed. Is filled with a polycrystalline silicon film.

Thereafter, FIG. 8 in the first embodiment
Processing similar to the steps shown from (a)-(c) to FIGS. 12 (a)-(c) is performed. However, since the diffusion layer 3 has already been formed, it is not necessary to perform arsenic ion implantation.

According to the manufacturing method of this embodiment, FIG.
In the steps (a) to (c), when forming the separation groove, a linear separation groove extending along the main surface of the Si substrate 1 can be formed instead of the island-shaped groove. Then, FIG.
5 (a)-(c), the embedded isolation insulating film 7
Are separated into islands, but the separation characteristics between the cells do not decrease so much. Therefore, when the separation groove is formed during the manufacturing process, a semiconductor memory device having a fine cell structure can be formed by improving the photolithography accuracy by the line & space pattern.

In the manufacturing method according to the first to fourth embodiments, a floating gate type EEPROM having an erase gate electrode has been described as an example. However, the present invention has a structure in which a buried isolation insulating film is provided. Needless to say, the present invention can be applied to the case where the buried conductor film is used in the source / drain region of the EEPROM having no erase gate electrode.

[0064]

According to the semiconductor memory device of the present invention, in the floating gate type semiconductor memory device, the linear buried isolation insulating film intersects with the buried conductor film functioning as the source / drain region and the bit line. Since the buried conductor film is buried in the buried isolation insulating film at this intersection, it is possible to provide the buried isolation insulating film in a linear shape instead of an island shape while securely maintaining the functions of both members. It is possible to achieve ultra-miniaturization of a semiconductor memory device having a high structure.

According to the first method of manufacturing a semiconductor memory device of the present invention, after a linear isolation groove is formed, an insulating material is embedded therein to form a buried isolation insulating film, which intersects with the isolation groove. The trench for the conductor film is formed shallower than the trench for the separation in the direction in which the conductor film is formed, and the conductor material is buried in the trench to form the buried conductor film functioning as the source / drain region and the bit line. By using the high resolution of photolithography, a separation groove having a fine shape and high shape accuracy can be formed, and therefore, an ultra-miniaturized semiconductor memory device can be easily formed.

According to the second method of manufacturing a semiconductor memory device of the present invention, a linear isolation groove is formed, and then an insulating material is embedded therein to form a buried isolation insulating film, which intersects with the isolation groove. The trench for the conductor film is formed deeper than the trench for the separation in the direction in which the conductor film is formed, and the conductor material is buried in the trench to form the buried conductor film functioning as the source / drain region and the bit line. Utilizing the high resolution of photolithography, it is possible to form fine and highly precise isolation grooves, and thus to easily form ultra-miniaturized semiconductor memory devices with island-shaped buried isolation insulating films can do.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line Ia-Ia in FIG.

FIG. 3 is a sectional view taken along the line Ib-Ib in FIG. 1;

FIG. 4 is a sectional view taken along the line Ic-Ic in FIG. 1;

FIG. 5 is a sectional view taken along the line Ia-Ia of FIG. 1 showing a state in which a thermal oxide film is formed in the method of manufacturing the semiconductor memory device according to the first embodiment;
It is sectional drawing of the cross section corresponding to the Ib-Ib line and the Ic-Ic line.

FIG. 6 is a cross-sectional view corresponding to lines Ia-Ia, Ib-Ib, and Ic-Ic of FIG. 1 showing a state in which a buried conductive film forming groove is formed in the method of manufacturing the semiconductor memory device according to the first embodiment; FIG.

FIG. 7 shows a state in which a polycrystalline silicon film is buried in a buried conductor film forming groove in the method of manufacturing the semiconductor memory device according to the first embodiment, and is a line Ia-Ia, Ib-Ib, Ic-Ic in FIG.
It is sectional drawing of the cross section corresponding to a line.

FIG. 8 is a line Ia-Ia line, Ib-Ib line, Ic-Ic line of FIG. 1 showing a state in which a wiring mask pattern is formed and arsenic ions are implanted in the method of manufacturing the semiconductor memory device according to the first embodiment; 3 is a cross-sectional view of a cross section corresponding to FIG.

FIG. 9 is a sectional view taken along lines Ia-Ia and Ib of FIG. 1 showing a state in which a diffusion layer is formed in the method of manufacturing the semiconductor memory device according to the first embodiment;
It is sectional drawing of the cross section corresponding to the -Ib line and the Ic-Ic line.

FIG. 10 is a diagram illustrating a state in which a second interlayer insulating film is formed in the method for manufacturing a semiconductor memory device according to the first embodiment;
It is sectional drawing of the cross section corresponding to the Ia-Ia line, the Ib-Ib line, and the Ic-Ic line.

FIG. 11 is a cross-sectional view corresponding to lines Ia-Ia, Ib-Ib, and Ic-Ic of FIG. 1 showing a state in which a sidewall insulating film is formed in the method for manufacturing a semiconductor memory device according to the first embodiment; FIG.

FIG. 12 is a diagram illustrating a state in which an erase gate electrode is formed in the method of manufacturing the semiconductor memory device according to the first embodiment;
It is sectional drawing of the cross section corresponding to the -Ia line, the Ib-Ib line, and the Ic-Ic line.

FIG. 13 is a sectional view taken along the line Ia-Ia of FIG. 1 showing a state in which a diffusion layer is formed in the method for manufacturing a semiconductor memory device according to the second embodiment;
It is sectional drawing of the cross section corresponding to the Ib-Ib line and the Ic-Ic line.

FIG. 14 is a view showing a state in which a second gate insulating film is removed in the method for manufacturing a semiconductor memory device according to the second embodiment;
FIG. 2 is a cross-sectional view of a cross section corresponding to line Ia-Ia, line Ib-Ib, and line Ic-Ic of FIG.

FIG. 15 is a sectional view taken along line Ia-Ia of FIG. 1 showing a state in which a diffusion layer is formed in the method for manufacturing a semiconductor memory device according to the third embodiment;
It is sectional drawing of the cross section corresponding to the Ib-Ib line and the Ic-Ic line.

FIG. 16 corresponds to lines Ia-Ia, Ib-Ib, and Ic-Ic of FIG. 1 showing a state in which a second polycrystalline silicon film is formed in the method of manufacturing a semiconductor memory device according to the third embodiment. FIG.

FIG. 17 is a diagram illustrating a state in which a high-melting-point metal film is formed in the method for manufacturing a semiconductor memory device according to the third embodiment;
It is sectional drawing of the cross section corresponding to the Ia line, the Ib-Ib line, and the Ic-Ic line.

FIG. 18 shows a state in which a third polycrystalline silicon film is formed in the method of manufacturing the semiconductor memory device according to the third embodiment, taken along lines Ia-Ia, Ib-Ib, and Ic-Ic in FIG. It is sectional drawing of the cross section corresponding to a line.

FIG. 19 is a diagram illustrating a state in which a buried conductor film is formed in the method for manufacturing a semiconductor memory device according to the third embodiment;
It is sectional drawing of the cross section corresponding to the Ia-Ia line, the Ib-Ib line, and the Ic-Ic line.

FIG. 20 is a plan view of a conventional floating gate type semiconductor memory device with an erase gate of an embedded element isolation method.

21 is a sectional view taken along line XXa-XXa in FIG.

FIG. 22 is a sectional view taken along line XXb-XXb in FIG. 20;

FIG. 23 is a sectional view taken along line XXb-XXb in FIG. 20;

FIG. 24 is a diagram illustrating a state where a thermal oxide film is formed in the method of manufacturing the semiconductor memory device according to the fourth embodiment;
It is sectional drawing of the cross section corresponding to a line, Ib-Ib line, Ic-Ic line.

FIG. 25 is a cross-sectional view corresponding to the lines Ia-Ia, Ib-Ib, and Ic-Ic of FIG. 1 showing a state in which a groove for forming a buried conductive film is formed in the method for manufacturing a semiconductor memory device according to the fourth embodiment; FIG.

FIG. 26 shows a state in which a polycrystalline silicon film is buried in a buried conductor film forming groove in the method for manufacturing a semiconductor memory device according to the fourth embodiment, taken along lines Ia-Ia, Ib-Ib, and Ic- in FIG.
It is sectional drawing of the cross section corresponding to Ic line.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Si substrate 2 buried conductor film 3 diffusion layer 4 gate insulating film 5 floating gate electrode 6 control gate electrode 7 buried isolation insulating film 8 capacitance insulating film 9 erase gate electrode 10 tunnel insulating film 11 on-gate insulating film 12 sidewall insulating film 13 protection Oxide film for use 14 Conductive film forming mask pattern 15 Conductive film groove 16 Polycrystalline silicon film 17 Wiring mask pattern 18 Second polycrystalline silicon film 19 Third polycrystalline silicon film 20 First polycrystalline silicon film 21 Polycrystalline silicon film for groove bottom 22 Second polycrystalline silicon film 23 Polycrystalline silicon film for groove side wall 24 Refractory metal film 25 Refractory metal wiring layer 26 Third polycrystalline silicon film 27 Polycrystalline silicon film for groove top

Continued on the front page F term (reference) 5F001 AA02 AA09 AA22 AA23 AA25 AA26 AA64 AB03 AB07 AD15 AD60 AE08 AG07 AG10 5F083 EP13 EP25 EP30 EP42 EP62 ER18 ER21 GA02 GA09 JA39 KA07 KA08 NA01 PR03 PR09 PR29

Claims (10)

[Claims] 1. A semiconductor memory device comprising memory cells having a gate insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode sequentially provided on a main surface of a semiconductor substrate, arranged in an array. A plurality of linear buried isolation insulating films extending in one direction on the main surface side of the semiconductor substrate for separating the memory cells from each other; and intersecting with the buried isolation insulating films on the main surface side of the semiconductor substrate. And the source of each of the above memory cells
A semiconductor having a plurality of buried conductor films functioning as a drain region and a bit line, wherein the buried isolation insulating film is provided deeper than the buried conductor film at a portion intersecting with the buried conductor film; Storage device. 2. The semiconductor memory device according to claim 1, wherein a tunnel insulating film provided on a side surface of said floating gate electrode and serving as a tunneling medium, and an erase gate opposed to said floating gate electrode with said tunnel insulating film interposed therebetween. A semiconductor memory device further comprising an electrode. 3. The semiconductor memory device according to claim 1, wherein the source / drain region of each memory cell includes:
A semiconductor memory device, wherein an impurity diffusion layer formed by introducing an impurity is formed in a region around the buried conductor film in the semiconductor substrate. 4. The semiconductor memory device according to claim 1, wherein said buried conductor film is made of a high melting point metal. 5. The semiconductor memory device according to claim 1, wherein said buried conductor film is made of polycrystalline silicon containing impurities. . 6. The semiconductor memory device according to claim 1, wherein said buried conductor film is formed by sandwiching a refractory metal film between polycrystalline silicon films. Semiconductor storage device. 7. A method of manufacturing a semiconductor memory device in which memory cells having a gate insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode sequentially provided on a main surface of a semiconductor substrate are arranged in an array. A first step of forming a plurality of linear isolation grooves extending in one direction on the main surface side of the semiconductor substrate; and forming an embedded isolation insulating film by embedding an insulating material in the isolation grooves. A second step of forming a plurality of conductive film grooves extending in a direction intersecting with the separation groove on the main surface side of the semiconductor substrate so as to be shallower than the separation groove; A fourth step of burying a conductive material in the trenches to form a buried conductive film functioning as a source / drain region and a bit line of each of the memory cells; A fifth step of forming the gate insulating film, the floating gate electrode, the capacitor insulating film, and the control gate electrode on a region surrounded by the isolation insulating film and the buried conductor film. Of manufacturing a semiconductor memory device. 8. The method of manufacturing a semiconductor memory device according to claim 7, wherein said fifth step is a step of forming a tunnel insulating film that can serve as a tunneling medium on a side surface of said floating gate electrode; Forming an erase gate electrode opposed to the floating gate electrode with the interposition therebetween. 9. The method for manufacturing a semiconductor memory device according to claim 7, wherein an impurity is introduced into the buried conductor film, and the impurity is diffused from the buried conductor film to a region in a semiconductor substrate around the buried conductor film. A manufacturing method of the semiconductor memory device, further comprising the step of: 10. A method of manufacturing a semiconductor memory device in which memory cells having a gate insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode sequentially provided on a main surface of a semiconductor substrate are arranged in an array. A first step of forming a plurality of linear isolation grooves extending in one direction on the main surface side of the semiconductor substrate; and forming an embedded isolation insulating film by embedding an insulating material in the isolation grooves. A second step of forming a plurality of conductor film grooves extending in a direction intersecting with the separation groove on the main surface side of the semiconductor substrate, and a third step of forming a plurality of conductor film grooves deeper than the separation groove; A fourth step of forming a buried conductive film functioning as a source / drain region and a bit line of each of the memory cells by burying a conductive material in the groove for use; Forming a gate insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode on a region surrounded by the embedded isolation insulating film and the buried conductor film. Of manufacturing a semiconductor memory device.