JP2000031286A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high integration of a semiconductor integrated circuit device and to prevent deterioration of characteristics of each transistor in the adjacent-arranged unit cells, by removing minute opposing regions between a plurality of unit cells arranged adjacent. SOLUTION: Regions defined by boundary lines LX and LY of X and Y directions includes at least a well region WN of a one conductivity type, well contact regions WCAN of the same conductivity type as unit cells C4 to C8 are arranged in the well region WN, the cells are arranged in an X direction (or Y direction) so that boundary lines LY of the adjacent unit cells are mutually overlapped, and the well contact regions WCAN are formed as contacted with the boundary lines LY of the unit cells adjacent in the above array direction. No minute opposing regions can be formed between the well contact regions WCAN of the adjacent unit cells an array dimension of the unit cells in the X direction can be reduced thus realizing a high integration. Further a transistor having an accurate region can be formed without causing falling of a photoresist film in a photoresist step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device in which a plurality of unit cells are arranged, and more particularly, to a high integration by improving the arrangement of wells or substrate contact regions provided in each unit cell. The present invention relates to a semiconductor integrated circuit device which realizes improvement in semiconductor element characteristics.

[0002]

2. Description of the Related Art In the case of manufacturing a semiconductor integrated circuit device in which a plurality of unit cells, the size of which is not necessarily uniform, are manufactured, for example, a CMOS type semiconductor integrated circuit device, FIG. As shown in an example, an arbitrary number (eight in this case) of unit cells C21 to C28 are combined and laid out, and a required wiring is formed. In each of the unit cells C21 to C28, P-type and N-type well regions WP and WN are respectively disposed, and a gate electrode G and N-type and P-type source / drain regions SD are provided in these well regions.
Forming N and SDP, each M of N channel or P channel
OS transistors NMOS and PMOS are arranged, and a boundary line LX extending in the X direction and a boundary line LY extending in the Y direction are formed by dividing a region including the MOS transistor by a predetermined width or length. In this specification, the well region means a P-type or N-type semiconductor layer formed on a semiconductor substrate,
The present invention is not necessarily limited to the case where the impurity layer of the opposite conductivity type is formed on the substrate of one conductivity type, but includes the conductivity type layer of the substrate itself. Further, each of the N-type and P-type well regions WN, WN,
Within the WP, well contact regions WCAN and WCAP of the same conductivity type and made of a high concentration impurity layer for supplying power to the well region are provided. The unit cells C21 to C24 and C25 to C28 are arranged such that the boundary lines LX extending in the X direction of the unit cells are arranged in a straight line such that the well regions are aligned in the X direction. As shown, when unit cells are arranged adjacently in the Y direction, which is the direction in which the well regions are juxtaposed, if the unit cells adjacent in the Y direction are of the same conductivity type of P-type or N-type. Are set in the opposite direction, and are arranged so that the well regions of the same conductivity type of the unit cells adjacent in the Y direction are integrated. Thus, the formed semiconductor integrated circuit device is configured as one well in which the well regions of each unit cell are connected in the X direction.

In such a semiconductor integrated circuit device, FIG.
As shown in FIG. 10 together with FIG. 10, a plurality of unit cells C21 to C28 are laid out to form a desired integrated circuit. At least one well contact region WCAP, WCAN is arranged in each well region WP, WN of each unit cell so that a potential gradient does not occur in the well potential of each unit cell, and via well contact WCT connected to this well contact region. Power supply. In FIG. 10,
PSUB is a P-type silicon substrate, SIO is an interlayer insulating film, S
IG is a signal wiring, and WCT is a well contact. Also, in this case, since the unit cells having different configurations have different arrangement patterns depending on the standard and the number of MOS transistors arranged therein, the well contact region of each unit cell is unique to each unit cell. Is located in the position.

[0004]

By the way, in the conventional semiconductor integrated circuit device, as shown in FIG. 9, the well contact regions WCAP and WCAN are smaller than the boundary line LX extending in the X direction of the unit cell by ΔL ′. Only located inside. Therefore, when an integrated circuit is formed by laying out a large number of unit cells, a cross-sectional view of a portion where each well contact region of the unit cell adjacent in the X direction and the Y direction is arranged close to each other, for example, a CC line in FIG. 10, a minute interval ΔL (ΔL = 2 · Δ) between the well contact regions WCAN of the unit cells C23 and C27.
L ′), an opposing area (hereinafter, referred to as a small inter-opposed area) SPC is formed. For this reason, in the case of the semiconductor integrated circuit device, a minute facing region SPC exists between each well contact region WCAN of the N-type well region WN of the adjacent unit cell. As a result,
The dimension in the arrangement direction of the unit cells is increased by the interval dimension ΔL of the minute facing area SPC, which hinders high integration of the semiconductor integrated circuit device.

In addition, when the minute facing region exists as described above, a photoresist mask having a very small width is formed in the minute facing region in a photolithography process when the well contact region is actually formed. Become. FIG. 11 shows such a state, in which the N-type source / drain region SDN and the N-type well contact region WCAN are provided.
Is formed as a narrow-width photoresist mask PR ′ in the region SPC between the small opposing sides of the adjacent well contact region WCAN. For this reason, the photoresist mask PR ′ having a very small width easily falls down in the middle of the photolithography process. In the above-described impurity implantation process for forming the well contact region WCAN, the photoresist mask PR ′ falls as designed due to the fall of the photoresist mask. This causes a problem that the well contact region cannot be formed.

In order to prevent the occurrence of the above-mentioned minute facing region, the well contact region may be formed at a position in contact with the boundary line of the unit cell. For example, JP
According to the technique described in Japanese Patent Application Laid-Open No. 1-191047, each source contact region of a unit cell arranged adjacently is arranged at a position in contact with a boundary line of the unit cell. Each source contact region of the cell is brought into contact with each other, and a small inter-facing region is not formed between the two source contact regions, which is effective in achieving high integration of the semiconductor integrated circuit device.

However, in this conventional technique, since it is applied to a source contact region for supplying power to a source region of the opposite conductivity type formed in a region of one conductivity type, as described above, the adjacent unit is used. If the source regions of the cells are formed in contact with each other, it is good. However, when the source regions in each unit cell are displaced and arranged, the source regions are spaced apart without contact. Occasionally, a parasitic transistor is generated between the well region of one conductivity type and each source region of the opposite conductivity type, and the original transistor characteristics may be deteriorated. Therefore, the technique described in the above publication is effective under the restriction that each source region of an adjacent unit cell is brought into contact, but as described above, the well in each unit cell is covered by the present invention. If the arrangement position of the contact region is not specified, it is inevitable that the respective well contact regions of the adjacent unit cells will be in contact with each other, so that the above-described problem cannot be avoided. Also, if the well contact region is in contact with the boundary line of the unit cell, when the well contact region is formed by actually diffusing impurities into the semiconductor substrate,
The impurity may be formed beyond the boundary of the unit cell due to diffusion of impurities in the horizontal direction. In particular, when well regions of different conductivity types are arranged adjacent to each other, the well contact region is formed in the well region of the opposite conductivity type. In addition, the characteristics of the transistor in each unit cell are degraded, and the intended semiconductor integrated circuit device cannot be manufactured.
Further, when unit cells having the same shape are arranged in the same direction as in a gate array, they can be arranged in consideration of the position of the well contact WCT in advance. For example, the layout can be relatively easily achieved such that the well contacts WCT are shared by adjacent unit cells, or one well contact WCT is arranged for a plurality of unit cells. For this reason, there is no problem of the small inter-facing region as described above. However, when unit cells having different configurations are randomly arranged, it is impossible to predict where the well contacts WCT of adjacent unit cells will be. If the well contact WCT is determined in advance as in a gate array, problems such as the inability to arrange the transistors constituting the unit cell at optimal positions and the increase in the size of the unit cell occur.

SUMMARY OF THE INVENTION It is an object of the present invention to realize a high integration of a semiconductor integrated circuit device by eliminating a minute facing region between adjacently arranged unit cells, and to reduce the characteristic deterioration of each transistor in an adjacently arranged unit cell. It is an object of the present invention to provide a semiconductor integrated circuit device that prevents the above problem.

[0009]

A semiconductor integrated circuit device according to the present invention has a semiconductor region of at least one conductivity type in a region defined by a boundary line in the X direction and the Y direction, and includes a semiconductor region in the semiconductor region. A unit cell in which semiconductor contact regions of the same conductivity type are arranged, wherein the unit cell and a unit cell adjacent thereto are arranged in at least one of the X direction and the Y direction so that boundary lines of the unit cells overlap each other, and The semiconductor contact region is formed so as to be in contact with a boundary line between adjacent unit cells in the arrangement direction. Here, the semiconductor contact region is formed in a rectangular pattern, and one side thereof is formed so as to overlap a boundary line between adjacent unit cells in the arrangement direction. For example, the unit cells are arranged at least in the X direction, and the semiconductor contact region of each unit cell is arranged so that one side thereof overlaps the boundary line on the X side of each unit cell opposed in the X direction. Alternatively, the unit cells are arranged at least in the Y direction, and the semiconductor contact region of each unit cell is arranged so that one side thereof overlaps a boundary line on the Y side of each unit cell opposed in the Y direction.

In the case where the present invention is applied to a semiconductor integrated circuit device having a CMOS structure, the semiconductor region of the unit cell may be a semiconductor substrate of one conductivity type or a well region of the opposite conductivity type formed on the semiconductor substrate. The semiconductor contact region is configured as a substrate contact region of the semiconductor substrate or a well contact region of the well region. Alternatively, the unit cell has a structure in which a P-type well region and an N-type well region are arranged in the X direction, and a P-type well contact region provided in each of the P-type well region and the N-type well region. The N-type well contact region has a configuration in which one side overlaps with a boundary line at both ends in the X direction or a boundary line at both ends in the Y direction.

In the semiconductor integrated circuit device according to the present invention, since the semiconductor contact regions are arranged on the boundary line between the adjacent unit cells, a minute facing region is generated between the semiconductor contact regions of the adjacent unit cells. Therefore, the arrangement dimensions of the unit cells can be reduced, and high integration can be realized. Further, it is possible to form a highly accurate element pattern without causing the photoresist film to collapse in the photoresist process. Further, between adjacent unit cells, the same conductivity type semiconductor contact regions provided in the semiconductor region of one waveguide are arranged on the same boundary line, so that a parasitic element may be formed between both unit cells. Therefore, deterioration of the device characteristics can be prevented.

[0012]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows the present invention in CM
FIG. 2 is a plan view of a part of the first embodiment applied to the OS type semiconductor integrated circuit device. A plurality (here, eight) of unit cells C1 to C8 are arranged in the X direction (length direction) and the Y direction (width direction). Each of the unit cells C1 to C8 includes:
As schematically shown in FIG. 2, one unit cell has a P-type well WP and an N-type well WN arranged in the Y direction. The unit cell is located in a region including the P-type well WP and the N-type well WN. Are set as the boundary lines LX and LY. Here, each of the unit cells is designed to have the same width dimension, that is, the cell dimension in the Y direction, but the length dimension, that is, the cell dimension in the X direction, is designed to have a unique length dimension. In each of the unit cells C1 to C8, a gate electrode G is arranged over the region of the P-type well WP and the N-type well WN, and N-type and P-type source / drain regions SDN and SDP are arranged. The layout of a CMOS structure composed of an N-channel MOS transistor NMOS and a P-channel MOS transistor PMOS is designed. Further, one well contact region WCAP and WCAN is provided corresponding to each of the P well region WP and the N well region WN. It is arranged. The well contact regions WCAP and WCAN are designed so that the planar shape is a rectangular pattern, and their outer sides are arranged on the boundary lines LY between the unit cells C1 to C8. That is, in this embodiment, one side of each of the well contact regions WCAP and WCAN is arranged at a position in the X direction so as to overlap a boundary line LY extending in the Y direction of each unit cell. In addition, each of the unit cells C1 to C
In No. 8, the position of the well contact region in the Y direction is arranged at the same position or at a different position in the cell, respectively, due to the difference in the number and the standard of the MOS transistors included in the cell.

As shown in FIG. 1, each of the unit cells C1 to C8 includes a P-type well WP and an N-type well WN.
Are arranged in the X direction such that they are arranged in a straight line in the X direction, and the boundary line LX extending in the X direction of each unit cell is aligned in the X direction, and the boundary line LY extending in the Y direction is adjacent to the unit cell. The cells are arranged so as to overlap each other. Here, the unit cells C5 to C8 are configured as unit cells in which a P-type well WP and an N-type well WN are invertedly arranged in the Y direction with respect to the unit cells C1 to C4. C5 to C8 are arranged in the X direction in the same manner as the unit cells C1 to C4. Then, the rows of the unit cells C5 to C8 are added to the unit cells C1 to C8.
It is arranged so as to be adjacent to the column C4 in the Y direction.
At this time, similarly to the case of the unit cells C1 to C4, the boundary line L extending in the Y direction of each adjacent unit cell is provided.
They are arranged at positions in the X direction such that Ys overlap each other.

As described above, the unit cells C1 to C
A required wiring pattern is designed for 8. FIG. 3 is an enlarged layout diagram of the unit cells C5 to C8 in the integrated circuit of FIG. FIG. 4 is an enlarged sectional view taken along the line AA of FIG. 3. In FIG. 4, parts corresponding to the above-described parts are denoted by the same reference numerals. Also, in FIG.
UB is a P-type silicon substrate, and SIO is an interlayer insulating film.
As shown in these figures, the source contact S is connected to the source / drain regions SDP and SDN of the MOS transistors PMOS and NMOS of the unit cells C5 to C8.
CT and a drain contact DCT are arranged, and a well contact region WC of each of the well regions WP and WN is provided.
Well contact WCT is arranged for AP and WCAN. Then, a high voltage side wiring (VCC) and a low voltage side wiring (GND) are provided for each of the contacts SCT and WCT.
Is arranged. The drain contacts DCT of both MOS transistors are mutually connected by a signal wiring SIG.

In this semiconductor integrated circuit device, between unit cells arranged in the X direction and adjacent to each other in the X direction, the positions of the well contacts WCAP and WCAN in the X direction are the boundaries extending in the Y direction as described above. Although specified at a position in contact with the line LY, the positions in the Y direction are such that the well contact regions WCAP and WCAN coincide with each other or are different from each other. For example, in FIG. 3, the position of each well contact region WCAP in the Y direction completely matches between the unit cells C7 and C8, and the well contact region WCAN also partially overlaps in the Y direction, and the unit cells C5 and C6 Between them, the well contact regions WCAP are completely displaced in the Y direction. However, as described above, each well contact region WCAP, WCAP of the unit cell adjacent in the X direction is used.
CAN is a boundary line LY extending in the Y direction of each unit cell.
Because it is located above, there is no X-direction minute facing area SPC between the well contact areas of both unit cells. That is, since the well contact regions WCAN are in contact with each other in the unit cells C7 and C8, it is apparent that there is no minute facing region between the two well contact regions WCAN. Even when the two well contact regions are shifted, such as between the contact regions WCAP or between the well contact regions WCAP of the unit cells C5 and C6, the two well contact regions are not separated from each other in the X direction and face each other. , No small inter-facing region is generated.

Therefore, as can be seen from FIG. 4, there is no need to secure a small inter-facing area between the unit cells adjacent in the X direction, for example, C7 and C8, and the dimension in the X direction of the semiconductor integrated circuit device is reduced. Minimizing, high integration of the semiconductor integrated circuit device can be realized. Incidentally, FIG. 5 shows a configuration in which unit cells in which the well contact region is arranged apart from the boundary line LY of the unit cells as in the related art are arranged in the X direction. As shown in the drawing, a small inter-facing area SPC having a dimension ΔL is generated between adjacent unit cells C7 and C8. Further, since the small inter-facing region SPC is not generated, the narrow photoresist pattern PR ′ as shown in FIG. 11 is not formed during the manufacture of the semiconductor integrated circuit device, and the pattern due to the fall of the photoresist pattern is not formed. There is no failure. Further, as is apparent from this embodiment, in the present invention, the well contact regions of the same conductivity type are formed in the well regions of one conductivity type, so that the well contact regions of the adjacent unit cells are arranged close to each other. In this case, no parasitic transistor is formed between the well and the well contact region,
There is no deterioration in transistor characteristics. Further, even if the well contact region of each unit cell diffuses in the horizontal direction and enters the well region of the unit cell adjacent in the X direction, the entered region is the well of the same conductivity type of the unit cell adjacent in the X direction. Therefore, the characteristics of the transistors of the adjacent unit cells do not deteriorate.

In this embodiment, the well contact region W
Since CAP and WCAN are arranged on the boundary line LY extending in the Y direction of the unit cells, the width in the X direction can be reduced, and the number of unit cells arranged in the X direction can be increased.
Alternatively, this is advantageous when designing an integrated circuit in which the width dimension in the X direction is reduced. In this embodiment, when the well contact region of each unit cell is arranged close to the boundary line LX extending in the X direction, a minute facing region is formed between the well contact region of the unit cell adjacent in the Y direction. Therefore, it is important to arrange the position of the well contact region in the Y direction at a position that does not approach the boundary line LX.

FIG. 6 shows the present invention as in the first embodiment.
FIG. 11 is a plan view of a part of the second embodiment applied to a MOS type semiconductor integrated circuit device, and shows a plurality (eight) of unit cells C;
11 to C18 are arranged in the X direction and the Y direction. Each of the unit cells C11 to C18 is exactly the same as that of the first embodiment except for the arrangement positions of the well contact regions WCAP and WCAN, as shown in the schematic diagram of FIG. N-type wells WN are juxtaposed, and unit cells are defined by boundary lines LX and LY.
Each of the unit cells C11 to C18 is designed to have the same width dimension, that is, the cell dimension in the Y direction, but the length dimension, that is, the cell dimension in the X direction is designed to have a unique length dimension. . In each of the unit cells, a gate electrode G is disposed over the region of the P-type well WP and the N-type well WN, and N-type and P-type source / drain regions SDN and SDP are disposed.
Channel MOS transistor NMOS, P-channel MO
A CMOS structure composed of S-transistor PMOS is designed for layout, and the P-well region WP and N
One well contact region WCAP, WCAN is provided corresponding to each well region WN.

Here, in the second embodiment, the well contact regions WCAP and WCAN are designed so that their planar shapes are rectangular patterns, and their outer sides are boundary lines extending in the X direction of each unit cell. It is located on LX. In each of the unit cells C11 to C18, the positions in the X direction of the well contact regions WCAP and WCAN are arranged at the same position or at different positions, respectively, due to the difference in the number and standards of the MOS transistors included in the cells.

The unit cells C11 to C18
Is a boundary line L that is arranged in the X direction such that the P-type well WP and the N-type well WN of each unit cell are respectively arranged in a straight line in the X direction, and extends in the X direction of each unit cell.
X is arranged in a straight line in the X direction, and the boundary lines LY extending in the Y direction are arranged so as to overlap in unit cells adjacent in the X direction. In the unit cells C11 to C14 and the unit cells C15 to C18, the well regions WP and WN are directed to opposite sides, respectively. The N-type well regions WN of the unit cells are in contact with each other, and The boundary lines LX extending in the directions are arranged so as to overlap each other.

The unit cells C11 to C11 arranged as described above
Source contact SCT and drain contact DC for each source / drain region SDP, SDN of C18
T is disposed, and the well contact region WCA
Well contacts WCT are arranged for P and WCAN, and high voltage side wiring (V
CC) and a low-voltage side wiring (GND) are provided.
The connection of the signal wiring SIB is the same as in the first embodiment.

In this semiconductor integrated circuit device, the unit cells arranged in the Y direction and adjacent to each other in the Y direction have N portions integrated with each other in the respective well contact regions.
The well contact regions WCAN of the mold well region WN have the same position in the X direction or different positions. For example, in the figure, the position of each well contact region WCAN in the X direction completely matches between the unit cells C13 and C17, and partially overlaps in the X direction between the unit cells C12 and C16. Between C18, it is completely displaced in the X direction. However, since one side of each well contact region WCAN of the unit cells adjacent in the Y direction is located on the boundary line LX extending in the X direction of each unit cell, the unit cells opposed in the Y direction Is not present between the well contact regions WCAN. That is, the unit cells C13 and C13
17, the well contact region WCAN is in contact, and it is clear that there is no minute inter-facing region, and the unit cell C12 and C16 or the unit cell C14
In the case where the two well contact regions WCAN are shifted from each other, as in the case between
Are not opposed to each other with a distance in the Y direction, so that a minute facing area is not generated.

Therefore, it is not necessary to secure a small inter-facing area between adjacent unit cells in the Y direction, minimizing the dimension of the semiconductor integrated circuit device in the Y direction, and increasing the degree of integration of the semiconductor integrated circuit device. realizable. FIG. 7 shows FIG.
FIG. 10 is a cross-sectional view taken along the line BB of FIG.
It can be seen that the small inter-facing region SPC has not been generated between 17. In addition, since the minute facing area SPC is not generated, a narrow photoresist pattern is not formed at the time of manufacturing the semiconductor integrated circuit device, and a pattern failure due to the collapse of the photoresist pattern does not occur. Further, as is apparent from this embodiment, in the present invention, the well contact regions of the same conductivity type are formed in the well regions of one conductivity type, so that the well contact regions of the adjacent unit cells are arranged close to each other. Even if
No parasitic transistor is formed between the well and the well contact region, and no deterioration in transistor characteristics occurs. Further, even if the well contact region of each unit cell diffuses in the horizontal direction and enters the well region of the unit cell adjacent in the Y direction, the entered region is the well of the same conductivity type of the unit cell adjacent in the Y direction. Because
The characteristics of the transistors of the adjacent unit cells are not deteriorated.

In this embodiment, since one side of the well contact region is arranged on the boundary line LX extending in the X direction of the unit cell, the length dimension in the Y direction can be reduced, and the unit arranged in the Y direction can be reduced. This is advantageous when designing an integrated circuit in which the number of cells is increased or the length in the Y direction is reduced. In this embodiment, the boundary line LY extending in the Y direction extends through the well contact region of each unit cell.
, There is a possibility that a minute inter-facing region may be formed between the well contact region of the unit cell adjacent in the X direction and the position of the well contact region in the X direction may be close to the boundary line LY. It is important to place them in such a position.

As described above, in the semiconductor integrated circuit device according to the present invention, various unit cells having different lengths in the X direction of the unit cells are designed, or various arrangements of transistors inside the unit cells are different. In the case where the unit cell is designed, even if the arrangement position of the well contact region of each unit cell in the X direction or the Y direction is arranged at a different position in each unit cell, any of the Y direction and the X direction A small inter-facing region is not generated between the well contact regions between unit cells adjacent to each other, so that high integration of the semiconductor integrated circuit device and improvement in element characteristics can be achieved.

When a layout of such a unit cell is automatically designed by computer software, each contact region between adjacent unit cells must be laid out so as to be smaller than the resolution dimension of the photolithography technique. Conventionally, the minimum dimension is limited in order to prevent the above problem. However, if this restriction is still effective, the arrangement of the well contact region may be limited. Therefore, in the computer software that executes the present invention, it is preferable to design the software such that the above-described restriction on the minimum dimension is released in the layout for the well contact region.

In the above embodiment, an example in which the present invention is applied to a semiconductor integrated circuit device having a CMOS structure has been described. However, if the semiconductor integrated circuit device has a layout configuration in which wells of the same conductivity type are arranged adjacent to each other, one conductive type is used. The present invention can be similarly applied to a semiconductor integrated circuit device of a type, or can be similarly applied to a semiconductor integrated circuit device including a bipolar transistor.

[0028]

As described above, according to the present invention, a unit cell provided with a semiconductor contact region of the same conductivity type as that of a semiconductor region is placed in the X direction so that boundary lines for defining each unit cell overlap each other. And the semiconductor contact region of each unit cell is formed so as to be in contact with the boundary line of the unit cell adjacent in the arrangement direction. A small inter-facing region is not generated between the semiconductor contact regions, the arrangement size of the unit cells is reduced, and high integration can be realized. Further, it is possible to form a highly accurate element pattern without causing the photoresist film to collapse in the photoresist process. Further, between adjacent unit cells, the same conductivity type semiconductor contact regions provided in the semiconductor region of one waveguide are arranged on the same boundary line, so that a parasitic element may be formed between both unit cells. Therefore, deterioration of the device characteristics can be prevented. In addition, even if unit cells of different sizes and different types are arranged adjacently, it is not necessary to provide an unnecessary inter-facing region, so that miniaturization can be realized and the degree of freedom of arrangement can be improved.

[Brief description of the drawings]

FIG. 1 is a plan layout diagram of a first embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a diagram showing a basic configuration of a unit cell according to the first embodiment of the present invention.

FIG. 3 is an enlarged view of a part of FIG. 1;

FIG. 4 is an enlarged sectional view taken along line AA of FIG.

FIG. 5 is a cross-sectional view of the related art as a comparative diagram for explaining the effect of the first embodiment.

FIG. 6 is a plan layout diagram of a second embodiment of the present invention.

FIG. 7 is a diagram illustrating a basic configuration of a unit cell according to a second embodiment of the present invention.

FIG. 8 is an enlarged sectional view taken along the line BB of FIG. 6;

FIG. 9 is a plan layout diagram of a conventional semiconductor integrated circuit device.

FIG. 10 is an enlarged sectional view taken along the line CC of FIG. 9;

FIG. 11 is a cross-sectional view for explaining a problem of the related art.

[Explanation of symbols]

 C1 to C8 Unit cell C11 to C18 Unit cell PSUB P-type silicon substrate WN N-type well region WP P-type well region WCAN N-type well region well contact region WCAP P-type well region well contact region PMOS P-channel MOS transistor NMOS N Channel MOS transistor LX Boundary line extending in X direction LY Boundary line extending in X direction G Gate electrode SDN N-type source / drain region SDP P-type source / drain region SPC Small facing region

Claims (7)

[Claims] A semiconductor region having at least one conductivity type in a region defined by boundary lines in the X direction and the Y direction;
And a unit cell in which a semiconductor contact region of the same conductivity type is arranged in the semiconductor region, and X is set such that a boundary line between the unit cell and a unit cell adjacent thereto overlaps with each other.
In a semiconductor integrated circuit device arranged in at least one of the direction and the Y direction, the semiconductor contact region is formed so as to be in contact with a boundary line between adjacent unit cells in the arrangement direction. . 2. The semiconductor integrated circuit device according to claim 1, wherein said semiconductor contact region is formed in a rectangular pattern, and one side thereof is formed so as to overlap a boundary line between adjacent unit cells in said arrangement direction. 3. The unit cells are arranged at least in the X direction, and a semiconductor contact region of each unit cell is arranged so that one side thereof overlaps a boundary line on the X side of each unit cell opposed in the X direction. The semiconductor integrated circuit device according to claim 2. 4. The unit cells are arranged at least in the Y direction, and a semiconductor contact region of each unit cell is arranged so that one side thereof overlaps a boundary line on the Y side of each unit cell opposed in the Y direction. The semiconductor integrated circuit device according to claim 2. 5. One side of each semiconductor contact region of an adjacent unit cell is disposed so as to overlap on the same boundary line between the unit cells, and each side of each semiconductor contact region is on the same boundary line. 5. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device overlaps, contacts, or is separated from each other. 6. The semiconductor region of the unit cell is a semiconductor substrate of one conductivity type or a well region of the opposite conductivity type formed on the semiconductor substrate, and the semiconductor contact region is a substrate contact region of the semiconductor substrate or the semiconductor contact region. 6. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a well contact region of a well region. 7. The unit cell, wherein a P-type well region and an N-type well region are arranged in the X direction, and a P-type well contact region and an N-type well region provided in each of the P-type well region and the N-type well region. 6. The semiconductor integrated circuit device according to claim 1, wherein each of the mold well contact regions is arranged such that one side thereof overlaps a boundary line at both ends in the X direction or a boundary line at both ends in the Y direction.