JP2000031263A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent dimples from being left on the surface of an isolation oxide film formed in a trench. SOLUTION: A layer 14 of softening material such as boron which decreases the glass softening point is formed as buried in a CVD oxide film 6 as deep as prescribed by implantation of ions or thermal oxidation carried out in vapor phase, liquid phase or solid phase. Thereafter, the CVD oxide film 6 is thermally treated so as to melt its part adjacent to a non-close contact surface 5, whereby a dimple 12 is filled up. By this setup, the surface of the CVD oxide film 6 is turned smooth, and an isolation oxide film free from dimples 12 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having an isolation oxide film embedded in a trench and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, there has been a method of manufacturing a semiconductor device in which a trench is formed in a semiconductor substrate and the trench is filled with an isolation oxide film to isolate an element formation region. Hereinafter, a conventional method of manufacturing a semiconductor device will be described with reference to FIG.
This will be described with reference to FIGS.

First, a silicon oxide film 102 having a thickness of 10 nm to 30 nm is formed by thermally oxidizing the main surface of the silicon substrate 101 from a surface of the silicon substrate 101 to a predetermined depth. Next, SiH ₂ Cl ₂ and NH
₃ using CVD (Ch at a temperature condition of 630 ° C. to 800 ° C.)
A silicon nitride film 103 having a thickness of 50 nm to 400 nm is formed on the silicon oxide film 102 by an emical vapor deposition method. After that, the trench 120 is formed by using a photolithography technique and a dry etching technique. Further, the pressure condition is 1.2 Torr.
The CVD oxide film 104 is buried in the trench 120 by the thermal CVD method using ethyl silicate or an oxidizing gas containing ethyl silicate and oxygen at the temperature condition of 630 ° C. to 720 ° C. Also form. At this time, C
A non-contact surface 105 is formed on the VD oxide film 104 (see FIG. 16).

[0004] Next, as shown in FIG. 17, etch back by plasma etching or CMP (Chemical Mec.).
hanical polishing) until the surface of the silicon nitride film 103 is exposed by polishing or the like.
4 is removed from the top. Thereafter, thermal oxidation treatment is performed in a steam atmosphere at a temperature condition of 1000 ° C. or more, whereby CVD
The oxide film is densified. At this time, the densified CV
A D oxide film 106, an oxide film 107 in which the side surfaces of the silicon nitride film 103 are oxidized, and an oxide film 108 in which the silicon substrate 101 is oxidized at the upper end of the trench opening are formed.

Next, as shown in FIG. 18, the silicon nitride film 103 is removed using phosphoric acid or the like. Then, by removing the silicon oxide film 102 using hydrofluoric acid or the like,
As shown in FIG. 19, an isolation oxide film 109 for electrically isolating elements is formed. Next, a gate oxide film 110 is formed in the element formation region. Thereafter, a wiring 111 such as a word line of a DRAM (Dynamic Random Access Memory) is provided so as to cross over the isolation oxide film 109 and the gate oxide film 110 in the element formation region where the MOS transistor is formed. 20 is in the state as shown in FIG.

However, when the aspect ratio of the trench 120 formed by the above manufacturing method is large,
Isolation oxide film 1 formed to fill trench 120
In some cases, a dimple 112 may be generated at the center of the upper part of the part 09. When the wiring 111 crosses over the dimple 112, if the wiring 111 is a thin film, the dimple 1
12, a step is also formed in the wiring 111,
It may be disconnected. Further, when the wiring 111 is formed, an etching residue of amorphous or polycrystalline silicon is generated along the dimple 112, and the residue may cause a short circuit between the adjacent wirings 111. As a conventional method for solving this problem, for example, Japanese Unexamined Patent Publication No.
There is a technique described in Japanese Patent Application Laid-Open No. 3-197355.

In the technique described in the publication, when the CVD oxide film 104 is removed in the state shown in FIG. 16, etch back is performed until the surface of the CVD oxide film 104 is lower than the surface of the silicon substrate 101. CVD as shown in 21
An oxide film 106 is formed. Next, as shown in FIG.
A polycrystalline silicon film 115 is formed so as to fill the upper part of trench 120 and silicon substrate 101. afterwards,
As shown in FIG. 23, polycrystalline silicon film 115 is thermally oxidized to form silicon oxide film 116 on CVD oxide film 106. Next, polishing is performed by a CMP method to form an isolation oxide film 117 having a planarized surface on the CVD oxide film 106 as shown in FIG.

[0008]

However, in the step of planarizing the surface for forming the isolation oxide film 117 according to the technique described in Japanese Patent Application Laid-Open No. 63-197355,
As shown in FIG. 23, a step of thermally oxidizing polycrystalline silicon 116 is included. Generally, it takes a long time to thermally oxidize polycrystalline silicon film 115 to the surface of CVD oxide film 106 in the state of FIG. It costs. Therefore, in the long-time thermal oxidation process, the corners of the surface of the silicon substrate 101 forming the trench 120 are further oxidized,
As shown in FIG. 23, oxide film 108 is formed. Therefore, in the conventional technique described in Japanese Patent Application Laid-Open No. 63-197355, the area of the element formation region 118 is reduced, and there may be a problem that an active region such as a transistor cannot be formed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to secure a necessary area of an element forming region and to prevent disconnection of a wiring or short circuit between adjacent wirings. Therefore, it is necessary to prevent dimples from remaining in the center of the surface of the trench.

[0010]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a trench in a semiconductor substrate; forming an isolation oxide film so as to fill the trench; A step of distributing an element that lowers the softening point of the isolation oxide film from the first to a predetermined depth, and a step of performing a heat treatment on the isolation oxide film.

In the method of manufacturing a semiconductor device having such a process, a substance consisting of an element which lowers the softening point of the isolation oxide film is generated in the upper center of the isolation oxide film in the process of softening the isolation oxide film by heat treatment. The dimple dissolves and the depression can be embedded. Therefore, it is possible to prevent the disconnection of the wiring traversing over the isolation oxide film and the short circuit between adjacent wirings, which are caused by the presence of the dimple.

Further, since there is no step of heat-treating the polycrystalline silicon formed over the entire surface of the semiconductor substrate for a long time as in the prior art, the surface corners of the silicon substrate for forming the trench are not oxidized and the element formation region is not oxidized. The area can be secured accurately.

In the method of manufacturing a semiconductor device according to the first aspect, the method of distributing the substance made of the element that lowers the softening point of the isolation oxide film can be performed by ion implantation or thermal diffusion.

Further, according to the manufacturing method of the first or second aspect, the structure as in the third aspect, that is, in the vicinity of the upper center of the isolation oxide film so as to fill a trench provided on the semiconductor substrate. Only in this case, a structure in which a substance that lowers the softening point of the isolation oxide film remains can be formed. According to such a structure, there is an advantage that the material that lowers the softening point is not distributed over the whole of the isolation oxide film filling the trench, so that the isolation breakdown voltage is not deteriorated by the material. .

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming a trench in a semiconductor substrate, forming an isolation oxide film so as to fill the trench, and implanting silicon into the surface of the isolation oxide film. Accordingly, the method includes a step of distributing silicon from the surface of the isolation oxide film to a predetermined depth, and a step of performing a heat treatment on the isolation oxide film.

In the method of manufacturing a semiconductor device having such steps, in the step of heat-treating silicon formed on the isolation oxide film, the dimple generated at the upper center of the isolation oxide film is dissolved, The depression can be embedded. Therefore, it is possible to prevent the disconnection of the wiring crossing the upper part of the isolation oxide film and the short circuit between the adjacent wirings caused by the presence of the dimple.

Further, since there is no step of heat-treating the polycrystalline silicon formed over the entire surface of the semiconductor substrate for a long time as in the prior art, the surface corners of the silicon substrate for forming the trench are not oxidized, and the element forming region is not oxidized. The area can be secured accurately.

A method of manufacturing a semiconductor device according to claim 5, wherein a trench is formed in a semiconductor substrate, and an isolation oxide film is formed so as to fill the trench, and an amorphous silicon film is formed on the isolation oxide film. And applying a heat treatment to the isolation oxide film and the amorphous silicon film.

In the method of manufacturing a semiconductor device having such a process, the step of applying heat treatment to the amorphous silicon film formed on the isolation oxide film removes the dimple dent generated in the upper center of the isolation oxide film. Can be embedded. Therefore, it is possible to prevent the disconnection of the wiring crossing the upper part of the isolation oxide film and the short circuit between the adjacent wirings, which are caused by the presence of the dimple.

Further, since the amorphous silicon film is formed only at the center of the surface of the isolation oxide film, the CV embedded in the trench is not subjected to a heat treatment for a long time as in the prior art.
The dimple formed at the center of the surface of the D oxide film can be flattened. Thereby, the surface corners of the silicon substrate forming the trench are not oxidized, and the area of the element formation region can be accurately secured. Further, since the amorphous silicon film has a small crystal structure and is more likely to enter the dimple than polycrystalline silicon or the like, the amorphous silicon film is more suitable for embedding the dimple.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first, second, fourth, and fifth aspects, the isolation oxide film is formed. Is performed by forming a CVD oxide film by a CVD method.

Since the dimple having the problem as in the prior art is easily generated by the CVD oxide film, the manufacturing of the semiconductor device according to any one of claims 1, 2, 4, and 5 is performed. 2. The method according to claim 1, wherein the oxide film filling the trench is formed of a CVD oxide film, whereby the disconnection of the wiring and the short circuit between the wirings can be more effectively prevented. , Claim 2,
The operation and effect of the method of manufacturing a semiconductor device according to claim 4 or 5 can be utilized.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) First, Embodiment 1 of the present invention will be described with reference to FIGS. By thermally oxidizing the silicon substrate 1, a silicon oxide film 2 having a thickness of 10 nm to 30 nm is formed from the surface of the silicon substrate 1 to a predetermined depth. Next, a silicon nitride film 3 having a thickness of 50 nm to 400 nm is formed on the silicon oxide film 2 by CVD using SiH ₂ Cl ₂ and NH ₃ at a temperature of 630 ° C. to 800 ° C. Then, after patterning the resist film by the lithography technique, the silicon substrate 1 and the silicon oxide film 2 are formed by the dry etching technique.
And a trench is formed to penetrate silicon nitride film 3. Further, a CVD oxide film 4 is formed on the trench 20 and the silicon nitride film 3 by thermal CVD under a temperature condition of 630 ° C. to 720 ° C. using ethyl silicate or an oxidizing gas containing ethyl silicate and oxygen. The structure shown in FIG.

Next, as shown in FIG. 2, the CV is removed by etching back using plasma etching or polishing such as CMP until the surface of the silicon nitride film 3 is exposed.
The D oxide film 4 is removed, and a CVD oxide film 6 is formed.

Next, as shown in FIG. 3, a substance that lowers the glass softening point temperature, such as boron, is implanted by ion implantation.
A softened material layer 14 is formed distributed from the upper surface of the CVD oxide film 6 to a predetermined depth.

Thereafter, by performing a thermal oxidation treatment in a steam atmosphere at 850 ° C. or higher, the softened material layer 14 is softened and the non-contact surface 5 is brought into close contact. Thereby, as shown in FIG. 4, dimple 12 at the upper center of CVD oxide film 6 serving as an isolation oxide film is planarized. At this time, a CVD oxide film 6 in which the non-contact surface 5 is adhered, an oxide film 7 in which the side surface of the silicon nitride film 3 is oxidized, and an oxide film 8 in which the silicon substrate 1 is oxidized are formed at the upper end of the trench opening. You.

Next, as shown in FIG. 5, the silicon nitride film 3 is removed using phosphoric acid, and then the silicon oxide film 2 is removed using hydrofluoric acid, thereby electrically isolating the elements. Therefore, isolation oxide film 16 is formed. Next, a gate oxide film 10 is formed in an element formation region between the isolation oxide films 16. Next, the gate oxide film 10 and the isolation oxide film 16
The wiring 11 is formed so as to cross over the structure, and the structure is as shown in FIG.

By using such a manufacturing method,
Since the non-contact surface 5 where the dimples 12 remain can be softened, the surface of the isolation oxide film 16 can be made relatively flat as shown in FIGS. Therefore, wiring 1
It is possible to prevent disconnection of one and short-circuit between adjacent wirings 11. In addition, since the element such as boron used to soften the isolation oxide film 16 remains only in the upper center of the isolation oxide film 16, the trench 20 is directly buried with a silicon oxide film or the like containing boron or the like. Compared to
The device has an element isolation structure that has a high isolation breakdown voltage and suppresses the influence on the channel concentration of the transistor.

Further, since the method does not include the step of thermally oxidizing the deposited polycrystalline silicon for a long time as in the prior art, the surface corner of the silicon substrate 1 for forming the trench is further oxidized, and as a result, the oxide film is formed. 8 does not increase, and the semiconductor device can secure a necessary area of the element formation region.

In this embodiment, boron is distributed by ion implantation to reduce the softening point of the oxide film. However, boron is distributed by thermal diffusion in a gas phase, a liquid phase, or a solid phase. Is also good.

Second Embodiment Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. First, by the same steps as in the first embodiment,
As shown in FIG. 2, CVD is performed on a trench 20 formed so as to penetrate semiconductor substrate 1, oxide film 2 and nitride film 3.
An oxide film 6 is formed. Thereafter, as shown in FIG. 7, silicon is implanted to a predetermined depth from the upper surface of the CVD oxide film 6 by ion implantation to form a silicon excess layer 18. At this time, the molecular arrangement is rearranged by the energy of the ion-implanted silicon, and the non-contact surface 5 has disappeared. Thereafter, by performing a thermal oxidation treatment in a steam atmosphere of 950 ° C. or higher, the silicon excess layer 18 is oxidized as shown in FIG. 8 and the surface thereof is flattened to form a dense CVD oxide film 6. At the same time, an oxide film 7 in which the side surface of the silicon nitride film 3 is oxidized and an oxide film 8 in which the corner of the silicon substrate 1 forming the trench 20 is oxidized are formed.

Next, the silicon nitride film 3 is removed using phosphoric acid, and then the silicon oxide film 2 is removed using hydrofluoric acid, thereby forming an isolation oxide film 16 for electrically isolating the elements. (See FIG. 9). Next, the gate oxide film 10 is formed between the isolation oxide films 16. Next, a wiring 11 is formed so as to cross over the gate oxide film 10 and the isolation oxide film 16, and the structure shown in FIG. 10 is obtained.

By using such a manufacturing method,
A heat treatment is applied to the implanted silicon to obtain dimples 12.
Can be softened,
The surface of the isolation oxide film 16 can be made flat. Therefore, by using such a manufacturing method, an effect similar to that of the semiconductor device manufacturing method described in the first embodiment can be obtained.

Unlike the prior art, there is no step of subjecting the polycrystalline silicon formed over the entire surface of the semiconductor substrate to heat treatment for a long time, and the dimple formed at the center of the surface of the CVD oxide film 4 embedded in the trench is not provided. By simply performing a heat treatment on the substrate 12, the CVD oxide film 4 can be planarized. Thus, the oxide film 8 in which the surface corners of the silicon substrate 1 forming the trench 20 are oxidized is not formed over a wide range of the element formation region, and the required area of the element formation region can be secured.

Third Embodiment A method of manufacturing a semiconductor device according to a third embodiment will be described with reference to FIGS. First, as shown in FIG. 2, CVD oxidation is performed on trench 20 and silicon nitride film 3 formed to penetrate semiconductor substrate 1, oxide film 2 and nitride film 3 by the same steps as in the first embodiment. A film 6 is formed. Thereafter, as shown in FIG. 11, CVD is performed by a thermal CVD method, a sputtering method, or the like.
Amorphous silicon 22 is formed on oxide film 6. next,
As shown in FIG. 12, the amorphous silicon film 22 is etched back by dry etching using plasma or the like. At this time, a residual film of the amorphous silicon film 22 remains on the dimples 12 on the surface of the CVD oxide film 6.

Thereafter, by performing a thermal oxidation process in a steam atmosphere of 950 ° C. or higher, the amorphous silicon film 22 is oxidized to form a silicon oxide film 23 as shown in FIG. At the same time, the oxide film 8 is formed at the corners of the silicon substrate 1 where the densified CVD oxide film 6, the silicon nitride film 3 is formed by oxidizing the side surfaces of the silicon nitride film 3, and the trench 20. Next, as shown in FIG. 14, the silicon nitride film 3 is removed using phosphoric acid, and then the silicon oxide film 2 is removed using hydrofluoric acid. A film 16 is formed. Next, the gate oxide film 10 is formed between the isolation oxide films 16. Next, the wiring 11 is formed so as to cross over the gate oxide film 10 and the isolation oxide film 16, and the structure as shown in FIG. 15 is obtained.

By using such a manufacturing method,
Since the amorphous silicon film 22 embedded in the dimple 12 is oxidized to become the silicon oxide film 23, the surface of the isolation oxide film is flattened, and the method of manufacturing the semiconductor device according to the second embodiment is described. Similar effects can be obtained.

Since the amorphous silicon film 22 is formed only at the center of the surface of the isolation oxide film 6, the heat treatment is not performed for a long time and the amorphous silicon film 22 is formed at the center of the surface of the CVD oxide film 6 buried in the trench 20. The formed dimples 12 can be flattened. Thereby, the surface corners of the silicon substrate 1 on which the trenches 20 are formed are not further oxidized, and the required area of the element formation region can be secured. Further, since the amorphous silicon film 22 has a small crystal structure and is more suitable for embedding the dimples 12, voids and the like are hardly formed, and the amorphous silicon film 22 can be more accurately flattened.

It should be understood that the embodiments disclosed herein are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0041]

According to the method of manufacturing a semiconductor device according to the first or second aspect of the present invention, the step of softening the isolation oxide film by a substance comprising an element which lowers the softening point of the isolation oxide film is performed. Dimples generated in the upper center can be embedded. Therefore, it is possible to provide a semiconductor device capable of preventing disconnection of a wiring crossing over the isolation oxide film and short-circuiting between adjacent wirings, which are caused by having the dimple.

According to the manufacturing method of the first or second aspect, the separation withstand voltage is not deteriorated by the substance that lowers the softening point of the isolation oxide film as described in the third aspect. A trench structure of a semiconductor device can be formed.

According to a fourth aspect of the present invention, in the step of heat-treating the silicon formed on the isolation oxide film, the depression of the dimple generated in the upper center of the isolation oxide film is buried. Can be. Therefore, it is possible to prevent disconnection of the wiring traversing the upper part of the isolation oxide film and short-circuit between adjacent wirings, which are caused by having the dimple, and to secure a necessary area of the element formation region.

According to the method of manufacturing a semiconductor device of the fifth aspect, in the step of applying a heat treatment to the amorphous silicon film formed on the isolation oxide film, the dimple generated at the upper center of the isolation oxide film is filled. Can be included. Therefore, it is possible to prevent the disconnection of the wiring traversing the upper part of the isolation oxide film and the short circuit between adjacent wirings, which have been caused by having the dimple,
In addition, the required area of the element formation region can be secured. Further, since amorphous silicon has a small crystal structure and is more likely to enter dimples than polycrystalline silicon or the like, amorphous silicon is more suitable for embedding dimples.

According to the method of manufacturing a semiconductor device described in claim 6, claim 1, claim 2, claim 4, or claim 5
By using the method for manufacturing a semiconductor device according to any one of the above for the method for manufacturing a semiconductor device of the present invention in which a CVD oxide film is formed, disconnection of wiring and short-circuit between wirings can be more effectively prevented.

[Brief description of the drawings]

FIG. 1 is a diagram showing a cross section of a state immediately after a CVD oxide film is formed in a trench in a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a cross section of a state immediately after the CVD oxide film is etched back in the method of manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a cross-sectional view showing a state immediately after boron ion implantation for lowering the glass softening point of the isolation oxide film in the method for manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a diagram showing a cross section in a state immediately after heat-treating an isolation oxide film containing boron for lowering the glass softening point and fusing the non-adhesion surface in the method for manufacturing a semiconductor device according to the first embodiment of the present invention; is there.

FIG. 5 is a diagram showing a cross section in a state immediately after a silicon oxide film and a silicon nitride film are removed in the method of manufacturing a semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a diagram showing a cross section in a state where the wiring crosses over the element formation region and the isolation oxide film in the method of manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a diagram showing a cross section in a state immediately after silicon is implanted in the method for manufacturing a semiconductor device according to the second embodiment of the present invention;

FIG. 8 is a diagram showing a cross section in a state immediately after heat treatment of an isolation oxide film containing silicon in a method of manufacturing a semiconductor device according to a second embodiment of the present invention;

FIG. 9 is a diagram showing a cross section in a state immediately after etching a silicon oxide film and a silicon nitride film in the method for manufacturing a semiconductor device according to the second embodiment of the present invention;

FIG. 10 is a diagram showing a cross section in a state immediately after forming a wiring crossing over an element formation region and an isolation oxide film in the method of manufacturing a semiconductor device according to the second embodiment of the present invention;

FIG. 11 is a diagram illustrating a cross section of a state immediately after an amorphous silicon film is formed in a method of manufacturing a semiconductor device according to a third embodiment of the present invention;

FIG. 12 is a diagram showing a cross section in a state immediately after the amorphous silicon film is etched back in the method of manufacturing a semiconductor device according to the third embodiment of the present invention;

FIG. 13 is a diagram illustrating a cross section of a state immediately after heat-treating an amorphous silicon film in a method of manufacturing a semiconductor device according to a third embodiment of the present invention;

FIG. 14 is a diagram illustrating a cross section in a state immediately after a silicon oxide film and a silicon nitride film are removed in the method of manufacturing a semiconductor device according to the third embodiment of the present invention;

FIG. 15 is a diagram showing a cross section of a state immediately after the wiring has traversed over the element formation region and the isolation oxide film in the method of manufacturing the semiconductor device according to the third embodiment of the present invention;

FIG. 16 is a cross-sectional view showing a state immediately after a CVD oxide film is formed in a trench in a conventional method for manufacturing a semiconductor device.

FIG. 17 is a cross-sectional view of a conventional method for manufacturing a semiconductor device;
FIG. 11 is a diagram showing a cross section in a state immediately after the VD oxide film is etched back.

FIG. 18 is a view showing a cross section in a state immediately after a silicon nitride film is removed in a conventional method for manufacturing a semiconductor device.

FIG. 19 is a cross-sectional view showing a state immediately after a silicon oxide film is removed in a conventional method for manufacturing a semiconductor device.

FIG. 20 is a diagram showing a cross section in a state immediately after a wiring has traversed over an element formation region and an isolation oxide film in a conventional method for manufacturing a semiconductor device.

FIG. 21 is a view showing a state of a cross section immediately after a CVD oxide film is etched back in a method of manufacturing a semiconductor device described in JP-A-63-197355.

FIG. 22 is a view showing a state of a cross section immediately after polycrystalline silicon is formed on an isolation oxide film and a semiconductor substrate in the method of manufacturing a semiconductor device described in Japanese Patent Application Laid-Open No. 63-197355.

FIG. 23 is a view showing a state of a cross section immediately after a silicon oxide film is formed by oxidizing polycrystalline silicon in a method of manufacturing a semiconductor device described in Japanese Patent Application Laid-Open No. 63-197355.

FIG. 24 is a view showing a state of a cross section immediately after a silicon oxide film is etched back and an isolation oxide film is formed in the method of manufacturing a semiconductor device described in Japanese Patent Application Laid-Open No. 63-197355.

[Explanation of symbols]

1 silicon substrate, 2,23 silicon oxide film, 3 silicon nitride film, 4,6 CVD oxide film, 5 non-adhesive surface,
7, 8 oxide film, 9, 16 isolation oxide film, 10 gate oxide film, 11 wiring, 12 dimples, 14 softened material layer, 18 silicon excess layer, 22 amorphous silicon film.

Claims (6)

[Claims] A step of forming a trench in a semiconductor substrate and forming an isolation oxide film so as to fill the trench; and setting a softening point of the isolation oxide film from a surface of the isolation oxide film to a predetermined depth. A method for manufacturing a semiconductor device, comprising: distributing an element to be reduced; and performing a heat treatment on the isolation oxide film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the method of distributing the substance made of an element that lowers the softening point of the isolation oxide film is performed by ion implantation or thermal diffusion. 3. A semiconductor device having an isolation oxide film formed so as to fill a trench provided in a semiconductor substrate, wherein the softening point of the isolation oxide film is reduced only near the upper center of the isolation oxide film. A semiconductor device having a substance made of an element to be made. 4. A step of forming a trench in a semiconductor substrate and forming an isolation oxide film so as to fill the trench, and injecting silicon into the surface of the isolation oxide film, thereby forming a trench from the surface of the isolation oxide film. A method of manufacturing a semiconductor device, comprising: distributing silicon to a predetermined depth; and performing a heat treatment on the isolation oxide film. 5. A step of forming a trench in a semiconductor substrate and forming an isolation oxide film so as to fill the trench; a step of forming an amorphous silicon film on the isolation oxide film; Applying a heat treatment to the film and the amorphous silicon film. 6. The step of forming the isolation oxide film comprises the step of forming a CV
6. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed by forming a CVD oxide film by a D method.