JP2000031200A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JP2000031200A
JP2000031200A JP10196407A JP19640798A JP2000031200A JP 2000031200 A JP2000031200 A JP 2000031200A JP 10196407 A JP10196407 A JP 10196407A JP 19640798 A JP19640798 A JP 19640798A JP 2000031200 A JP2000031200 A JP 2000031200A
Authority
JP
Japan
Prior art keywords
semiconductor chip
adhesive
semiconductor device
inner lead
branch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10196407A
Other languages
Japanese (ja)
Other versions
JP3805108B2 (en
Inventor
Koji Nose
幸之 野世
Hisashi Funakoshi
久士 船越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP19640798A priority Critical patent/JP3805108B2/en
Publication of JP2000031200A publication Critical patent/JP2000031200A/en
Application granted granted Critical
Publication of JP3805108B2 publication Critical patent/JP3805108B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/787—Means for aligning
    • H01L2224/78743—Suction holding means
    • H01L2224/78744—Suction holding means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PROBLEM TO BE SOLVED: To prevent surplus squeeze-out seeping of an adhesive, while improving adhesion strength by aiming at an adhesive structure in a semiconductor device with a structure for retaining a semiconductor chip at a lead part via an adhesive. SOLUTION: A semiconductor device consists of an inner lead part 8 with a branching pad part 5a which adheres to a semiconductor chip 1 and a photothermal curing adhesive 3 that is provided between the semiconductor chip 1 and the branch pad part 5a, and the branch pad part 5a is provided away from the tip of the inner lead part 8, namely away from a bonding point, thus preventing the photothermal curing adhesive 3 from extending to the tip part of the inner lead part 8, when the photothermal curing adhesive 3 which is present at the lower portion leaks and solving reliability problems without causing difficulties also during wire bonding.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体チップの主面
上にインナーリード部が延在するＬＯＣ（リード・オン
・チップ）構造を有する半導体装置及びその製造方法に
関するものであり、特に半導体チップとリードとの接着
構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a LOC (lead-on-chip) structure in which an inner lead extends on a main surface of a semiconductor chip, and a method of manufacturing the same. It relates to an adhesive structure with a lead.

【０００２】[0002]

【従来の技術】近年、主としてメモリーチップなどに代
表される半導体チップのパッケージング技術としては、
リードフレームのインナーリード部が半導体チップの主
面上に延在し、そのインナーリード部と半導体チップの
主面とを接着固定して半導体チップを保持する、いわゆ
るＬＯＣ技術が開発されている。従来のＬＯＣ型半導体
装置としては、半導体チップ主面とインナーリード部の
一部とを絶縁テープを介して接着して固定しているもの
があるが、最近は、前記のように半導体チップとインナ
ーリードとを接着剤により固定するタイプのＬＯＣ型半
導体装置が主流である。2. Description of the Related Art In recent years, as a semiconductor chip packaging technology mainly represented by a memory chip, etc.,
A so-called LOC technology has been developed in which an inner lead portion of a lead frame extends over a main surface of a semiconductor chip, and the inner lead portion and the main surface of the semiconductor chip are bonded and fixed to hold the semiconductor chip. As a conventional LOC-type semiconductor device, there is a device in which a main surface of a semiconductor chip and a part of an inner lead portion are bonded and fixed via an insulating tape. LOC semiconductor devices of a type in which leads are fixed with an adhesive are mainly used.

【０００３】以下、従来のＬＯＣ型半導体装置の製造方
法について図面を参照しながら説明する。図７の（ａ）
は、従来の半導体装置の製造過程における半製品の平面
図、（ｂ）は、（ａ）のＥ−Ｅ１線断面図を示す。図に
おいて、１は半導体チップ１を示し、この半導体チップ
１の主面に、接着剤３によってリードフレーム５が接着
固定されている。８はインナーリード部を示し、このイ
ンナーリード部８は半導体チップ１の端子１ａと金属細
線（図示せず）によってワイヤーボンディングされる。
５ｂは、保持部分を示し、複数のインナーリード部８の
内、接着剤３によって、半導体チップ１の主面に接着さ
れたインナーリード部８を特に名付けたものである。Hereinafter, a method for manufacturing a conventional LOC semiconductor device will be described with reference to the drawings. (A) of FIG.
Is a plan view of a semi-finished product in the process of manufacturing a conventional semiconductor device, and (b) is a cross-sectional view taken along line E-E1 of (a). In the figure, reference numeral 1 denotes a semiconductor chip 1, and a lead frame 5 is bonded and fixed to a main surface of the semiconductor chip 1 with an adhesive 3. Reference numeral 8 denotes an inner lead portion, and the inner lead portion 8 is wire-bonded to the terminal 1a of the semiconductor chip 1 by a thin metal wire (not shown).
Reference numeral 5b denotes a holding portion. Of the plurality of inner lead portions 8, the inner lead portion 8 bonded to the main surface of the semiconductor chip 1 by the adhesive 3 is specifically named.

【０００４】次に、従来の半導体装置における製造方法
の断面図を図８、図９、図１０に示す。まず、チップ接
着工程（ダイスボンド工程）について説明する。図８
（ａ）に示すように半導体チップ１を真空取り付け可能
なステージ２上に載置する。ここでは半導体チップ１が
不要な移動を起こさないように真空吸着する。固定ステ
ージ２の両側上部にはリードフレーム５の位置を規制す
るピン２ａが突設している。Next, FIGS. 8, 9 and 10 are sectional views showing a method of manufacturing a conventional semiconductor device. First, the chip bonding step (die bonding step) will be described. FIG.
As shown in (a), the semiconductor chip 1 is mounted on a stage 2 which can be vacuum-mounted. Here, the semiconductor chip 1 is vacuum-adsorbed so as not to cause unnecessary movement. Pins 2 a for regulating the position of the lead frame 5 project from upper portions on both sides of the fixed stage 2.

【０００５】そして、図８（ｂ）に示すように、半導体
チップ１上の所定の位置、すなわちインナーリード部の
保持部分５ｂを接着箇所するために接着剤３をノズル４
により塗布する。[0005] Then, as shown in FIG. 8 (b), an adhesive 3 is applied to a predetermined position on the semiconductor chip 1, that is, the nozzle 4 to adhere the holding portion 5 b of the inner lead portion.
To apply.

【０００６】次に図８（ｃ）に示すように、接着剤３が
塗布された半導体チップ１とリードフレーム５とを位置
合わせして、インナーリード部５の保持部分５ｂと半導
体チップ１とを接着する。そして、図８（ｄ）に示すよ
うに、リードフレーム５を接着した半導体チップ１を固
定ステージ２に載置したまま、硬化炉ステージ１７にセ
ットし、一定時間加熱処理を行うことにより、接着剤３
を硬化させる。なお、リードフレーム５はその外側の位
置規制孔にステージ２に設けたピン２ａを挿通すること
により規制される。Next, as shown in FIG. 8C, the semiconductor chip 1 to which the adhesive 3 has been applied is aligned with the lead frame 5, and the holding portion 5b of the inner lead portion 5 and the semiconductor chip 1 are aligned. Glue. Then, as shown in FIG. 8D, the semiconductor chip 1 to which the lead frame 5 has been adhered is set on the curing furnace stage 17 while being mounted on the fixed stage 2, and is subjected to a heat treatment for a certain period of time. 3
To cure. The lead frame 5 is regulated by inserting a pin 2a provided on the stage 2 into a position regulating hole on the outside thereof.

【０００７】次にワイヤーボンド工程について説明す
る。図９（ａ）に示すように、リードフレーム５を接着
した半導体チップ１をヒーターブロック７上に真空吸着
により固定する。なお、図中半導体チップ１とリードフ
レーム５とは分離しているように示しているが、前記し
た保持部分５ｂは半導体チップ１と接着しているもので
あり、図示している箇所は、リードフレーム５の半導体
チップ１の端子１ａと電気的な接続を行うインナーリー
ド部８の部分の断面図である。Next, the wire bonding step will be described. As shown in FIG. 9A, the semiconductor chip 1 to which the lead frame 5 is adhered is fixed on the heater block 7 by vacuum suction. Although the semiconductor chip 1 and the lead frame 5 are illustrated as being separated from each other in the drawing, the holding portion 5b is bonded to the semiconductor chip 1, and the illustrated portion corresponds to the lead. FIG. 4 is a cross-sectional view of a part of an inner lead portion 8 that electrically connects with a terminal 1a of a semiconductor chip 1 of a frame 5.

【０００８】そして図９（ｂ）に示すように、リードフ
レーム５の外周部を押さえるクランパー９ａと、インナ
ーリード部８を押さえるクランパー９ｂによりリードフ
レーム５及びインナーリード部８を押さえ、半導体チッ
プ１の主面上にインナーリード部８を接触させる。そし
てワイヤーボンダーのキャピラリー１０により金属細線
１１でインナーリード部８と半導体チップ１の端子１ａ
とを接続する。ここで半導体チップ１の主面上にインナ
ーリード部８を接触させる目的は、金属細線１１の接続
を安定に行うためである。Then, as shown in FIG. 9B, the lead frame 5 and the inner lead portion 8 are pressed by the clamper 9a for holding the outer peripheral portion of the lead frame 5 and the clamper 9b for holding the inner lead portion 8, and the semiconductor chip 1 The inner lead portion 8 is brought into contact with the main surface. Then, the inner lead portion 8 and the terminal 1a of the semiconductor chip 1 are connected by the metal wire 11 by the capillary 10 of the wire bonder.
And connect. Here, the purpose of bringing the inner lead portion 8 into contact with the main surface of the semiconductor chip 1 is to stably connect the thin metal wires 11.

【０００９】次に図９（ｃ）に示すように、クランパー
９ａ，９ｂを除去する事によりインナーリード部８が元
の状態に戻り、図９（ｄ）に示すようにインナーリード
部８と半導体チップ１とが金属細線１１により電気的に
接続される。Next, as shown in FIG. 9C, by removing the clampers 9a and 9b, the inner lead portion 8 returns to the original state, and as shown in FIG. The chip 1 is electrically connected by the thin metal wires 11.

【００１０】次に樹脂封止工程について説明する。図１
０（ａ）に示すように、半導体チップ１と保持部分５ｂ
とが接着剤３により接着された図９（ｄ）の半製品をリ
ードフレーム封止用の金型１２内にセットする。そして
図１０（ｂ）に示すように、金型１２のゲート口１３よ
り封止樹脂１４を注入する。樹脂注入後の状態を図１０
（ｃ）に示す。以上のような工程により、図１０（ｄ）
に示すような半導体チップ１とインナーリード部の保持
部分５ｂとを接着剤３により固定し、外周を封止樹脂１
４で封止したＬＯＣ型の半導体装置が製造されるもので
ある。図１０（ｄ）の状態からリードフレーム８の不要
な箇所を裁断して半導体装置が完成する。Next, the resin sealing step will be described. FIG.
0 (a), the semiconductor chip 1 and the holding portion 5b
The semi-finished product of FIG. 9D to which is adhered with the adhesive 3 is set in a lead frame sealing mold 12. Then, as shown in FIG. 10B, the sealing resin 14 is injected from the gate port 13 of the mold 12. FIG. 10 shows the state after resin injection.
It is shown in (c). By the steps as described above, FIG.
The semiconductor chip 1 and the holding portion 5b of the inner lead portion are fixed with an adhesive 3 as shown in FIG.
The LOC type semiconductor device sealed at 4 is manufactured. Unnecessary portions of the lead frame 8 are cut from the state of FIG. 10D to complete the semiconductor device.

【００１１】[0011]

【発明が解決しようとする課題】しかしながら従来の半
導体装置製造方法では、半導体チップ１とインナーリー
ド部の保持部分５ｂとを接着剤により接着固定していた
が、接着剤が必要以上に保持部分からはみ出したり、ま
たは接着剤３がインナーリード部と半導体チップ主面と
の隙間を伝って浸延するという課題があった。すなわち
接着剤の余分なはみ出し、または浸延によって、保持部
分の表面にまで接着剤が被覆し、外囲を封止樹脂により
封止した際には熱衝撃等の信頼性に悪影響を及ぼすとい
う問題と、保持部分５ｂの先端部まで接着剤が浸延し、
インナーリード部のボンディング箇所に接着剤が被覆す
ることになり、後工程の金属細線による接続時に金属細
線が接続できないという問題があった。また接着強度の
面では保持部分毎にはみ出しや浸延が発生することによ
り接着強度に差が生じ、信頼性に問題があった。However, in the conventional method of manufacturing a semiconductor device, the semiconductor chip 1 and the holding portion 5b of the inner lead portion are bonded and fixed with an adhesive. There has been a problem that the adhesive 3 protrudes or spreads along a gap between the inner lead portion and the main surface of the semiconductor chip. In other words, when the adhesive is excessively protruded or spread, the surface of the holding portion is covered with the adhesive, and when the outer periphery is sealed with a sealing resin, the reliability is adversely affected by thermal shock and the like. The adhesive spreads to the tip of the holding portion 5b,
The adhesive is coated on the bonding portion of the inner lead portion, and there is a problem that the thin metal wire cannot be connected at the time of connection by the thin metal wire in a later process. In addition, in terms of adhesive strength, there is a difference in the adhesive strength due to the occurrence of protrusion or infiltration in each holding portion, and there has been a problem in reliability.

【００１２】さらに、従来構造の半導体装置でワイヤー
ボンドを行う際、インナーリード部先端をクランパーで
押さえて、半導体チップ１の主面上の端子１ａとインナ
ーリード部８との間を金属細線１１で接続する方法を取
る。従って、従来のインナーリード部の位置を接着剤で
接着した場合、クランパーと接着点との距離が短くなる
為に、インナーリード部の塑性変形が生じ、リード先端
付近が半導体チップ主面と近接することでリードの入力
容量が増加するという問題点があった。Further, when wire bonding is performed in a semiconductor device having a conventional structure, the tip of the inner lead portion is pressed by a clamper, and a thin metal wire 11 is used between the terminal 1 a on the main surface of the semiconductor chip 1 and the inner lead portion 8. Take a way to connect. Therefore, when the position of the conventional inner lead portion is bonded with an adhesive, since the distance between the clamper and the bonding point becomes shorter, plastic deformation of the inner lead portion occurs, and the vicinity of the lead tip is close to the semiconductor chip main surface. As a result, there is a problem that the input capacity of the lead increases.

【００１３】本発明は、前記従来の課題を解決するもの
であり、半導体チップを接着剤を介してリード部分で保
持する構造の半導体装置において、半導体チップとリー
ドの保持部分との接着構造に着目して、接着強度を向上
させつつ接着剤の余分なはみ出しや浸延を防止した半導
体装置及びその製造方法を提供することを目的とする。The present invention solves the above-mentioned conventional problems, and focuses on a bonding structure between a semiconductor chip and a holding portion of a lead in a semiconductor device having a structure in which a semiconductor chip is held at a lead portion via an adhesive. Accordingly, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, in which excess adhesive is prevented from protruding or spreading while improving adhesive strength.

【００１４】さらに、本発明は、リードフレームを半導
体チップの主面に取り付けるためにインナーリード部の
側方から枝分かれした分岐部の先端に設けた分岐パッド
部を半導体チップのコーナー近傍に接着固定することで
樹脂封止の際の流動抵抗のアンバランスにより発生する
半導体チップの正規の位置からのズレや半導体チップの
傾きを防止することを目的とする。Further, according to the present invention, in order to attach the lead frame to the main surface of the semiconductor chip, a branch pad portion provided at the tip of a branch portion branched from the side of the inner lead portion is adhesively fixed near a corner of the semiconductor chip. Accordingly, it is an object of the present invention to prevent a semiconductor chip from deviating from a regular position and an inclination of the semiconductor chip due to an unbalance of flow resistance at the time of resin sealing.

【００１５】[0015]

【課題を解決するための手段】前記課題を解決するため
に本発明の半導体装置は、半導体チップと、リードフレ
ームを前記半導体チップの主面に設けるためにインナー
リード部から枝分かれした分岐部の先端に設けた分岐パ
ッド部と、前記半導体チップと分岐パッド部との間に設
けられた接着剤と、前記半導体チップの端子とインナー
リード部とを電気的に接続する接続手段と、少なくとも
前記半導体チップの外周を封止した封止樹脂と、前記封
止樹脂から露出し、前記インナーリード部と接続したア
ウターリードとよりなる半導体装置であって、前記接着
剤は、前記接続手段をインナーリード部に接続する箇所
から離れて設けられている。According to another aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor chip; and a tip of a branch portion branched from an inner lead portion for providing a lead frame on a main surface of the semiconductor chip. A bonding pad provided on the semiconductor chip, an adhesive provided between the semiconductor chip and the branch pad, connection means for electrically connecting a terminal of the semiconductor chip to an inner lead portion, and at least the semiconductor chip A sealing resin that seals the outer periphery of the semiconductor device, and an outer lead exposed from the sealing resin and connected to the inner lead portion, wherein the adhesive is configured to connect the connecting means to the inner lead portion. It is provided away from the connecting point.

【００１６】また、具体的にはインナーリード部から枝
分かれした分岐部の先端に設けられた分岐パッド部は、
接着面側の表面に錫或いは銅メッキを施し、光熱硬化型
接着剤により半導体チップ表面と接続する際、光を照射
することによって予め仮硬化をするために、少なくとも
１箇所以上の開孔を設けた構造である。この分岐パッド
部は樹脂で封止られる半導体チップのコーナー部３ｍｍ
以内の位置もしくは半導体チップのエッジ部３ｍｍ以内
の位置に少なくとも３点以上配置する。Further, specifically, a branch pad portion provided at the tip of the branch portion branched from the inner lead portion includes:
Provide tin or copper plating on the surface on the side of the bonding surface and provide at least one or more holes in order to preliminarily cure by irradiating light when connecting to the semiconductor chip surface with a photo-thermosetting adhesive. Structure. This branch pad part is a corner part 3 mm of a semiconductor chip sealed with resin.
At least three points are arranged at positions within a range or within 3 mm of the edge of the semiconductor chip.

【００１７】さらに接着固定に使用する接着剤は硬化収
縮率が３％以下のものとする。また半導体装置の製造方
法は、絶縁層がその表面に形成された半導体チップを供
給する工程と、半導体チップを所定の位置に所望の精度
で再配置する工程と、半導体チップ主面の絶縁膜上に光
熱硬化型接着剤を所定の厚みに塗布する工程と、インナ
ーリード部の側方から枝分かれした分岐部の先端に設け
られた分岐パッド部を有するリードフレームを半導体チ
ップ上に供給する工程と、半導体チップ主面の所定の位
置に分岐パッド部が配置されるようにリードフレームを
合わせる工程と、半導体チップ主面と分岐パッド部との
間に設けられた接着剤に光（２９０ｎｍ〜４３６ｎｍの
波長）を照射して接着剤を仮硬化する工程と、さらに前
記接着剤を加熱硬化（１２０℃〜３００℃）することに
より最終硬化する工程と、半導体チップの端子とインナ
ーリード部先端とを金属細線で接続し電気的に導通させ
る工程と、アウターリード部を露出させて半導体チップ
の外囲を封止樹脂で封止する工程とより成るものであ
る。The adhesive used for bonding and fixing has a curing shrinkage of 3% or less. The method of manufacturing a semiconductor device includes a step of supplying a semiconductor chip having an insulating layer formed on a surface thereof, a step of rearranging the semiconductor chip at a predetermined position with a desired accuracy, and a step of disposing the semiconductor chip on the insulating film on the main surface of the semiconductor chip. A step of applying a photo-thermosetting adhesive to a predetermined thickness, and a step of supplying a lead frame having a branch pad portion provided at the tip of a branch portion branched from the side of the inner lead portion onto the semiconductor chip, A step of aligning the lead frame so that the branch pad portion is arranged at a predetermined position on the semiconductor chip main surface; and a step of applying light (wavelength of 290 nm to 436 nm) to the adhesive provided between the semiconductor chip main surface and the branch pad portion. ), Temporarily curing the adhesive by irradiating the adhesive, heat-curing (120 ° C. to 300 ° C.) the adhesive, and finally curing the adhesive; A step of the N'narido tip electrically conductive connected by a metal thin wire, to expose the outer lead portion of the outer circumference of the semiconductor chip are those comprising more the step of sealing with the sealing resin.

【００１８】[0018]

【発明の実施の形態】以下、本発明の一実施形態につい
て図面を参照しながら説明するまず本実施形態の半導体
装置の構成について説明する。図１〜図３に本実施形態
の半導体装置の半製品を示す。各図において、（ａ）は
平面図であり、（ｂ）及び（ｃ）は各Ａ−Ａ１、Ｂ−Ｂ
１、Ｃ−Ｃ１、Ｄ−Ｄ１箇所の断面図である。なお、図
１、図２、図３では、図面を簡略化するために、金属細
線を省略し、各図の（ｂ）において、インナーリード部
先端と半導体チップの端子を省略している。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. First, the configuration of a semiconductor device of the present embodiment will be described. 1 to 3 show semi-finished products of the semiconductor device of the present embodiment. In each figure, (a) is a plan view, and (b) and (c) are A-A1, BB
It is sectional drawing of 1, CC1 and DD1 location. 1, 2 and 3, the thin metal wires are omitted to simplify the drawings, and the end of the inner lead portion and the terminal of the semiconductor chip are omitted in (b) of each drawing.

【００１９】図１（ａ）、図１（ｂ）、図１（ｃ）に示
す構成は、最上層が絶縁層１５を有する半導体チップ１
と、インナーリード部８と、リードフレーム５を半導体
チップ１主面に取り付けるためにインナーリード部８の
側方から分岐する分岐部５ｂの先端に設けられ、少なく
とも一箇所以上の貫通孔１６を有する４個の分岐パッド
部５ａと、半導体チップ１に分岐パッド５ａを接着する
ために塗布された光熱硬化型接着剤３とにより構成され
ている。The configuration shown in FIGS. 1A, 1B, and 1C is a semiconductor chip 1 having an insulating layer 15 as an uppermost layer.
And at least one through hole 16 provided at an end of a branch portion 5b branched from the side of the inner lead portion 8 for attaching the inner lead portion 8 and the lead frame 5 to the main surface of the semiconductor chip 1. It is composed of four branch pad portions 5a and a photo-thermosetting adhesive 3 applied for bonding the branch pads 5a to the semiconductor chip 1.

【００２０】分岐パッド部５ａは、半導体チップ１の端
子１ａとインナーリード部８先端とを電気的に接続する
接続手段（金属細線）がボンディングしている箇所から
離れた所に位置する。すなわち、分岐パッド５ａは、イ
ンナーリード部８のつけ根側方から分岐した分岐部５ｂ
の先端で、インナーリード部８の先端から離れた位置に
形成されたものである。したがって、光熱硬化型接着剤
３は、インナーリード部８の先端から離れた分岐パッド
５ａに塗布される。The branch pad portion 5a is located at a position distant from the portion where the connecting means (fine metal wire) for electrically connecting the terminal 1a of the semiconductor chip 1 and the tip of the inner lead portion 8 is bonded. That is, the branch pad 5a is provided with a branch portion 5b branched from the base side of the inner lead portion 8.
And formed at a position apart from the tip of the inner lead portion 8. Therefore, the photothermosetting adhesive 3 is applied to the branch pad 5 a away from the tip of the inner lead portion 8.

【００２１】なお、分岐パッド部５ａの数は前記のよう
に４個には限定されないが、２箇所しか無い場合、樹脂
成形工程の樹脂注入時に溶融樹脂の流動バランスの崩れ
から、半導体チップが回転して実用に耐えないので、少
なくとも３個以上必要である。The number of branch pads 5a is not limited to four as described above, but if there are only two, the semiconductor chip is rotated due to a loss of the flow balance of the molten resin during resin injection in the resin molding process. Therefore, at least three or more are necessary.

【００２２】接着固定に使用する接着剤は硬化収縮率が
３％以下のものが好ましい。すなわち、半導体チップ１
の主面で複数の分岐パッド部５ａを支持した場合、収縮
率の大きい接着剤を使用すると、各支持した支点の収縮
バランスが崩れた時、半導体チップ１が傾斜する不都合
が生じる。したがって、接着剤は硬化収縮率が３％以下
のものが好ましい。The adhesive used for the adhesive fixing preferably has a curing shrinkage of 3% or less. That is, the semiconductor chip 1
When a plurality of branch pad portions 5a are supported on the main surface of the above, if an adhesive having a large shrinkage ratio is used, there is a problem that the semiconductor chip 1 is inclined when the shrinkage balance of each supported fulcrum is lost. Therefore, the adhesive preferably has a cure shrinkage of 3% or less.

【００２３】光熱硬化型接着剤３は、例えば、エポキシ
系樹脂や感光性樹脂等を主成分とする液状樹脂に、Ｓｉ
Ｏ2 （二酸化珪素）の微粉末を前記液状樹脂に対して重
量比で５０〜８０％を混合してものを用いる。ただし、
この光熱硬化型接着剤３は、かかる成分や配合割合に限
定されない。The photothermosetting adhesive 3 is made of, for example, a liquid resin mainly composed of an epoxy resin or a photosensitive resin,
A mixture of a fine powder of O 2 (silicon dioxide) in a weight ratio of 50 to 80% with respect to the liquid resin is used. However,
The photothermosetting adhesive 3 is not limited to such components and mixing ratios.

【００２４】なお、エポキシ系の樹脂を主成分とする接
着剤は、リードフレーム材（Ｆｅ−Ｎｉ合金）や銀メッ
キ面との接着力が弱く、銅や錫とは強く接着するので、
分岐パッド部の被接着面は、錫もしくは銅を５μｍ以下
の厚みにメッキしてある。The adhesive containing an epoxy resin as a main component has a low adhesive strength to a lead frame material (Fe-Ni alloy) or a silver-plated surface, and strongly adheres to copper or tin.
The surface to be bonded of the branch pad portion is plated with tin or copper to a thickness of 5 μm or less.

【００２５】図２（ａ）、図２（ｂ）は、図１（ａ）、
図１（ｂ）の分岐パッド部５ａの配置数が異なる場合の
他の実施の形態である。図２の実施の形態は、分岐パッ
ド部５ａの構成が、図１の実施の形態より一対多く形成
され、中央部のインナーリード部８に分岐パッド部５ａ
が形成されている。この実施の形態の分岐パッド５ａも
インナーリード部８の先端部から離れた位置にある。FIGS. 2 (a) and 2 (b) correspond to FIGS.
This is another embodiment in which the number of arranged branch pad portions 5a in FIG. 1B is different. In the embodiment of FIG. 2, the configuration of the branch pad portion 5 a is formed in a pair more than that of the embodiment of FIG.
Are formed. The branch pad 5a of this embodiment is also at a position away from the tip of the inner lead portion 8.

【００２６】図３（ａ）、図３（ｂ）は、分岐パッド部
面に設けた貫通孔の数が図１（ａ）、図１（ｂ）の分岐
パッド部の面に設けた貫通孔１６の数と異なる場合の他
の実施の形態である。この図３の実施の形態の分岐パッ
ド部５ａは、先端部が三角形をし、基端部が矩形をして
おり、この分岐パッド部５ａに三角形と矩形の貫通孔が
それぞれ１個づつ形成されている。もちろん、分岐パッ
ド部５ａの形状や貫通孔の形状、数量等は本実施の形態
に限定されないことは言うまでもない。FIGS. 3 (a) and 3 (b) show that the number of through holes provided on the surface of the branch pad portion is equal to the number of through holes provided on the surface of the branch pad portion shown in FIGS. 1 (a) and 1 (b). This is another embodiment in the case where the number is different from 16. The branch pad portion 5a of the embodiment of FIG. 3 has a triangular distal end portion and a rectangular base end portion. Triangular and rectangular through holes are respectively formed in the branch pad portion 5a. ing. Of course, it goes without saying that the shape of the branch pad portion 5a, the shape and the number of through holes, and the like are not limited to the present embodiment.

【００２７】上記実施の形態のように、分岐パッド５ａ
がインナーリード部８の先端部から離れて設けられ、し
かも、本発明の構造のインナーリード部８先端が半導体
チップ１主面から３０〜１９０μｍ上に浮いた状態で位
置することで、このインナーリード部８の先端と半導体
チップ１の端子間に金属細線でワイヤーボンディングす
る際に、インナーリード部８の先端を押さえることによ
り生じるインナーリード部８先端の塑性変形が防止でき
る。As in the above embodiment, the branch pad 5a
Is provided apart from the tip of the inner lead portion 8, and the tip of the inner lead portion 8 of the structure of the present invention is positioned above the main surface of the semiconductor chip 1 by 30 to 190 μm so that this inner lead is formed. When performing wire bonding between the tip of the portion 8 and the terminal of the semiconductor chip 1 with a thin metal wire, plastic deformation of the tip of the inner lead portion 8 caused by pressing the tip of the inner lead portion 8 can be prevented.

【００２８】さらに、光熱硬化型接着剤３の粘度は、余
分な浸延やタレ下がりを防止する観点から５０ｐｏｉｓ
ｅ〜５００ｐｏｉｓｅのものを使用することが好まし
い。しかし、接着剤に粘度の低い光熱硬化型接着剤３を
使用して浸延が生じた場合でも、分岐パッド５ａがイン
ナーリード部８の先端部から離れて設けられているた
め、インナーリード部８の先端部にまで光熱硬化型接着
剤３が及ぶことはなく、後工程の金属細線による接続に
も支障を生じない。Further, the viscosity of the photo-thermosetting adhesive 3 is set to 50 pois from the viewpoint of preventing excessive spreading and sagging.
It is preferable to use e-500 poise. However, even when the photothermosetting adhesive 3 having a low viscosity is used as the adhesive, the branch pad 5a is provided away from the tip of the inner lead portion 8, so that the inner lead portion 8 is not provided. The photothermosetting adhesive 3 does not reach the front end of the substrate, and there is no hindrance to the connection by a fine metal wire in a later step.

【００２９】また、本発明のリードフレームを構成する
分岐パッド５ａのパターンは、分岐パッド５ａの中心点
が樹脂封止される半導体チップ１主面の各辺のエッジか
ら３ｍｍ以内の点に配置することが好ましい。The pattern of the branch pad 5a constituting the lead frame of the present invention is arranged at a point where the center point of the branch pad 5a is within 3 mm from the edge of each side of the main surface of the semiconductor chip 1 to be resin-sealed. Is preferred.

【００３０】また、本発明は、配置された分岐パッド部
５ａの面には少なくとも１箇所以上の貫通孔１６を設け
る。前記貫通孔１６の形成は、本発明半導体装置を組み
立てるに当り、半導体チップ主面と分岐パッド部５ａを
接着剤３により接着する際に、設備の時間当りの処理数
量の向上を図るために設けてたものである。即ち、光熱
硬化型接着剤３を用いた硬化は、光による短時間仮硬化
と、熱によるバッチ処理もしくはインライン硬化から成
りる。仮硬化は分岐パッド部５ａでリードフレーム５が
取り付けられた半導体チップを次工程に送る際、半導体
チップ１からリードフレームが脱落するのを防止するこ
とが目的であり、前記条件を満たす接着強化を必要とす
る。貫通孔は、以上の理由から光照射面積を確保し、接
着強化の維持に貢献することを狙いとして形成されたも
のである。In the present invention, at least one or more through holes 16 are provided on the surface of the arranged branch pad portion 5a. The formation of the through holes 16 is provided to improve the processing quantity per unit time of the equipment when the semiconductor chip main surface and the branch pad portion 5a are bonded by the adhesive 3 in assembling the semiconductor device of the present invention. It was something. That is, the curing using the photo-thermosetting adhesive 3 includes short-time temporary curing by light and batch processing or in-line curing by heat. Preliminary curing is intended to prevent the lead frame from falling off from the semiconductor chip 1 when the semiconductor chip to which the lead frame 5 is attached at the branch pad portion 5a is sent to the next step. I need. The through-hole is formed for the purpose of securing a light irradiation area and contributing to maintenance of adhesion reinforcement for the above reasons.

【００３１】さらに、分岐パッド部５ａは、具体的には
少なくとも半導体チップ１の４つのコーナーの対角線に
対して±３０゜内に配置する。この角度、すなわち接着
位置は次のような理由から重要になる。即ち、樹脂封止
工程で熱硬化型樹脂を用いて金型内に溶融樹脂を注入す
る時、樹脂は注入時間の経過と共に粘度上昇が生じる。
その時、金型内に配置される半導体チップ１は、チップ
主面の接着点と前記接着点の支持部分が前記角度範囲か
ら外れた場合、半導体チップ１の上側と下側の溶融樹脂
の流れの不均衡等で、その時の半導体チップ上下面での
流動抵抗の不均衡増幅により、金型内半導体チップ１が
元の位置から大きく上下に逸脱する。すなわち、半導体
チップ１の上側または下側の各面と、金型壁面との間隔
に違いがあれば、樹脂が流動する圧力に差が生じ、圧力
の大きい流れが小さい流れの方に半導体チップ１を押し
動かすことになる。これを防止するために、分岐パッド
部５ａは、半導体チップ１の４つのコーナーの対角線上
に配置し、その有効範囲として±３０゜を設定した。Further, the branch pad portion 5a is specifically arranged at least within ± 30 ° with respect to a diagonal line of four corners of the semiconductor chip 1. This angle, that is, the bonding position is important for the following reasons. That is, when the molten resin is injected into the mold using the thermosetting resin in the resin sealing step, the viscosity of the resin increases with the elapse of the injection time.
At this time, the semiconductor chip 1 placed in the mold is configured such that when the bonding point of the chip main surface and the supporting portion of the bonding point are out of the angle range, the flow of the molten resin above and below the semiconductor chip 1 is reduced. Due to imbalance or the like, the imbalance in the flow resistance on the upper and lower surfaces of the semiconductor chip at that time causes the semiconductor chip 1 in the mold to largely deviate vertically from the original position. That is, if there is a difference in the distance between the upper surface or the lower surface of the semiconductor chip 1 and the mold wall surface, a difference occurs in the pressure at which the resin flows, and the semiconductor chip 1 moves in the direction where the flow with a large pressure is smaller than the flow with a smaller pressure. Will be pushed. In order to prevent this, the branch pad portion 5a is arranged on a diagonal line of four corners of the semiconductor chip 1, and its effective range is set to ± 30 °.

【００３２】また、半導体チップ１主面と分岐パッド５
ａの接着固定は、光熱硬化型接着剤３の使用で分岐パッ
ド５ａの貫通孔１６から照射される２９０ｎｍ〜４３６
ｎｍの波長の光による仮硬化と、熱による最終硬化を採
用する。その結果、仮硬化の採用は設備当たりの組立能
力が飛躍的に増加する。The main surface of the semiconductor chip 1 and the branch pad 5
The adhesive fixing of a is performed by using the photo-thermosetting adhesive 3 and irradiating from the through-hole 16 of the branch pad 5a to 290 nm to 436.
Temporary curing with light having a wavelength of nm and final curing with heat are employed. As a result, the use of temporary curing dramatically increases the assembly capacity per facility.

【００３３】次に本実施形態の半導体装置の製造方法に
ついて図面を参照しながら説明する。図４〜図６は本発
明の半導体装置の製造方法を示す断面図である。Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to the drawings. 4 to 6 are sectional views showing a method for manufacturing a semiconductor device according to the present invention.

【００３４】まず、図４を用いて、半導体チップ１の主
面に分岐パッド部５ａを介してリードフレームを接着す
る半導体チップ１接着工程（ダイスボンド工程）につい
て説明する。First, a semiconductor chip 1 bonding step (die bonding step) of bonding a lead frame to the main surface of the semiconductor chip 1 via the branch pad portion 5a will be described with reference to FIG.

【００３５】図４（ａ）に示すように半導体チップ１を
真空取り付け可能なステージ６上に載置する。ここでは
半導体チップ１が不要な移動を起こさないように真空吸
着により固定する。ステージ６にはリードフレーム５の
位置を規制するピン２ａが設けられている。As shown in FIG. 4A, the semiconductor chip 1 is mounted on a stage 6 which can be mounted in a vacuum. Here, the semiconductor chip 1 is fixed by vacuum suction so as not to cause unnecessary movement. The stage 6 is provided with pins 2 a for regulating the position of the lead frame 5.

【００３６】そして図４（ｂ）に示すように、半導体チ
ップ１上の所定の位置に、光熱硬化型接着剤３をノズル
４により塗布する。所定の位置とは、リードフレーム５
を半導体チップ１主面に取り付けるために、分岐部５ｂ
の先端に形成された分岐パッド部５ａを、半導体チップ
主面に接着する箇所を言う。Then, as shown in FIG. 4B, a photothermosetting adhesive 3 is applied to a predetermined position on the semiconductor chip 1 by a nozzle 4. The predetermined position means that the lead frame 5
To attach the semiconductor chip 1 to the main surface of the semiconductor chip 1,
Refers to a portion where the branch pad portion 5a formed at the tip of the semiconductor chip is bonded to the main surface of the semiconductor chip.

【００３７】つぎに、図４（ｃ）に示すように、光熱硬
化型接着剤３が塗布された半導体チップ１と、リードフ
レーム５とを位置合わせする。リードフレーム５はその
外側の位置規制孔にステージ２に設けたピン２ａを挿通
することにより規制される。Next, as shown in FIG. 4C, the semiconductor chip 1 on which the photothermosetting adhesive 3 is applied and the lead frame 5 are aligned. The lead frame 5 is regulated by inserting a pin 2a provided on the stage 2 into a position regulating hole on the outside thereof.

【００３８】そして、図４（ｄ）に示すように２９０ｎ
ｍ〜４３６ｎｍの波長の光をリードフレーム５の分岐パ
ッド部５ａ上から貫通孔１６を介して１〜１０秒照射
し、光が浸入する深さまで仮硬化を行う。Then, as shown in FIG.
Light having a wavelength of m to 436 nm is irradiated from above the branch pad portion 5a of the lead frame 5 through the through hole 16 for 1 to 10 seconds, and temporary curing is performed to a depth at which the light penetrates.

【００３９】前記のように、分岐パッド部５ａと半導体
チップ１とを仮接着した後、図４（ｅ）に示すように、
１２０℃〜３００℃の温度で３０分〜６０分間硬化炉ス
テージ１７で最終硬化を行って光熱硬化型接着剤３を硬
化させる。光熱硬化型接着剤３の硬化は光と加熱で順次
処理する方法と、加熱のみで処理する方法の２通りがあ
る。After temporarily bonding the branch pad portion 5a and the semiconductor chip 1 as described above, as shown in FIG.
The final curing is performed in the curing furnace stage 17 at a temperature of 120 ° C. to 300 ° C. for 30 minutes to 60 minutes to cure the photothermographic adhesive 3. There are two methods for curing the photothermosetting adhesive 3: a method of sequentially processing with light and heating, and a method of processing only with heating.

【００４０】次にワイヤーボンド工程について説明す
る。図５（ａ）に示すように、ヒーターブロック７上
に、リードフレーム５を取り付けた半導体チップ１を真
空吸着により固定する。なお図中、半導体チップ１とリ
ードフレーム５とは分離しているように示しているが、
前記した分岐パッド部５ａは、半導体チップと接続して
いるものであり、図示している箇所は、リードフレーム
５の半導体チップ１と電気的な接続を行うインナーリー
ド部８の断面である。Next, the wire bonding step will be described. As shown in FIG. 5A, the semiconductor chip 1 to which the lead frame 5 is attached is fixed on the heater block 7 by vacuum suction. In the figure, although the semiconductor chip 1 and the lead frame 5 are shown as being separated,
The branch pad portion 5a is connected to the semiconductor chip, and the illustrated portion is a cross section of the inner lead portion 8 for making an electrical connection with the semiconductor chip 1 of the lead frame 5.

【００４１】次に、図５（ｂ）に示すように、クランパ
ー９ａ、９ｂによりインナーリード部８及びリードフレ
ーム５を押さえ、絶縁層１５で保護された半導体チップ
１主面上にインナーリード部８を接触させる。そして、
ワイヤーボンダーのキャピラリー１０を用いて金属細線
１１によってインナーリード部８と半導体チップ１の端
子１ａとを接続する。ここで半導体チップ１主面上にイ
ンナーリード部８を接触させる目的は、金属細線１１の
接続を安定に行うためである。Next, as shown in FIG. 5B, the inner lead portion 8 and the lead frame 5 are pressed by the clampers 9a and 9b, and the inner lead portion 8 is placed on the main surface of the semiconductor chip 1 protected by the insulating layer 15. Contact. And
The inner lead portion 8 and the terminal 1 a of the semiconductor chip 1 are connected by the thin metal wire 11 using the capillary 10 of a wire bonder. Here, the purpose of bringing the inner lead portion 8 into contact with the main surface of the semiconductor chip 1 is to stably connect the thin metal wires 11.

【００４２】さらに、図５（ｃ）に示すようにクランパ
ー９ａ、９ｂを除去することにより、インナーリード部
８が元の状態に戻り、図５（ｄ）に示すようにインナー
リード部８と半導体チップ１とが金属細線１１により電
気的に接続される。Further, by removing the clampers 9a and 9b as shown in FIG. 5 (c), the inner lead portion 8 returns to the original state, and as shown in FIG. The chip 1 is electrically connected by the thin metal wires 11.

【００４３】次に樹脂封止工程について説明する。図６
（ａ）に示すように、分岐パッド部５ａを介してリード
フレーム５が光熱硬化型接着剤３により接着固定された
半導体チップ１を封止用の金型１２内にセットする。Next, the resin sealing step will be described. FIG.
As shown in (a), the semiconductor chip 1 to which the lead frame 5 is adhered and fixed by the photothermosetting adhesive 3 via the branch pad portion 5a is set in a mold 12 for sealing.

【００４４】そして図６（ｂ）に示すように、金型１２
のゲート口１３より封止樹脂１４を注入する。樹脂注入
後の状態を図６（ｃ）に示す。以上のような工程により
図６（ｄ）に示すように、半導体チップ１にリードフレ
ーム５の分岐パッド部５ａを光熱硬化型接着剤３により
固定し、外周を封止樹脂１４で封止したＬＯＣ型の半導
体装置が製造される。Then, as shown in FIG.
The sealing resin 14 is injected from the gate port 13 of FIG. FIG. 6C shows the state after the resin injection. As shown in FIG. 6D, the LOC in which the branch pad portion 5a of the lead frame 5 is fixed to the semiconductor chip 1 with the photothermosetting adhesive 3 and the outer periphery is sealed with the sealing resin 14 as shown in FIG. The semiconductor device of the mold is manufactured.

【００４５】以上、本実施形態の半導体装置の製造方法
は、少なくとも、半導体チップ１にリードフレーム５を
取り付ける分岐パッド部５ａを有し、分岐パッド部５ａ
の面は１箇所以上の貫通孔１６を有し、半導体チップ１
の端子１ａと電気的に接続する部分が分岐パッド部５ａ
から離れているインナーリード部８と、インナーリード
部８と接続したアウターリード部とを有するリードフレ
ーム５を用いて、半導体チップ１をリードで接着固定し
たタイプの半導体装置を製造する場合に用いる。As described above, the method of manufacturing a semiconductor device according to the present embodiment has at least the branch pad portion 5a for attaching the lead frame 5 to the semiconductor chip 1, and the branch pad portion 5a
Has one or more through-holes 16 in the semiconductor chip 1.
The portion electrically connected to the terminal 1a is a branch pad portion 5a.
It is used when manufacturing a semiconductor device of a type in which the semiconductor chip 1 is bonded and fixed with leads using a lead frame 5 having an inner lead portion 8 separated from the inner lead portion and an outer lead portion connected to the inner lead portion 8.

【００４６】分岐パッド部５ａが貫通孔１６を有するこ
とより、貫通孔１６を通して光熱硬化型接着剤３を硬化
させるために必要な（波長２９０ｎｍ〜４３６ｎｍの）
光を直接光熱硬化型接着剤３に照射することが出来る。
このため、分岐パッド部５ａの貫通孔１６から露出した
光熱硬化型接着剤３に光が当り、光が侵入した深さまで
接着剤３が硬化する。従って、本発明の製造方法によ
り、接着強度の向上と共に製造工程におけるインデック
スの時間短縮が図れて製造効率を向上させる事が出来る
ものである。Since the branch pad portion 5a has the through hole 16, it is necessary to cure the photothermosetting adhesive 3 through the through hole 16 (wavelength 290 nm to 436 nm).
Light can be directly applied to the photothermosetting adhesive 3.
For this reason, light hits the photo-thermosetting adhesive 3 exposed from the through hole 16 of the branch pad portion 5a, and the adhesive 3 is cured to a depth at which the light has entered. Therefore, according to the manufacturing method of the present invention, it is possible to improve the bonding efficiency and shorten the index time in the manufacturing process, thereby improving the manufacturing efficiency.

【００４７】なお、本実施形態で用いる光熱硬化型接着
剤３は、超高圧水銀灯のｇ線やｉ線または２９０ｎｍの
波長及びハロゲンランプの発光波長に感光感度を有し、
粘度は光熱硬化型接着剤３の余分な浸延やタレ下がりを
防止する観点から５０ｐｏｉｓｅ〜５００ｐｏｉｓｅの
ものとする。The photo-thermosetting adhesive 3 used in the present embodiment has photosensitivity to g-line or i-line of an ultra-high pressure mercury lamp or a wavelength of 290 nm and an emission wavelength of a halogen lamp.
The viscosity is set to 50 poise to 500 poise from the viewpoint of preventing the photothermosetting adhesive 3 from being excessively spread or sagged.

【００４８】以上、本実装形態ではインナーリード部８
から枝分かれした分岐パッド部５ａと、半導体チップ１
主面とを光熱硬化型接着剤３により接着固定する際、イ
ンナーリード部８は、分岐パッド部５ａのボンディング
箇所から離れて設けられているので、光熱硬化型接着剤
３が余分に浸延してもインナーリード部８まで延在する
危険性がなく金属細線１１の接続不良誘発を防止する。As described above, in this embodiment, the inner lead portion 8
Pad portion 5a branched from the semiconductor chip 1
When the main surface is bonded and fixed with the photothermosetting adhesive 3, the inner lead portion 8 is provided apart from the bonding portion of the branch pad portion 5a, so that the photothermosetting adhesive 3 is excessively spread. However, there is no danger of extending to the inner lead portion 8 and the occurrence of poor connection of the thin metal wires 11 is prevented.

【００４９】[0049]

【発明の効果】以上、本発明の半導体装置は、インナー
リード部と枝分かれして形成される分岐パッド部と、半
導体チップ主面とを光熱硬化型接着剤により接着固定す
るタイプの半導体装置であって、前記分岐パッド部はイ
ンナーリード部の先端部から離されて設けられているの
で、半導体チップ主面に分岐パッド部を接着した際に光
熱硬化型接着剤が余分にはみ出しても、はみ出した光熱
硬化型接着剤はインナーリード部の先端部まで延在する
ことなく、接続不良を防止できるものである。As described above, the semiconductor device of the present invention is a semiconductor device of a type in which a branch pad portion formed by branching from an inner lead portion and a main surface of a semiconductor chip are adhered and fixed with a photo-thermosetting adhesive. Since the branch pad portion is provided apart from the tip of the inner lead portion, even if the photothermosetting adhesive excessively protrudes when the branch pad portion is bonded to the semiconductor chip main surface, it protrudes. The photo-thermosetting adhesive can prevent poor connection without extending to the tip of the inner lead portion.

【００５０】また、本発明の半導体装置は、インナーリ
ード部の先端部が半導体チップ主面と所定の間隔を保っ
て浮いている構造となる。一方、インナーリード部は分
岐パッド部と分岐し、金属細線で半導体チップの端子と
接続されるインナーリード部の先端は、半導体チップの
主面に光熱硬化型接着剤により接着固定されている分岐
パッド部と離れている。従って、ワイヤーボンディング
時にインナーリード部先端近傍をクランパーで押さえて
もインナーリード部は塑性変形を起こさず元の状態に復
帰できるものである。Further, the semiconductor device of the present invention has a structure in which the tip of the inner lead portion is floated at a predetermined distance from the main surface of the semiconductor chip. On the other hand, the inner lead part is branched from the branch pad part, and the tip of the inner lead part connected to the terminal of the semiconductor chip with a thin metal wire is bonded and fixed to the main surface of the semiconductor chip with a photo-thermosetting adhesive. Away from the department. Therefore, even when the vicinity of the tip of the inner lead portion is pressed by the clamper during wire bonding, the inner lead portion can be returned to the original state without causing plastic deformation.

【００５１】さらに、本発明の半導体装置は搭載する半
導体チップコーナーの対角線近傍の少なくとも３箇所以
上に分岐パッド部を設けることで、樹脂封止の際の半導
体チップ傾きや正規の位置からの上下への移動が防止出
来るものである。Further, in the semiconductor device of the present invention, the branch pads are provided in at least three places near the diagonal line of the corner of the semiconductor chip to be mounted. Movement can be prevented.

【図面の簡単な説明】[Brief description of the drawings]

【図１】（ａ）は本発明の一実施形態の半導体装置の半
製品を示す平面図、（ｂ）は図１（ａ）のＡ−Ａ１線断
面図、（ｃ）は同、Ｂ−Ｂ１線断面図である。1A is a plan view showing a semi-finished product of a semiconductor device according to an embodiment of the present invention, FIG. 1B is a cross-sectional view taken along line A-A1 of FIG. 1A, and FIG. It is a B1 line sectional view.

【図２】（ａ）は本発明の他の実施形態の半導体装置の
半製品を示す平面図、（ｂ）は図２（ａ）のＣ−Ｃ１線
断面図である。2A is a plan view showing a semi-finished product of a semiconductor device according to another embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along line C-C1 of FIG. 2A.

【図３】（ａ）は本発明のさらに他の実施形態の半導体
装置の半製品を示す平面図、（ｂ）は図３（ａ）のＤ−
Ｄ１線断面図である。FIG. 3A is a plan view showing a semi-finished product of a semiconductor device according to still another embodiment of the present invention, and FIG.
It is D1 line sectional drawing.

【図４】本発明の一実施形態の半導体装置の製造方法
（チップ接着工程）を示す断面図である。FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device (chip bonding step) according to one embodiment of the present invention;

【図５】本発明の一実施形態の半導体装置の製造方法
（ワイヤーボンド工程）を示す断面図である。FIG. 5 is a cross-sectional view illustrating a method for manufacturing a semiconductor device (wire bonding step) according to one embodiment of the present invention;

【図６】本発明の一実施形態の半導体装置の製造方法
（樹脂封止工程）を示す断面図である。FIG. 6 is a cross-sectional view illustrating a method for manufacturing a semiconductor device (resin sealing step) according to one embodiment of the present invention;

【図７】（ａ）は従来の半導体装置の半製品を示す平面
図、（ｂ）は図７（ａ）のＥ−Ｅ１部断面図である。7A is a plan view showing a semi-finished product of a conventional semiconductor device, and FIG. 7B is a cross-sectional view taken along the line E-E1 of FIG. 7A.

【図８】従来の半導体装置の製造方法（チップ接着工
程）を示す断面図である。FIG. 8 is a cross-sectional view showing a conventional semiconductor device manufacturing method (chip bonding step).

【図９】従来の半導体装置の製造方法（ワイヤーボンド
工程）を示す断面図である。FIG. 9 is a cross-sectional view showing a conventional semiconductor device manufacturing method (wire bonding step).

【図１０】従来の半導体装置の製造方法（樹脂封止工
程）を示す断面図である。FIG. 10 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device (resin sealing step).

【符号の説明】[Explanation of symbols]

１ 半導体チップ １ａ 端子 ２ ステージ（チップ接着装置） ２ａ ピン ３ 光熱硬化型接着剤（接着剤） ４ ノズル ５ リードフレーム ５ａ 分岐パッド部 ５ｂ インナーリード部の保持部分 ５ｃ 分岐部 ６ ステージ ７ ヒーターブロック（ワイヤーボンダー） ８ インナーリード部 ９ａ クランパー（フレーム） ９ｂ クランパー（インナーリード部） １０ キャピラリー １１ 金属細線 １２ 金型 １３ ゲート口 １４ 封止樹脂 １５ 絶縁層 １６ 貫通孔 １７ 硬化炉ステージ Reference Signs List 1 semiconductor chip 1a terminal 2 stage (chip bonding device) 2a pin 3 photothermosetting adhesive (adhesive) 4 nozzle 5 lead frame 5a branch pad portion 5b inner lead holding portion 5c branch portion 6 stage 7 heater block (wire Bonder) 8 Inner lead portion 9a Clamper (frame) 9b Clamper (inner lead portion) 10 Capillary 11 Fine metal wire 12 Mold 13 Gate opening 14 Sealing resin 15 Insulating layer 16 Through hole 17 Curing furnace stage

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップと、 リードフレームを前記半導体チップの主面に設けるため
にインナーリード部から枝分かれした分岐部の先端に設
けられた分岐パッド部と、 前記半導体チップと前記分岐パッド部との間に設けられ
た接着剤と、 前記半導体チップの端子と前記インナーリード部とを電
気的に接続する接続手段と、 少なくとも前記半導体チップの外周を封止した封止樹脂
と、 前記封止樹脂から露出し、前記インナーリード部と接続
したアウターリードと、 よりなることを特徴とする半導体装置。A semiconductor chip; a branch pad provided at an end of a branch branched from an inner lead for providing a lead frame on a main surface of the semiconductor chip; and a semiconductor chip and the branch pad. An adhesive provided therebetween, a connecting means for electrically connecting a terminal of the semiconductor chip and the inner lead portion, a sealing resin for sealing at least an outer periphery of the semiconductor chip, and a sealing resin And an outer lead exposed from the inner lead portion and connected to the inner lead portion. 【請求項２】 前記半導体チップの主面と前記分岐パッ
ド部との間を接続する接着剤は、２９０ｎｍ〜４３６ｎ
ｍの波長の光および／または熱で硬化反応が進行し、硬
化後の硬化収縮率は３％以下であることを特徴とする請
求項１に記載の半導体装置。2. An adhesive for connecting between a main surface of the semiconductor chip and the branch pad portion, the adhesive being 290 nm to 436 nm.
2. The semiconductor device according to claim 1, wherein the curing reaction proceeds by light and / or heat having a wavelength of m, and a curing shrinkage rate after curing is 3% or less. 3. 【請求項３】 光熱硬化型接着剤の粘度が、５０ｐｏｉ
ｓｅ〜５００ｐｏｉｓｅのものを使用したことを特徴と
する請求項２に記載の半導体装置。3. The photothermosetting adhesive has a viscosity of 50 poi.
3. The semiconductor device according to claim 2, wherein said semiconductor device has a se of 500 to 500 poise. 【請求項４】 前記分岐パッド部は、１箇所以上の貫通
孔を有することを特徴とする請求項１に記載の半導体装
置。4. The semiconductor device according to claim 1, wherein the branch pad has one or more through holes. 【請求項５】 前記分岐パッド部の被接着面は、錫もし
くは銅を５μｍ以下の厚みにメッキすることを特徴とす
る請求項１または４に記載の半導体装置。5. The semiconductor device according to claim 1, wherein the surface to be bonded of the branch pad portion is plated with tin or copper to a thickness of 5 μm or less. 【請求項６】 前記分岐パッド部から成る接着部は、少
なくとも半導体チップ主面の３箇所以上に位置すること
を特徴とする請求項１、４、５のいずれか１項に記載の
半導体装置。6. The semiconductor device according to claim 1, wherein said bonding portion comprising said branch pad portion is located at least at three or more positions on a main surface of said semiconductor chip. 【請求項７】 分岐パッド部は、半導体チップの４つの
コーナーの対角線に対して±３０゜内に配置することを
特徴とする請求項１、４〜６のいずれか１項に記載の半
導体装置。7. The semiconductor device according to claim 1, wherein the branch pad portion is disposed within ± 30 ° with respect to a diagonal line of four corners of the semiconductor chip. . 【請求項８】 前記分岐パッド部は、その中心が前記半
導体チップのエッジから３ｍｍ以内の点に設けることを
特徴とする請求項１、４〜７のいずれか１項に記載の半
導体装置。8. The semiconductor device according to claim 1, wherein said branch pad portion is provided at a point whose center is within 3 mm from an edge of said semiconductor chip. 【請求項９】 チップ接着工程において、２９０ｎｍ〜
４３６ｎｍの波長の光および／または熱で硬化反応が進
行し、硬化後の硬化収縮率は３％以下である光熱硬化型
接着剤を用い、リードフレームを半導体チップの主面に
設けるために、インナーリード部から枝分かれした分岐
部の先端に設けられた分岐パッド部と、半導体チップ主
面とを接着するに当り、予め光による仮硬化を行った
後、熱による最終硬化を行うことを特徴とする半導体装
置の製造方法。9. The method according to claim 9, wherein in the chip bonding step, the
The curing reaction proceeds by light and / or heat having a wavelength of 436 nm, and a curing contraction rate after curing is 3% or less. In bonding the branch pad portion provided at the tip of the branch portion branched from the lead portion to the main surface of the semiconductor chip, preliminary curing is performed in advance by light, and then final curing by heat is performed. A method for manufacturing a semiconductor device.
JP19640798A 1998-07-13 1998-07-13 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3805108B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19640798A JP3805108B2 (en) 1998-07-13 1998-07-13 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19640798A JP3805108B2 (en) 1998-07-13 1998-07-13 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2000031200A true JP2000031200A (en) 2000-01-28
JP3805108B2 JP3805108B2 (en) 2006-08-02

Family

ID=16357356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19640798A Expired - Fee Related JP3805108B2 (en) 1998-07-13 1998-07-13 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP3805108B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7414303B2 (en) 2004-03-23 2008-08-19 Samsung Electronics Co., Ltd. Lead on chip semiconductor package
US9197218B2 (en) 2013-03-29 2015-11-24 Seiko Epson Corporation Electronic device, electronic apparatus, moving object, and method for manufacturing electronic device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7414303B2 (en) 2004-03-23 2008-08-19 Samsung Electronics Co., Ltd. Lead on chip semiconductor package
US9197218B2 (en) 2013-03-29 2015-11-24 Seiko Epson Corporation Electronic device, electronic apparatus, moving object, and method for manufacturing electronic device

Also Published As

Publication number Publication date
JP3805108B2 (en) 2006-08-02

Similar Documents

Publication Publication Date Title
US5960260A (en) Semiconductor device, its manufacturing method, and dicing adhesive element therefor
JP2871800B2 (en) Method of manufacturing hybrid semiconductor structure and synthetic hybrid semiconductor structure
US7534652B2 (en) Microelectronic elements with compliant terminal mountings and methods for making the same
US6373142B1 (en) Method of adding filler into a non-filled underfill system by using a highly filled fillet
JP2000260819A (en) Manufacture of semiconductor device
JP3631922B2 (en) Manufacturing method of center pad type semiconductor package element
JPH0745641A (en) Semiconductor device mounting method
US7148083B2 (en) Transfer mold semiconductor packaging processes
JP2000031200A (en) Semiconductor device and its manufacture
JP3014577B2 (en) Method for manufacturing semiconductor device
JP3381563B2 (en) Method for manufacturing semiconductor device
JP3274314B2 (en) Resin-sealed semiconductor device and method of manufacturing the same
JP2797598B2 (en) Hybrid integrated circuit board
JP2902497B2 (en) Manufacturing method of hybrid integrated circuit board
US7008493B2 (en) Method for applying a semiconductor chip to a carrier element
JPH0974149A (en) Small package and manufacture
JPS6313337A (en) Process of mounting semiconductor element
JP2914569B1 (en) Semiconductor device mounting method and its mounting body
JP3045121B2 (en) Semiconductor device and method of manufacturing semiconductor device
JPH0888248A (en) Face-down bonding method and connecting material using thereof
JPH1098077A (en) Production of semiconductor device
JPH03283552A (en) Hybrid integrated circuit substrate
JPH08204048A (en) Sealing structure of semiconductor chip
JP3277830B2 (en) How to assemble electronic components
JPH02101753A (en) Semiconductor chip attached structure

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050131

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20051221

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060110

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060313

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20060411

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20060509

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100519

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110519

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees