JP2000029663A - Data shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data shift circuit capable of a high-speed processing by simple and regular wiring. SOLUTION: This circuit is provided with multiplexers 1060-10631 for selecting and outputting one piece of bit data among the inputted four pieces of the bit data. In the multiplexers 1060-10615 of a first stage, digital data A are shifted by the shift width of one of 0 bit, 1 bit 2 bits and 3 bits. In the multiplexers 10616-10631 of a second stage, the digital data from the first stage are shifted by the shift width of one of 0 bit 4 bits, 8 bits and 12 bits and are outputted as the digital data B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a data shift circuit.

[0002]

2. Description of the Related Art In an arithmetic processing device such as a graphic arithmetic processing device, digital data having a predetermined bit width is left by a specified number of bits (MSB: Most Significant Bit).
A data shift circuit for shifting in the direction or the right (LSB: Least Significant Bit) is incorporated.
Hereinafter, a conventional data shift circuit will be described. First Conventional Example FIG. 8 is a configuration diagram of a conventional data shift circuit 10.
As shown in FIG. 8, the data shift circuit 10 includes eight multiplexer 8 input 1 output shown in FIG. 9 12 _{0-12 7}
And a three-input / eight-output decoder 14 shown in FIG. 10, and converts the 8-bit digital data A to the number of bits specified by the shift width designation data T in the range of the maximum shift width of 7 bits to the left ( (MSB) and output as digital data B.

In a data shift circuit 10, bit data T ₀ , T ₁ , and T _{2 of} shift width designation data T are supplied to a decoder 1.
4, decoded bit data o
_{0 to} o ₇ are s of the multiplexers 12 _{0 to} 12 ₇ , respectively.
Is output to ₀ ~s ₇ pin. The decoder 14 includes inverters 60 _{1 to} 60 ₃ and AND circuits 61 _{1 to} 61
₈ , and only one bit data among the output bit data o _{0 to} o ₇ is set to the logical value “1” according to the bit data S _{0 to} S ₂ . Then, the multiplexer 12 ₀
In 12 _7, is input to a _i terminal corresponding to the bit data o ₀ transistor 50 bit data o _i singular indicating the logical value "1" (0 ≦ i ≦ 7) is applied within the ~ O _{7 i} from bit data out terminals are respectively outputted as the bit data B ₀ ~B _7. In the data shift circuit 10, one-stage multiplexers 12 _{0 to} 12
₇ and high-speed processing is possible. In the data shift circuit 10 shown in FIG. 8, for example, when the digital data A has N bits, the N
Requires multiple multiplexers.

[0004] The second conventional example Figure 11 is a block diagram of a conventional other data shift circuit 20. As shown in FIG.
Is a two-input one-output multiplexer 22 ₀ shown in FIG.
And to 22 _23, consists decoder 24. 3 inputs 6 outputs,
Functionally, the data shift circuit 10 shown in FIG.
Is the same as As shown in FIG. 12, the data shift circuit 20 places the multiplexer 22 _{0-22 23} each with eight increments 1-3 th three stages, the first stage of multiplexers 22 ₀ to 22 ₇ in the bit data T
₀ left shifted by one bit or directly outputs the input data to output based on only as 2 bits or outputs the input data on the basis of the second multiplexer 22 _{8-22 15-bit} data T ₁ in the stage The output is shifted left and the third stage multiplexer 22 ₁₆
Left shifts directly outputs only 4 bits or outputs the input data on the basis of to 22 ₂₃ In-bit data T _2.

That is, in the data shift circuit 20, 1
By combining the shift amounts in the third to third stages, it is possible to shift the shift width from 0 to 7 bits. In the data shift circuit 20, for example, when the digital data A is shifted leftward by a shift width of 5 bits, the decoder 24
Bit data (T ₀ , T ₁ , T ₂ ) = ( ₁ , ₀ , ₁ )
Enter a, shifted by one bit input data based on the bit data T ₀ the multiplexer 22 _{0-22 7,} it outputs the input data on the basis of the bit data T ₁ the multiplexer 22 _{8-22 15,} a multiplexer 2
At 2 _{16 to} 22 ₂₃ , the input data is shifted left by 4 bits and output based on the bit data T ₂ . According to the data shift circuit 20, wiring can be performed regularly.

[0006]

By the way, the data shift circuit 10 shown in FIG. 8 can be realized with a small number of stages as described above and can perform high-speed processing. However, when the digital data A is N bits, (N-1) It is necessary to use a multiplexer with one input and one output, and when N becomes large, there is a problem that wiring becomes complicated. Therefore, the data shift circuit 10 is not suitable for a design that emphasizes regularity.

The data shift circuit 20 shown in FIG.
In this case, as described above, wiring can be performed regularly, but there is a problem that the number of stages of the multiplexer is large and the processing time is long. In particular, when the shift width of the digital data A increases, this problem becomes serious.

An object of the present invention is to provide a data shift circuit capable of performing high-speed processing with simple and regular wiring.

[0009]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art and achieve the above-mentioned object, a data shift circuit according to a first aspect of the present invention employs a data shift circuit in which S≤M-1. A data shift circuit capable of outputting input M-bit digital data with an arbitrary shift width of 0 to S bits, provided corresponding to each bit data of the digital data output from the preceding stage; The corresponding bit data output from the previous stage and one bit data obtained by shifting the bit data output from the previous stage by a predetermined shift width or a plurality of bit data obtained by shifting the bit data output from the previous stage by different shift widths from each other Input bit data and
A first stage including M pieces of first data selecting means for selecting one bit data from the input bit data and outputting the selected bit data to a subsequent stage; and a bit data of digital data output from the preceding stage. The corresponding bit data output from the previous stage and a plurality of bit data obtained by shifting the bit data output from the previous stage by different shift widths are input, and among the input bit data, A second stage including M second data selecting means for selecting one bit data and outputting the selected bit data to a subsequent stage, wherein a shift width in the first stage and a shift width in the second stage are provided. Digital data obtained by shifting the input digital data by a shift width corresponding to the sum of the first stage and the second stage.
Output from the later stage among the stages.

In a data shift circuit according to a second aspect of the present invention, when the logarithm of 2 of (S + 1) is an odd integer N and S ≦ M−1, the input M-bit digital A data shift circuit for shifting data by an arbitrary shift width of 0 to S bits and outputting the data. The data shift circuit is provided in correspondence with each bit data of digital data output from a previous stage, and includes two data input from the previous stage. And a first stage including M first data selecting means for selecting and outputting one bit data of the bit data of each of the bit data of the digital data output from the preceding stage. M (2 + 1) / 2- (M + 1) data selection means are provided correspondingly, each of which has M second data selection means for selecting and outputting one bit data from the four bit data input from the preceding stage.
1) second stages. Each of the M first data selecting means of the first stage is configured to shift the corresponding bit data output from the previous stage and the bit data output from the previous stage by a shift width of 1 bit.
, And one bit data is selected from the input two bit data and output to the subsequent stage. Each of the M second data selection means of the second stage satisfies 2 ≦ i ≦ (N + 1) / 2 in the ((N + 1) / 2−1) second stages. When a different integer i is assigned among all the integers i, the corresponding bit data output from the preceding stage and the bit data from the preceding stage are represented by 2 ^{2 (i−1)} according to the assigned integer i. ^-1 bit, 2 ^{2 (i−1) −1} · 2 bits and 3 ^{2 (i−1) −1} · 3 bits and three bit data respectively shifted by a shift width of Of the bit data, one corresponding to the specified shift width
This bit data is output to the subsequent stage.

[0011] In the data shift circuit according to the second aspect of the present invention, the input M-bit digital data is transmitted through one first stage and ((N + 1) / 2-1) second stages. The data is transmitted from the preceding stage to the succeeding stage while shifting in each stage in a predetermined order according to the designated shift width. At this time, a shift of an arbitrary shift width equal to or less than the maximum shift width S bits is realized by the sum of the shift widths in the first stage and the second stage.

In a data shift circuit according to a third aspect of the present invention, when the logarithm of 2 of (S + 1) is an even integer N and S ≦ M−1, the input M-bit digital A data shift circuit that shifts data by an arbitrary shift width of 0 to S bits and outputs the data. The data shift circuit is provided in correspondence with each of bit data of digital data output from a preceding stage, and inputs four bits. N / 2 stages each having M data selection means for selecting and outputting one bit data from the data.
Number of stages, all integers i satisfying 1 ≦ i ≦ N / 2
When each of the different integers i is assigned, each of the M data selection means of the stage, in accordance with the assigned integer i, outputs the corresponding bit data output from the preceding stage and the corresponding bit data from the preceding stage. Bit data 2
^{2 (i-1)} bits, 2 ^{2 (i-1)} · 2 bits and 2 ^{2 (i-1)} · 3
Three bit data shifted by the bit shift width are input, and one bit data corresponding to the specified shift width is output to the subsequent stage among the input four bit data.

[0013] In the data shift circuit according to the third aspect of the present invention, the input M-bit digital data shifts N / 2 stages in a predetermined order in each stage according to a designated shift width. Meanwhile, it is transmitted from the former stage to the latter stage. At this time, the shift of an arbitrary shift width equal to or less than the maximum shift width S bits is realized by the sum of the shift widths in the N / 2 stages.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a data shift circuit according to an embodiment of the present invention will be described. The data shift circuit according to the present embodiment converts M-bit digital data with a maximum shift width of S bits in the MSB (left) direction or LSB.
Shift to the right. First Embodiment In the present embodiment, a case will be described in which “log (S + 1)”, that is, the integer N is an odd number. In this case, as a data shift circuit, M 2-input 1-output multiplexers corresponding to the bit number M of the input digital data are arranged in parallel in the first stage, and 2-｛(log)
In the (S + 1) +1) / 2｝ -th stage, M 4-input / 1-output multiplexers each corresponding to the bit number M are used in parallel.

In the data shift circuit of this embodiment, the input digital data and the bit data obtained by shifting the input bit data by a shift width of 1 bit are input to the first stage multiplexer. One bit data is selected from the two bit data based on the shift width designation data from the decoder, and the selected bit data is output to the second stage. Next, 2 ≦ i ≦ ｛(log (S + 1)
+1) / 2}, the i-th stage multiplexer converts the bit data from the preceding stage and the bit data from the preceding stage into 2 ^{2 (i−1) −1} bits, 2 ^{2 (i−1) − 1} and 2
The bit and three bit data shifted respectively by the shift width of 2 ^{2 (i-1) −1} · 3 bits are input, and based on the shift width designation data among the input four bit data, One bit data is selected and output to the subsequent stage.

Hereinafter, a data shift circuit capable of left-shifting 8-bit digital data with a maximum shift width of 7 bits will be described. In this case, "log (7 + 1)"
3, the data shift circuit employs a configuration in which the above-mentioned “log (S + 1)” is an odd number. FIG. 1 is a configuration diagram of a data shift circuit 101 that can shift 8-bit digital data leftward with a maximum shift width of 7 bits. As shown in FIG.
1, TA ₀ to Ta ₇ terminals, TT ₀ ~TT ₂ terminal, two-input 4-output decoder 104, 2-input 1-output multiplexer 105 _{0-105 7,} 4-input 1-output multiplexer 106 _{0-106 7} and inverter with a 107 _0.

The TA _{0 to} TA ₇ terminals are provided with bit data A _{0 to} A _{7 of} 8-bit digital data A to be shifted.
Enter The TT _{0 to} TT ₂ terminals receive the bit data T _{0 to} T ₂ of the 3-bit shift width data T.

The multiplexers 105 _{0 to} 105 ₇ have the configuration shown in FIG. 12 described above. When the s ₀ terminal has a logical value of “1”, the transistor 32 ₀ is turned on, and the inverter 30 ₀ and the transistor 32 ₀ and via the inverter 30 _2, the level of in ₀ terminal is output to the out terminal. Here, the multiplexers 105 ₁ to 105 ₁
05 ₇ in ₀ terminal is connected to the terminal TA ₀ to Ta ₆ respectively one lower bit, when s ₀ pin has the logical value "1" (bit data T ₀ has the logical value "1" By the time), the multiplexer 105 _{1-105 7} of out
From the terminal, the bit data A from the terminals TA _{0 to} TA _6
0 ~A ₆ is output. The multiplexer 105 ₀
'S in ₀ terminal is grounded, when s ₀ pin has the logical value "1", the bit data outputted from the out terminal of the multiplexer 105 ₀ becomes a logic value "0". Thus, when s ₀ pin has the logical value "1", the digital data composed of bit data output from the out terminal of the multiplexer 105 _{0-105 7,} the digital data A toward only one bit MSB shift It will be.

On the other hand, multiplexers 105 _{0 to} 105 ₇
Means that when the s ₁ terminal has a logical value “1” (bit data T ₀
There when the logic value of "0"), the transistor 32 ₁ is conductive, inverter 30 _1, via the transistor 32 ₁ and the inverter 30 _2, the level of in ₁ terminal is output to the out terminal. Here, the multiplexer 10
5 ₀ ~105 ₇ in ₁ terminal of each terminal TA ₀ ~
Is connected to the TA _7, when s ₁ terminal has the logical value "1", digital data composed of bit data output from the out terminal of the multiplexer 105 _{0-105 7} is the same as the digital data A .

The multiplexers 105 _{0 to} 105 ₇
In, s ₀ bit data T ₀ to the terminal is applied for s ₀ bit data T ₀ ¯ obtained by inverting the bit data T ₀ to the terminal is applied, either of the transistors 32 ₀ and 32 ₁ shown in FIG. 12 Meanwhile Only the conduction state occurs.

As shown in FIG. 1, the decoder 104 includes inverters 107 ₁ and 107 ₂ and an AND circuit 108 _0.
Having to 108 _3. Decoder 104, as shown in FIG. 2, the bit data t ₀ ~t ₃ corresponding to the bit data T ₁ and T _2, and outputs the s ₀ ~s ₃ terminal of the multiplexer 106 _{0-106 7.} Bit data t _{0 to} t
_{As for 3} , only one of the bit data has the logical value “1”.

[0022] Multiplexer 106 _{0-106 7} has a structure shown in FIG. 3, when s ₀ pin has the logical value "1", transistor 132 ₀ is conductive, inverter 130 _0, transistor 132 ₀ and through an inverter 130 _4, the level of in ₀ terminal is output to each TB ₀ ~TB ₇ pin from out terminal. here,
In ₀ terminal of the multiplexer 106 ₆ and 106 _7, which is connected to the multiplexer 105 ₀ and 105 ₁ of out terminals of the six lower order, s ₀ when the terminal has the logical value "1" (bit data t ₀ is a logic When the value is “1”, the bit data from the out terminals of the multiplexers 105 ₀ and 105 ₁ are
6 output from the ₆ and 106 ₇ out terminal TB ₆ to the terminal and TB ₇ terminals. The multiplexer 106
_{0-106 5} in ₀ terminal is grounded, when s ₀ terminal is a logical value of "1", the multiplexer 106 ₀ ~
Bit data output to TB ₀ ～TB ₅ terminal from 106 ₅ out terminal becomes a logic value "0". Thus, digital data composed of bit data output from the out terminal of the multiplexer 106 _{0-106 7,} digital data consisting of bit data from the out terminal of the multiplexer 105 _{0-105 7} 6
The bit is shifted toward the MSB.

[0023] In addition, multiplexer 106 _{0-106 7}
In this case, when the s ₁ terminal has the logical value “1”, the transistor 132 ₁ is turned on, and via the inverter 130 ₁ , the transistor 132 _1, and the inverter 130 ₄ ,
The level of the in ₁ terminal is output to the out terminal. Here, in ₁ terminal of the multiplexer 106 _{4-106 7,} each of the four lower multiplexers 105 _{0 -} 10
5 ₃ is connected to the out terminal, when s ₁ terminal has the logical value of "1" (when the bit data t ₁ has the logical value "1"), the multiplexer 105 _{0-105 3} out
The bit data from the terminal is supplied to the multiplexer 106 ₄ to
Output is performed from the out terminal of 106 ₇ to the TB _{4 to} TB ₇ terminals, respectively. In addition, multiplexers 106 _{0 to} 106 ₀
In ₁ terminal of ₃ is grounded, when s ₁ terminal has the logical value "1", bit data logical value output from the out terminal of the multiplexer 106 _{0-106 3} "0"
become. Thus, the multiplexers 106 _{0 to} 106 _0
The digital data composed of the bit data output from the out terminal of the multiplexers 105 _{0 to} 105
Digital data composed of bit data from the ₇ out terminal is shifted by 4 bits toward the MSB.

[0024] In addition, multiplexer 106 _{0-106 7}
Then, when the s ₂ terminal has a logical value of “1”, the transistor 132 ₂ is turned on, and via the inverter 130 ₂ , the transistor 132 ₂ and the inverter 130 ₄ ,
level of in ₂ terminal is output to the out terminal. Here, in ₂ terminal of the multiplexer 106 _{2-106 7,} each of the two low-order multiplexers 105 _{0 -} 10
5 ₅ is connected to the out terminal, when s ₂ terminal has the logical value of "1" (when the bit data t ₂ has the logical value "1"), the multiplexer 105 _{0-105 5} out
The bit data from the terminal is output to the multiplexers 106 ₂ to 106 ₂ .
Output is performed from the out terminal of 106 ₇ to the TB _{2 to} TB ₇ terminals. The in ₂ terminals of the multiplexers 106 ₀ and 106 ₁ are grounded, and when the s ₂ terminal has a logical value “1”, the multiplexers 106 ₀ and 106 1
Bit data output from the ₁ out terminal has a logical value “0”. As a result, the multiplexers 106 _0-
Digital data composed of bit data output from the 106 ₇ out terminal, the multiplexer 105 ₀ ~
In bit data from 105 ₇ out terminal that is acquired by shifting toward only MSB 2 bits of digital data composed.

[0025] In addition, multiplexer 106 _{0-106 7}
So when s ₃ terminal has the logical value "1", transistor 132 ₃ becomes conductive, inverter 130 _3, through the transistor 132 ₃ and the inverter 130 _4,
in ₃ level of the terminal is output to the out terminal. Here, in ₃ terminal of the multiplexer 106 _{0-106 7} is connected to a multiplexer 105 _{0-105 7} terminals respectively, when s ₃ terminal has the logical value "1" (bit data t ₃ has the logical value "1 the "time), the bit data outputted from the out terminal of the multiplexer 106 _{0-106 7,} multiplexer 106 _{0-106 7} o
It is output from ut terminal to TB ₀ ~TB ₇ terminals. , Thereby, the digital data consisting of bit data output from the out terminal of the multiplexer 106 _{0-106 7} is the same as composed digital data in bit data output from the out terminal of the multiplexer 105 _{0-105 7} become.

Next, the data shift circuit 101 shown in FIG.
Will be described. FIG. 4 shows the data shift circuit 1
FIG. 11 is a diagram for explaining an example of the operation of No. 01. Here, the bit data (A ₀ ,
A ₁ , A ₂ , A ₃ , A ₄ , A ₅ , A ₆ , A ₇ ) = (1,
₀ , ₁ , ₁ , ₀ , ₁ , ₁ , 1) and bit data (T ₀ , T ₁ , T ₂ ) constituting shift width designation data T =
The operation when (1, 0, 1) is input to the data shift circuit 101 will be described. Note that the shift width designation data T (1, 0, 1) is "5" when represented in decimal, and the data shift circuit 101 shifts the digital data A left by 5 bits as shown below. I do.

[0027] That is, the bit data T ₀ indicating a logical value "1" is input to the s ₀ terminal of the multiplexer 105 _{0-105 7,} the level of in ₀ terminal is outputted from the out terminal. As a result, as shown in FIG. 4, the terminals TA out of the multiplexers 105 _{1 to} 105 ₇ are connected to the terminal TA.
_The bit data A _{0 to} A ₆ input to _{0 to} TA ₆ are output. Also, from the out terminal of the multiplexer 105 _0, is output logical value "0" is ground level.

In the decoder 104, the bit data (T ₁ , T ₂ ) = (0, 1) is decoded, and the bit data (t ₀ , t ₁ ,
_{t 2, t 3) = (} 0,1,0,0) is output to the multiplexer 106 _{0-106 7.} As a result, from the out terminal of the multiplexer 106 ₀ ~106 _7, in
The level of _one terminal is output. That, TB ₄ ~TB ₇ from out terminal of the multiplexer 106 _{4-106 7}
The terminals are connected to the outs of the multiplexers 105 _{0 to} 105 ₃ .
Bit data is output from the terminal. In addition, TB ₀ ~T from out terminal of the multiplexer 106 _{0-106 3}
The B ₃ terminal are output logic value "0" is ground level. Thereby, the bit data (B ₀ , B ₁ , B ₂ , B ₀₎ of the digital data B output from the TB _{0 to} TB ₇ terminals
B ₃ , B ₄ , B ₅ , B ₆ , B ₇ ) are (0, 0, 0,
0, 0, 1, 0, 1), which is the digital data A left-shifted by 5 bits.

As described above, the data shift circuit 101
According to the first stage, the bit data T
_{A 0-} bit or 1-bit left shift is performed according to 0, and a 2-bit, 4-bit or 6-bit left shift is performed in the second stage according to the bit data T ₁ and T ₂ . Therefore, by combining the shift in the first stage and the shift in the second stage, a shift of an arbitrary shift width of 0 to 7 bits can be realized as in the “total shift width” shown in FIG.

According to the data shift circuit 101,
Since the maximum number of input data of the multiplexer is 4, the number of input data of the multiplexer can be significantly reduced as compared with the data shift circuit 10 shown in FIG.
Wiring can be simplified. As a result, the data shift circuit 10
Configuration 1 is suitable for a design that emphasizes discipline. Also, according to the data shift circuit 101, the first and second
Because it is composed of the second two stages,
2, the number of stages can be reduced as compared with the data shift circuit 20 shown in FIG. As a result, the shift processing can be realized in a short time.

Second Embodiment In this embodiment, a case where "log (S + 1)" is an even number will be described. In this case, the data shift circuit
M 4 inputs 1 corresponding to the bit number M of digital data
A stage in which output multiplexers are arranged in parallel is defined as one stage, which has (log (S + 1)) / 2 stages. In the data shift circuit of the present embodiment, the M multiplexers in the i-th stage convert the bit data from the previous stage and the bit data from the previous stage into 2 ^{2 (i−1)} bits,
3 bit data shifted by ^{2 (i-1)} · 2 bit and 2 ^{2 (i−1)} · 3 bit shift width are input, and the shift width of the input 4 bit data is input. One bit data is selected based on the designated data and output to the subsequent stage. At this time, in the data shift circuit,
The digital data is 1 based on the shift width designation data.
The shift is performed by a shift width corresponding to the sum of the shift widths in the {｛(log (S + 1)) / 2} th stage.

A data shift circuit capable of shifting 16-bit digital data to the left with a maximum shift width of 15 bits will be described below. In this case, "log (15+
1) ”is 4, so that the data shift circuit
A configuration in which “log (S + 1)” described above is an even number is employed. FIG. 5 is a configuration diagram of a data shift circuit 201 that can shift 16-bit digital data leftward with a maximum shift width of 15 bits. As shown in FIG. 5, the data shift circuit 201 has a TA ₀ to Ta ₁₅ pins, T ₀ through T ₃ terminals, two-input 4-output decoder 104a, 104b and four-input one-output multiplexer 106 _{0-106 31} .

Terminals TA _{0 to} TA ₁₅ are connected to bit data A _{0 to} A of 16-bit digital data A to be shifted.
Enter ₁₅ . The TT _{0 to} TT ₃ terminals receive the bit data T _{0 to} T ₃ of the 4-bit shift width data T.

The decoders 104a and 104b correspond to FIG.
Has the same configuration as the decoder 104 shown in FIG. Decoder 104a, as shown in FIG. 6, the bit data t ₀ ~t ₃ corresponding to the bit data T ₀ and T _1, and outputs the s ₀ ~s ₃ terminal of the multiplexer 106 _{0-106 15.}
As for the bit data t _{0 to} t ₃ , only one of the bit data has a logical value “1”. Decoder 104b, as shown in FIG. 6, the bit data t ₄ ~t ₇ corresponding to the bit data T ₂ and T _3, the multiplexer 106 _16-10
And outputs the 6 ₃₁ s ₀ ~s ₃ terminal. Bit data t ₄ to
t _7, only any one of the bit data becomes the logical value "1".

[First Stage] In the first stage, the input digital data A is shifted to the left as it is or by a shift width of 1 bit, 2 bits or 3 bits. Output to the second stage.

The multiplexers 106 _{0 to} 106 ₁₅ have the configuration shown in FIG. 3. When the s ₀ terminal has a logical value of “1”, the transistor 132 ₀ is turned on, and the inverter 130 ₀ and the transistor 132 ₀ are turned on. and through an inverter 130 _4, the level of in ₀ terminal is outputted from the out terminal. Here, the multiplexers 106 ₃ to 10 ₃
6 ₁₅ in ₀ terminal of, three each lower TA ₀ ~TA
_When the s ₀ terminal is a logical value “1” (when the bit data t ₀ is a logical value “1”), T
Bit data A ₀ to A ₁₂ from A ₀ to Ta ₁₂ terminal is output from the out terminal of the multiplexer 106 _{3-106 15.} Also, i of the multiplexers 106 _{0 to} 106 ₂
The n ₀ terminal is at the ground level, and when the s ₀ terminal has the logical value “1”, the multiplexers 106 _{0 to} 106 ₂
The bit data output from the out terminal of becomes a logical value “0”. Accordingly, when the s ₀ terminal has the logical value “1”, the digital data composed of the bit data output from the out terminals of the multiplexers 106 _{0 to} 106 ₁₅ directs the digital data A by 3 bits toward the MSB. It will be shifted.

The multiplexers 106 _{0 to} 106 ₁₅
Means that when the s ₁ terminal has a logical value “1”, the transistor 1
32 ₁ is turned on, and through the inverter 130 ₁ , the transistor 132 ₁ and the inverter 130 ₄ , i
levels n ₁ terminal is outputted from the out terminal. Here, the in ₁ terminals of the multiplexers 106 _{2 to} 106 ₁₅ are respectively connected to two lower TA ₀ to TA ₁₃ terminals, and when the s ₁ terminal has a logical value “1” (the bit data t ₁ is a logical value “1”). the value in the time) of "1", the bit data a ₀ to a ₁₃ from TA ₀ to Ta ₁₃ terminal, the multiplexer 10
Output from 6 _{2-106 15} out terminal. Also, the in ₁ terminals of the multiplexers 106 ₀ and 106 ₁ are:
When the s ₁ terminal is at the logic level “1” at the ground level, the outs of the multiplexers 106 ₀ and 106 ₁ are out.
The bit data output from the terminal has a logical value “0”. Accordingly, when s ₁ terminal has the logical value "1", the digital data composed of bit data output from the out terminal of the multiplexer 106 _{0-106 15,} the digital data A toward only 2 bits MSB It will be shifted.

The multiplexers 106 _{0 to} 106 ₁₅
Means that when the s ₂ terminal has a logical value “1”, the transistor 1
32 ₂ is turned on, and through the inverter 130 ₂ , the transistor 132 ₂ and the inverter 130 ₄ , i
level n ₂ terminal is outputted from the out terminal. Here, the in ₂ terminals of the multiplexers 106 _{1 to} 106 ₁₅ are respectively connected to the lower TA ₀ to TA ₁₄ terminals, and when the s ₂ terminal has a logical value “1” (the bit data t ₂ is a logical value “1”). the value in the time) of "1", the bit data a ₀ to a ₁₄ from TA ₀ to Ta ₁₄ terminal, the multiplexer 10
Output from 6 _{1-106 15} out terminal. Moreover, in ₂ terminal of the multiplexer 106 ₀ is at the ground level, when s ₂ terminal has the logical value "1", bit data in the logic "0" output from the out terminal of the multiplexer 106 ₀ Become. Accordingly, when s ₂ terminal has the logical value "1", the multiplexer 106 _{0-106 15}
The digital data composed of the bit data output from the out terminal of the
It will be shifted towards SB.

The multiplexers 106 _{0 to} 106 ₁₅
So when s ₃ terminal has the logical value "1", transistor 132 ₃ becomes conductive, inverter 130 _3, through the transistor 132 ₃ and the inverter 130 _4,
in ₃ level of the terminal is output to the out terminal. Here, in ₃ terminal of the multiplexer 106 _{0-106 15} are respectively connected to the terminals TA ₀ to Ta _15, s
_{When the three} terminals have the logical value “1” (when the bit data t ₃ has the logical value “1”), the bit data A _{0 to} A ₁₅ are output from the out terminals of the multiplexers 106 _{0 to} 106 ₁₅ . , Thereby allowing the multiplexers 106 ₀ to 106 ₀ to
Digital data composed of bit data output from the 6 ₁₅ out terminal is the same as the digital data A.

[Second Stage] In the second stage, the digital data from the first stage is shifted to the left as it is or with a shift width of 4 bits, 8 bits or 12 bits. The shift result is output as digital data B.

The multiplexers 106 ₁₆ -106 _{31
When the 0} terminal has the logical value “1”, the transistor 132 ₀ shown in FIG. 3 is turned on, and the level of the in ₀ terminal is changed from the out terminal via the inverter 130 ₀ , the transistor 132 ₀ and the inverter 130 ₄ respectively. TB
It is output to _{0 ~TB 7} pin. Here, in ₀ terminal of the multiplexer 106 _{28-106 31} is connected to the out terminal of the lower of the multiplexer 106 _{0-106 3} only 12 respectively, when s ₀ pin has the logical value "1" (bit data t ₄ but when the logical value "1"), the bit data from the out terminal of the multiplexer 106 _{0-106 3} is output from the out terminal of the multiplexer 106 _{28-106 31} to TB ₁₂ ~TB ₁₅ terminal. Further, in ₀ terminal of the multiplexer 106 _{16-106 27} is at the ground level, when s ₀ pin has the logical value "1", TB from out terminal of the multiplexer 106 _{16-106 27
The} bit data output to the terminals _{0 to} TB ₁₁ have a logical value “0”. Thereby, the multiplexer 106
_{16-106 31} digital data B consists of bit data output from the out terminal of the multiplexer 10
Comprising a digital data consisting of bit data from 6 _{0-106 15} out terminal to those left shift toward the MSB by 12 bits.

The multiplexers 106 _{16 to} 106 ₃₁
In this case, when the s ₁ terminal has the logical value “1”, the transistor 132 ₁ is turned on, and via the inverter 130 ₁ , the transistor 132 _1, and the inverter 130 ₄ ,
The level of the in ₁ terminal is output to the out terminal. Here, in ₁ terminal of the multiplexer 106 _{24-106 31,} eight each subordinate multiplexer 106 _{0 -} 10
6 ₇ is connected to the out terminal of, when s ₁ terminal has the logical value "1" (when the bit data t ₅ has the logical value "1"), the multiplexer 106 _{0-106 7} out
The bit data from the terminal is supplied to the multiplexer 106 ₂₄
From each 106 ₃₁ out terminal is output to the TB ₈ ~TB ₁₅ terminal. Further, the multiplexers 106 _{16 to} 106 ₁₆
The in ₁ terminal of ₂₃ is grounded, and when the s ₅ terminal has a logical value “1”, the bit data output from the out terminals of the multiplexers 106 _{16 to} 106 ₂₃ has a logical value of “0”.
become. As a result, the multiplexers 106 _{16 to} 106
_The digital data B composed of bit data output from the out terminal of the multiplexer ₃₁ is supplied to the multiplexers 106 ₀ to 106 _0.
Made to those left shift toward a digital data consisting of bit data from 6 ₁₅ out terminal MSB only 8 bits.

The multiplexers 106 _{16 to} 106 ₃₁
Then, when the s ₂ terminal has a logical value of “1”, the transistor 132 ₂ is turned on, and via the inverter 130 ₂ , the transistor 132 ₂ and the inverter 130 ₄ ,
level of in ₂ terminal is output to the out terminal. Here, the in ₂ terminals of the multiplexers 106 _{20 to} 106 ₃₁ are respectively connected to four lower multiplexers 106 ₀ to 10 _0.
6 ₁₁ is connected to the out terminal of when s ₂ terminal has the logical value of "1" (when the bit data t ₆ has the logical value "1") is, out of the multiplexer 106 _{0-106 11}
Bit data from the terminal, the multiplexer 106 ₂₀ -
106 is output from ₃₁ out terminal TB ₄ ~TB ₁₅ terminal. Also, the multiplexers 106 _{16 to} 106 ₁₉ in
_{The two} terminals are grounded, and when the s ₂ terminal has a logical value “1”, the bit data output from the out terminals of the multiplexers 106 _{16 to} 106 ₁₉ has a logical value “0”.
Thereby, the ou of the multiplexers 106 _{16 to} 106 ₃₁
The digital data B composed of bit data output from the t terminal is supplied to the multiplexers 106 _{0 to} 106 ₁₅ at o.
Digital data composed of bit data from the ut terminal is shifted by 4 bits toward the MSB.

The multiplexers 106 _{16 to} 106 ₃₁
So when s ₃ terminal has the logical value "1", transistor 132 ₃ becomes conductive, inverter 130 _3, through the transistor 132 ₃ and the inverter 130 _4,
in ₃ level of the terminal is output to the out terminal. Here, the in ₃ terminals of the multiplexers 106 _{16 to} 106 ₃₁ are connected to the multiplexers 106 _{0 to} 106 ₁₅ , respectively, and when the s ₃ terminal has the logical value “1” (the bit data t ₇ has the logical value “1”). )), The bit data output from the out terminals of the multiplexers 106 _{0 to} 106 ₁₅ are converted to the o data of the multiplexers 106 _{16 to} 106 ₃₁ .
output from ut terminal TB ₀ ~TB ₁₅ pin. Thereby, the digital data B composed of the bit data output from the out terminals of the multiplexers 106 _{16 to} 106 ₃₁ is output from the multiplexers 106 _{0 to} 106 ₁₅ .
It is the same as digital data composed of bit data output from the terminal.

Next, the data shift circuit 201 shown in FIG.
Will be described. FIG. 7 shows the data shift circuit 2
FIG. 11 is a diagram for explaining an example of the operation of No. 01. Here, the bit data (A ₀ ,
_{A 1, A 2, A 3} , A 4, A 5, A 6, A 7, A 8, A
_{9, A 10, A 11,} A 12, A 13, A 14, A 15) = (1,
0,1,1,0,1,1,1,0,0,1,1,0,
0, 0, 0) and bit data (T ₀ , T ₁ , T ₂ , T ₃ ) constituting shift width designation data T = (1, 0, 0,
1) are input to the data shift circuit 201. When the shift width designation data T (1, 0, 0, 1) is displayed in decimal,
"9", and the data shift circuit 101 shifts the digital data A to the left by 9 bits as shown below.

That is, in the decoder 104a, the bit data (T ₀ , T ₁ ) = (1, 0) is decoded, and the bit data (t ₀ , t 0) as a result of the decoding is decoded.
₁ , t ₂ , t ₃ ) = ( _{0, 0} , ₁ , ₀ ) are output to the multiplexers 106 _{0 to} 106 ₁₅ . As a result, from the out terminals of the multiplexers 106 _{0 to} 106 ₁₅ ,
The level of the in ₂ terminal is output. That is, T out is supplied from the out terminal of the multiplexers 106 _{1 to} 106 ₁₅ to the in ₃ terminal of the multiplexers 106 ₁₇ to 106 ₃₁ , respectively.
Bit data A _{0 to} A ₁₅ are output from the A _{0 to} TA ₁₅ terminals. In addition, the in ₃ terminal of the multiplexer 106 ₁₇ out terminal of the multiplexer 106 _0, is output logical value "0" is ground level. That is, the digital data output from the out terminals of the multiplexers 106 _{0 to} 106 ₁₅ is obtained by shifting the digital data A left by one bit.

In the decoder 104b, the bit data (T ₂ , T ₃ ) = (0, 1) is decoded, and the bit data (t ₄ , t ₅ , t) as a result of the decoding is decoded.
₆ , t ₇ ) = (0, 1, 0, 0)
It is output to 06 _{16 to} 106 ₃₁ . As a result, from the out terminal of the multiplexer 106 ₂₄ ~106 _31, in ₁
The terminal level is output. That is, the TB ₈ ~TB ₁₅ pin from out terminal of the multiplexer 106 _{24-106 31} bit data from the out terminal of the multiplexer 106 _{0-106 7,} respectively, are outputted. In addition, TB signals are output from the out terminals of the multiplexers 106 _{16 to} 106 _23.
A logic value “0” that is a ground level is output to the _{0 to} TB ₇ terminals. That is, the digital data B output from the TB _{0 to} TB ₁₅ terminals is combined with the multiplexers 106 ₀ to 1.
The digital data output from the 06 ₁₅ out terminal 8
The result is shifted left by bits.

As described above, in the example shown in FIG. 7, the digital data A is shifted left by one bit in the first stage, shifted left by eight bits in the second stage,
Digital data B obtained by shifting digital data A to the left by 9 bits in total is output.

As described above, the data shift circuit 201
According to FIG. 6, by combining the shift in the first stage and the shift in the second stage,
As shown in “total shift width”, a shift of an arbitrary shift width of 0 to 15 bits can be realized.

According to the data shift circuit 201,
Since the maximum number of input data of the multiplexer is 4, the number of input data of the multiplexer can be greatly reduced as compared with the case where the data shift circuit 10 is configured by the same method as the above-mentioned first conventional example, and the number of wirings can be reduced. Easy to do. As a result, the configuration of the data shift circuit 201 is suitable for a design that emphasizes regularity. Further, the data shift circuit 20
According to No. 1, since it is composed of the first and second stages, the number of stages can be reduced as compared with the case where the data shift circuit is configured in the same manner as in the second conventional example. As a result, the shift processing can be realized in a short time.

The present invention is not limited to the embodiment described above. For example, in the above-described embodiment, the case where the input digital data is shifted leftward toward the MSB has been described as an example. However, according to the present invention, the input digital data is directed toward the LSB by reversing the shift direction in each stage. It can also be applied when shifting right. In the data shift circuit of the present invention, the order of each stage does not matter and can be arbitrarily changed. In the above-described embodiment, 8
The data shift circuit 101 that inputs digital data of bits and shifts it with a maximum shift width of 7 bits, and the data shift circuit 201 that inputs digital data of 16 bits and shifts it with a maximum shift width of 15 bits has been illustrated. A data shift circuit that inputs digital data of 8 bits and shifts the data with a maximum shift width of 6 bits or less;
The present invention is also applicable to a data shift circuit that inputs digital data of bits and shifts the data with a maximum shift width of 14 bits or less.

The present invention can also be applied to, for example, a case where 32-bit digital data is input and shifted with a maximum shift width of 31 bits. In this case, log (3
Since (1 + 1) = 5, the data shift circuit of the first embodiment is used.

[0053] Further, in the embodiment described above, the multiplexer 105 _{0-105 7} and multiplexers 106 ₀
As - 106 _31, as shown in FIG. 12 and FIG. 3, gate (base) is a logical value "1", i.e., a case has been exemplified using a transistor which becomes conductive when the high level, the gate (base) May be a transistor that is turned on when the logic value is “0”, that is, when it is at a low level.

[0054]

As described above, according to the data shift circuit of the present invention, the shift operation can be performed at high speed. Further, according to the data shift circuit of the present invention, wiring can be performed simply and regularly, and circuit design becomes easy.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data shift circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining processing in a decoder shown in FIG. 1;

FIG. 3 is a configuration diagram of a 4-input / 1-output multiplexer shown in FIG. 1;

FIG. 4 is a diagram for explaining an operation of the data shift circuit shown in FIG. 1;

FIG. 5 is a configuration diagram of a data shift circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram for explaining processing in the decoder shown in FIG. 5;

FIG. 7 is a diagram for explaining an operation of the data shift circuit shown in FIG. 1;

FIG. 8 is a configuration diagram of a conventional data shift circuit.

FIG. 9 is a configuration diagram of a general eight multiplexer having seven inputs and one output.

FIG. 10 is a configuration diagram of a general three-input eight-output decoder.

FIG. 11 is a configuration diagram of another conventional data shift circuit.

FIG. 12 is a configuration diagram of a general two-input one-output multiplexer.

[Explanation of symbols]

101, 102... Data shift circuit, 104, 104
a, 104b... decoder, 105 _{0 to} 105 ₇ , 106
_{0 to} 106 ₁₆ : multiplexer, TA _{0 to} TA ₁₅ : input terminal of digital data A, TB _{0 to} TB ₁₅ : output terminal of digital data B

Claims (12)

[Claims] When S≤M-1, a data shift circuit capable of outputting input M-bit digital data with an arbitrary shift width of 0 to S bits is provided. Corresponding bit data provided from the preceding stage provided for each of the bit data, and one bit data obtained by shifting the bit data outputted from the preceding stage by a predetermined shift width or bit data outputted from the preceding stage And a plurality of bit data shifted by different shift widths from each other, M bit data selecting means for selecting one bit data from the input bit data and outputting the selected bit data to a subsequent stage. A first stage, and corresponding bit data output from the previous stage, provided corresponding to each bit data of the digital data output from the previous stage. , A plurality of bit data obtained by shifting the bit data output from the preceding stage with mutually different shift widths, and selecting one bit data from the input bit data to output to the subsequent stage. A second stage provided with a second data selecting means, wherein the input digital data is shifted by a shift width corresponding to a sum of a shift width in the first stage and a shift width in the second stage. A data shift circuit that outputs the converted digital data from a later stage of the first stage and the second stage. 2. The first data selecting means and the second data selecting means.
2. The data shift circuit according to claim 1, wherein the data selection means selects the bit data based on the shift width designation data. 3. When the logarithmic value of 2 of (S + 1) is an odd integer N and S ≦ M-1, the input M-bit digital data is shifted by an arbitrary shift width of 0 to S bits. In the data shift circuit for shifting and outputting, one bit data is provided corresponding to each of the bit data of the digital data output from the preceding stage, and one of the two bit data input from the preceding stage is selected and output. M
One first stage provided with a plurality of first data selection means, and one of the four bit data input from the preceding stage provided corresponding to each bit data of the digital data outputted from the preceding stage. M for selecting and outputting one bit data
(N + 1)
/ 2-1) second stages, wherein each of the M first data selecting means of the first stage has a corresponding bit data output from the previous stage and an output from the previous stage. One bit data obtained by shifting the selected bit data by a shift width of one bit, selecting one bit data from the input two bit data and outputting the selected bit data to a subsequent stage; Each of the M second data selection means of the (a) stage includes all the integers satisfying 2 ≦ i ≦ (N + 1) / 2 in the ((N + 1) / 2−1) second stages. When different integers i among i are assigned,
According to the assigned integer i, the corresponding bit data output from the preceding stage and the bit data from the preceding stage are 2 ^{2 (i−1) −1} bits, 2 ^{2 (i−1) −1} · 2 bits And 2
^{2 (i-1) -1} · Three bit data shifted by 3 bit shift width are input, and one of the input four bit data corresponding to the designated shift width is input. A data shift circuit that outputs bit data to the subsequent stage. 4. The first stage is provided first from the input side of the digital data, and the second data selection means of the i-th second stage is configured to perform the first stage in accordance with the assigned integer i. The corresponding bit data output from the preceding stage and the bit data from the preceding stage are divided into 2 ^{2 (i−1) −1} bits, 2 ^{2 (i−1) −1} · 2 bits and 2 bits.
^{2 (i-1) -1} · Three bit data shifted by 3 bit shift width are input, and one of the input four bit data corresponding to the designated shift width is input. 4. The data shift circuit according to claim 3, wherein the bit data is output to a subsequent stage. 5. The first data selection means and the second data selection means.
4. The data shift circuit according to claim 3, wherein the data selection means specifies the shift width based on shift width specification data. 6. A 2-bit second shift width data which decodes the first shift width designation data and outputs the decoded data to the first data selection means, and outputs the second shift width data to the second data selection means for each stage. A decoder for generating 4-bit third shift width designation data to be output, wherein the first data selection means designates the shift width based on the second shift width designation data; 6. The data shift circuit according to claim 5, wherein said second data selection means designates said shift width based on said third shift width designation data of a corresponding stage. 7. The data selection means according to claim 3, wherein said bit selection means outputs a predetermined logical value when bit data corresponding to said specified shift width does not exist in digital data from a preceding stage. Data shift circuit. 8. When the logarithmic value of 2 of (S + 1) is an even integer N and S ≦ M−1, input M-bit digital data is shifted by an arbitrary shift width of 0 to S bits. In a data shift circuit for shifting and outputting data, M is provided corresponding to each bit data of the digital data output from the preceding stage, and selects and outputs one bit data from the input four bit data. N / 2 stages each provided with a plurality of data selection means, and each of the N / 2 stages has a different integer i among all integers i satisfying 1 ≦ i ≦ N / 2 At the time of assignment, each of the M data selection means of the stage, according to the assigned integer i, assigns the corresponding bit data output from the preceding stage and the bit data from the preceding stage to two.
^{2 (i-1)} bits, 2 ^{2 (i-1)} · 2 bits and 2 ^{2 (i-1)} · 3
A data shift circuit which receives three bit data shifted by the bit shift width and outputs one bit data corresponding to the designated shift width to the subsequent stage among the input four bit data. . 9. The data selection means of the i-th stage from the input side of the digital data, according to the assigned integer i, converts the corresponding bit data output from the previous stage and the bit data from the previous stage into 2 ^{2 (i-1)} bits, 2
^{2 (i-1)} · 2 bits and 3 ^{2 (i-1)} · 3 bits, each of which is shifted by a shift width of 3 bits, are input, and out of the input 4 bit data, 9. The data shift circuit according to claim 8, wherein one bit data corresponding to the shifted width is output to a subsequent stage. 10. The data shift circuit according to claim 8, wherein said data selection means designates said shift width based on shift width designation data. 11. A decoder for decoding first shift width designating data to generate 4-bit second shift width designating data for each stage, wherein said data selecting means comprises: The data shift circuit according to claim 10, wherein the shift width is specified based on the second shift width specification data. 12. The data selection means according to claim 8, wherein said bit selection means outputs a predetermined logical value when bit data corresponding to said specified shift width does not exist in digital data from a preceding stage. Data shift circuit.