JP2000029579A - Bus hold circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a current which flows at the time of voltage variation of a bus to the minimum by allowing an output circuit to output a power source voltage when the output of a level detecting circuit is in a power source voltage area, generate a high impedance when it is in an intermediate voltage area, and output a ground voltage when it is in a ground voltage area. SOLUTION: The level detecting circuit 112 sections the voltage of a bus 3 into three levels from the power source voltage to the ground level to set the source voltage area, the intermediate voltage area, and the ground voltage area in order from the power source voltage side, and outputs their results. The output circuit 113 outputs the power source voltage when the output of the level detecting circuit 112 is in the power source voltage area. The output circuit 113 generates the high impedance when the output of the level detecting circuit 112 is in the intermediate voltage area. Further, the output circuit 113 outputs the ground voltage when the output of the level detecting circuit 112 is in the ground voltage area. Consequently, the current can be minimized in case of voltage variation of the bus 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to a semiconductor circuit technology circuit, and relates to a configuration of a bus hold circuit.

[0002]

2. Description of the Related Art A conventional bus hold circuit is disclosed in
The circuit configuration shown in Japanese Patent No. 127618 was adopted.
This circuit is shown in FIG.

[0003] 1 is a power supply, and 0 is a ground. 1010
1012 are a tri-state buffer and 1013 is an inverter. 1004 to 1006 are input terminals of the respective tri-state buffers, 1007 to 100
9 is a control terminal of each tristate buffer, 1
050 is a bus. 1014 and 1015 are P-channel transistors, 1016 and 1017 are N-channel transistors.

[0004] Tristate buffers 1010, 101
Outputs 1 and 1012 are connected to a bus 1050, and one of them is active and the others are in a high impedance state. This one active tri-state buffer determines the state of bus 1050. At the same time, P-channel transistors 1014 and 1015 and N-channel transistor 1
The state of the bus is also latched by the latch circuit composed of 016 and 1017. If all the tri-state buffers are in the high impedance state, the state of the bus is held by this latch circuit.

[0005]

When a bus hold circuit is to be constructed with the above-described configuration, the tristate buffer and the latch output momentarily collide. When attempting to invert the state in which the bus is latched, the tri-state buffer collides with the output of the inverter formed by the P-channel transistor 1014 and the N-channel transistor 1016, and then the state of the latch is inverted. Therefore, at this moment, a large amount of current flows.

FIG. 11 shows this state. Horizontal axis 1 of (A)
101 represents time. The vertical axis 1102 represents the voltage of the bus 1050. When a waveform having such a slope is input, the output 1051 of the inverter including the P-channel transistor 1015 and the N-channel transistor 1017 can be represented by (B) in FIG. The vertical axis 1103 indicates the voltage of the node 1051. An inverter formed of a P-channel transistor 1014 and an N-channel transistor 1016 that receives this voltage outputs the inverted voltage, so that it will collide with the input waveform 1110. Therefore, the P-channel transistor 1014 or the N-channel transistor 1016 Current will flow. This current is shown in FIG. The vertical axis 1104 indicates a current value. The current corresponding to the hatched area of (C) flows and becomes the current consumption.

This current has caused an increase in the current consumption of the system. In order to reduce this current, P
Although it is conceivable to reduce the current driving capability of the channel transistor 1014 and the N-channel transistor 1016, reducing the current driving capability causes a decrease in the bus holding capability.

[0008]

(1) In a bus connecting a plurality of tri-state buffers and an input circuit, a level detection circuit which receives the bus, detects a voltage of the bus, and outputs a detection result, An output circuit that receives an output of the level detection circuit as an input and outputs a voltage to a bus in accordance with the output of the level detection circuit, wherein the level detection circuit converts the voltage of the bus from a power supply voltage to ground. Are divided into three levels, and the results are output as a power supply voltage area, an intermediate voltage area, and a ground voltage area in order from the power supply voltage side. The output circuit outputs a signal when the output of the level detection circuit is the power supply voltage area. The output circuit outputs a power supply voltage, the output circuit becomes high impedance when the output of the level detection circuit is in the intermediate voltage range, and the output circuit outputs And outputs the ground voltage when output of the detection circuit of the ground voltage region.

(2) The level detection circuit according to (1) is composed of a first inverter having an inverted output voltage close to the power supply voltage and a second inverter having an inverted output voltage close to the ground voltage. The described output circuit connects a source to a power supply, connects a gate to the output of the first inverter,
A P-channel transistor having a drain connected to the bus, an N-channel transistor having a source connected to the ground, a gate connected to the output of the second inverter, and a drain connected to the bus. I do.

(3) In a bus connecting a plurality of tri-state buffers and input circuits, an inverter having the bus as an input, a tri-state inverter having an output of the inverter as an input, and having the bus as an output, And a level detection circuit that outputs a detection result to a control terminal of the tri-state inverter, wherein the level detection circuit is configured such that a voltage of the bus is between a ground voltage and a power supply voltage. When the voltage range is reached, the tri-state inverter is set to high impedance.

(4) The level detection circuit according to (3), wherein the first inverter whose output inversion voltage is close to the power supply voltage, the second inverter whose output inversion voltage is close to the ground voltage, and the first inverter. It is characterized by comprising a circuit for outputting an inverted signal of an exclusive OR having an output and an output of the second inverter as inputs.

(5) In a bus connecting a plurality of tri-state buffers and input circuits, a level detection circuit which receives the bus as an input, detects a voltage of the bus, and inverts and outputs a detection result, and the level detection circuit And an output circuit for outputting a voltage to the bus in response to the input, wherein the level detection circuit has a first circuit in which the bus voltage transitions from the ground voltage to the power supply voltage and the output is inverted. In the voltage and the second voltage at which the output is inverted by transition from the power supply voltage to the ground voltage, the inverted voltage has different hysteresis characteristics, and the second voltage is larger than the first voltage. I do.

(6) The level detection circuit according to (5), wherein the first inverter whose output inversion voltage is close to the ground voltage;
A second inverter whose output inversion voltage is close to the power supply voltage, a first differentiation circuit that receives an output of the first inverter as an input, and outputs a differential pulse with a falling waveform of the first inverter output, An output of the second inverter is an input, a second differentiating circuit that outputs a differential pulse with a rising waveform of the output of the second inverter, and an output of the first differentiating circuit is connected to a set input, and the second input is connected to the second input. The output of the differentiating circuit is constituted by an RS latch connected to the reset input, and the output circuit described in (5) is constituted by an inverter.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described according to specific embodiments of the present invention.

FIG. 1 shows an example of the configuration of a bus hold circuit according to the present invention. Reference numeral 3 denotes a bus, 1 is a power supply, and 0 is a ground. 110 is a P-channel transistor, and 111 is an N-channel transistor. An inverter 113 includes a P-channel transistor and 111 N-channel transistors. 112 is a level detection circuit. The level detection circuit 112 outputs an inverted signal of the input bus 3. Therefore, a latch circuit is formed by the inverter 113 and the repel detection circuit 112.

FIG. 2 is a detailed circuit diagram of the level detection circuit 112. 201 is an input terminal connected to the bus 3. 20
2 and 203 are P-channel transistors 11 respectively.
0, an output terminal connected to the gate of the N-channel transistor 111. 210 and 212 are P-channel transistors. 211 and 213 are N-channel transistors. An inverter is constituted by the P-channel transistor 210 and the N-channel transistor 211. Similarly, an inverter is configured by P-channel transistor 212 and N-channel transistor 213.

The inverted voltage of the inverter connected to the output terminal 202 is larger than 1/2 of the power supply voltage,
03 is the power supply voltage of 1
/ 2.

FIG. 3 shows these relationships. (A) is FIG.
5 shows a waveform of the bus 3 at the time of the second embodiment. 301 is a time axis,
302 is a voltage axis. Numeral 310 indicates the waveform of the bus 3.
Reference numerals 350 and 351 represent inverted voltages of the level detection circuit 112. 350 is an inverted voltage of the inverter constituted by the P-channel transistor 210 and the N-channel transistor 211. Similarly, reference numeral 351 denotes an inverted voltage of an inverter composed of a P-channel transistor 212 and an N-channel transistor 213. (B) shows the output waveform of the inverter 113. 303 is a voltage axis, 3
13, 314, and 312 are output waveforms of the inverter 113. 314 indicates a high impedance state. (C) is a waveform of a current flowing in the inverter constituted by the P-channel transistor 110 and the N-channel transistor 111. 304 is a current axis. 316
Is a current waveform that flows through the inverter when outputs are short-circuited, and the area indicated by hatching corresponds to the current value.

When the bus voltage is equal to or lower than the inversion voltage 351 of the level detection circuit, the bus 3 has a ground voltage 313.
Is output. Similarly, the inversion voltage 350 of the level detection circuit
If the bus voltage is higher than the above, the power supply voltage 31
2 is output. At the intermediate voltage, the P-channel transistor 110 and the N-channel transistor 1
11 are both in a non-conducting state and are in a high impedance state. The output voltage of the inverter 113 and the bus 3
The short-circuit current (C) flows from the difference from the output voltage of FIG. Here, the dotted line 31
Reference numeral 8 denotes a current flowing in the configuration of the conventional bus hold circuit. As is apparent here, the short-circuit time between the inverter and the bus 3 is considerably reduced by the conventional circuit configuration. Therefore, it is possible to reduce the current flowing in switching the bus 3 which cannot be avoided in the bus hold circuit having the latch structure.

FIG. 4 shows another example of the configuration of the bus hold circuit of the present invention. 3 indicates a bus, and 410 and 411 are inverters. Here, reference numeral 411 denotes a tri-state output inverter. Inverters 410 and 411 form a latch. 412 is a level detection circuit. The level detection circuit 412 detects the voltage of the bus 3 which is an input, and outputs a signal which is normal with respect to the input voltage. This output controls the output of the tri-state output inverter 411.

FIG. 5 is a detailed circuit diagram of the level detection circuit 412. Reference numeral 501 denotes an input terminal connected to the bus 3;
3 is an output terminal. Inverters 510 and 511 have different inversion voltages. An exclusive NOR 512 includes inverters 510 and 511.
The power supply voltage is output when the output signals match.

The inverted voltage of inverter 510 is larger than 1/2 of the power supply voltage, and the inverted voltage of inverter 511 is smaller than 1/2 of the power supply voltage.

FIG. 6 shows these relationships. (A) is FIG.
5 shows an input waveform of the inverter 410 in FIG. 601 is a time axis, and 602 is a voltage axis. 610 is bus 3
3 shows a voltage waveform of the voltage. 650 and 651 are level detection circuits 4
12 represents the inversion voltage of each of the inverters.
(B) shows the output waveform of the inverter 411. Reference numeral 603 denotes a voltage axis, and each of 613, 614, and 612 represents an output voltage waveform of the inverter 411. (C) is a waveform of the current flowing when the output is short-circuited to the inverter 411. 604 is a current axis. Reference numerals 616 and 617 denote current waveforms in which the output is short-circuited to the inverter 411 and flows.
The area indicated by hatching corresponds to the current value.

When the bus voltage is equal to or lower than the inversion voltage 651 of the level detection circuit, the bus 3 has a ground voltage 613.
Is output. Similarly, the inversion voltage 350 of the level detection circuit
When the bus voltage is higher than the above, the power supply voltage 61 is applied to the bus 3.
2 is output. At the intermediate voltage, the output of the level determination circuit is input to the control terminal of the inverter 411, so that the output of the inverter is in a high impedance state. The output short-circuit current (C) flows from the difference between the output voltage of the inverter and the output voltage of the bus 3, and the area becomes the hatched area. Here, a dotted line 618 indicates a current flowing in the configuration of the conventional bus hold circuit. As is apparent here, the short circuit time between the inverter 411 and the bus 3 is considerably reduced by this circuit configuration. Therefore, it is possible to reduce the current flowing in switching the bus 3 which cannot be avoided in the bus hold circuit having the latch structure.

FIG. 7 shows another example of the configuration of the bus hold circuit of the present invention. 3 indicates a bus, 710 indicates a P-channel transistor, and 711 indicates an N-channel transistor. Reference numeral 713 denotes an inverter composed of a P-channel transistor 710 and an N-channel transistor 711. 712 is a level detection circuit. The level detection circuit 712 detects the voltage of the bus 3, which is an input, and outputs a signal obtained by inverting the input voltage. The level detection circuit 712 and the inverter 713 constitute a latch.

FIG. 8 is a detailed circuit diagram of the level detection circuit 712. 801 is an input terminal connected to the bus 3;
3 is an output terminal. Inverters 810 and 811 have different inversion voltages. 814, 815
Is a delay circuit, which has a certain delay with respect to the signal output from the inverter 810 or 811 and has a node 855
Alternatively, the signal is output to the node 857. 815 and 816 are ANDs each having a negative input. 812 and 813 are NOR
And has a configuration of an RS latch.

The inverted voltage of inverter 810 is smaller than 1/2 of the power supply voltage, and the inverted voltage of inverter 811 is larger than 1/2 of the power supply voltage.

FIG. 9 shows these relationships. (A) is FIG.
5 shows an input waveform of the level detection circuit 712 at the time of FIG. 90
1 is a time axis, and 902 is a voltage axis. 910 indicates a voltage waveform of the bus 3. Reference numerals 950 and 951 represent inverted voltages of the respective inverters of the level detection circuit 712.
(B) shows voltage waveforms at nodes 850 and 851. 92
1 is the waveform of the node 850, and 922 is the waveform of the node 851. This pulse width corresponds to the delay value of the delay circuits 814 and 815. The difference between the inverted voltages of the inverters 810 and 811 appears as the difference in the time of the output waveform. (C) shows the output waveform of the inverter 713. Reference numeral 904 denotes a voltage axis, and reference numerals 913 and 914 denote output voltage waveforms of the inverter 713, respectively. (D) is a waveform of an output short-circuit current flowing through the inverter 713. 905 is a current axis. Reference numerals 916 and 917 denote output short-circuit current flows through the inverter 713, and the area indicated by hatching corresponds to the current value.

When the voltage of the bus 3 rises from the ground to the power supply voltage, a pulse is output by the inversion voltage of the inverter 810, the delay circuit 814, and the AND 815.
The RS latch constituted by R812 and R813 is hit, and the output of the inverter 713 is changed from the ground to the power supply voltage. Therefore, the difference between the output voltage of the bus 3 and the output voltage of the inverter 713 is the time required for the bus 3 to reach the inverted voltage 951 of the inverter 713. The current flowing during this time is the consumed current. Reference numeral 918 indicated by a dotted line indicates a current value flowing in the conventional bus hold circuit, and it can be seen from this comparison that the current value is smaller than that of the conventional bus hold circuit. The same operation is performed when the voltage of the bus 3 drops from the power supply voltage to the ground.

This shows one embodiment of the present invention, and other developments are conceivable.

[0031]

In the conventional bus hold circuit, when the state of the bus changes, a short circuit occurs between the output signals and a current flows, which leads to an increase in current consumption. In particular, the bus hold circuit is provided in order to avoid pull-up and pull-down in which current may always flow, and to prevent the CMOS input from floating and leak current from flowing in advance. Therefore, it is necessary to reduce the flow of useless current consumption as much as possible. According to the present invention, the current flowing when the bus changes can be minimized. In particular, when all the output buffers connected to the bus are in a high impedance state and the bus is surely suppressed to either one, the current driving capability of the inverter that outputs to the bus must be increased. This has led to an increase in current consumption. Even in such a state where the current driving capability is increased,
According to the present invention, an increase in current consumption can be prevented.

Further, in the invention having the configuration shown in FIG. 1, the circuit scale can be realized by adding one inverter, and the influence on the chip area and the unit cost of the chip is very large as compared with the conventional circuit configuration. Less. This is a configuration that can be easily added to a conventional circuit.

In the configuration shown in FIG. 2, when an input inverter is provided in a circuit connected to the bus, the inverter can be used also as the inverter 410. Therefore, it is possible to reduce the number of circuit elements, and when the bus hold circuit is not used, it is easy to disable the connection by connecting the node 451 to the ground. It is also possible to easily control with a signal from another.

In the configuration shown in FIG. 7, even when the bus is at the intermediate potential, the potential of the bus hold circuit is either, so that the number of floating states is reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a bus hold circuit of the present invention.

FIG. 2 is a partially detailed diagram of the bus hold circuit of FIG. 1;

FIG. 3 is a voltage and current waveform diagram of the bus hold circuit of FIG. 1;

FIG. 4 is a diagram of another configuration example of the bus hold circuit of the present invention.

FIG. 5 is a partial detailed diagram of the bus hold circuit of FIG. 4;

FIG. 6 is a diagram showing voltage and current waveforms of the bus hold circuit of FIG. 4;

FIG. 7 is a diagram showing another configuration example of the bus hold circuit of the present invention.

FIG. 8 is a partial detailed diagram of the bus hold circuit of FIG. 7;

FIG. 9 is a voltage and current waveform diagram of the bus hold circuit of FIG. 7;

FIG. 10 is a configuration diagram of a conventional bus hold circuit.

11 is a voltage and current waveform diagram of the bus hold circuit of FIG.

[Explanation of symbols]

0 Ground 1 Power supply 112 Level detection circuit 110, 210, 212 P-channel transistor 111, 211, 213 N-channel transistor 310 Voltage waveform of bus 3 313, 314, 312 Output voltage waveform of inverter 316, 317 Inverter current value 410, 411 Inverter 412 Level detection circuit 510, 511 Inverter 512 Exclusive NOR 610 Voltage waveform of bus 3 613, 614, 612 Output voltage waveform of inverter 616, 617 Inverter current value 710 P-channel transistor 711 N-channel transistor 712 Level detection circuit 810 , 811 Inverter 814, 815 Delay circuit 815, 816 AND 812, 813 NOR 610 Voltage waveform of bus 3 912, 902 Node 8 0, the current value of the output voltage waveform 916, 917 inverter 713 voltage waveforms 913 and 914 the inverter 713 of the node 851

Claims (6)

[Claims] 1. A level detection circuit for receiving a signal from a bus connected to a plurality of tristate buffers and an input circuit, detecting a voltage of the bus, and outputting a detection result, and an output of the level detection circuit. And an output circuit that outputs a voltage to a bus according to the output of the level detection circuit, wherein the level detection circuit divides the voltage of the bus from a power supply voltage to a ground into three levels, Power supply voltage region, intermediate voltage region,
The result is output as a ground voltage region, the output circuit outputs a power supply voltage when the output of the level detection circuit is the power supply voltage region, and the output circuit outputs the intermediate voltage when the output of the level detection circuit is the intermediate voltage. The bus hold circuit according to claim 1, wherein the impedance becomes high impedance in a voltage region, and the output circuit outputs a ground voltage when an output of the level detection circuit is in the ground voltage region. 2. The level detection circuit according to claim 1, further comprising a first inverter whose output inversion voltage is close to the power supply voltage, and a second inverter whose output inversion voltage is close to the ground voltage. An output circuit has a source connected to a power supply, a gate connected to the output of the first inverter, a drain connected to the bus, a P-channel transistor connected to the bus, a source connected to ground, and a gate connected to the second inverter. A bus hold circuit comprising an N-channel transistor connected to an output of an inverter and having a drain connected to the bus. 3. A bus connecting a plurality of tri-state buffers and an input circuit, wherein: an inverter having the bus as an input; a tri-state inverter having an output of the inverter as an input and having the bus as an output; A level detection circuit for detecting a voltage and outputting a detection result to a control terminal of the tri-state inverter, wherein the level detection circuit is configured to output a fixed voltage at which a voltage of the bus is between a ground voltage and a power supply voltage. A bus hold circuit wherein the tri-state inverter has a high impedance in a range. 4. The level detection circuit according to claim 3, wherein the first inverter has an output inversion voltage near the power supply voltage, the second inverter has an output inversion voltage near the ground voltage, and an output of the first inverter. And a circuit that outputs an inverted signal of an exclusive OR that receives an output of the second inverter as an input. 5. A level detection circuit comprising: a bus connecting a plurality of tri-state buffers and an input circuit, the level detection circuit receiving the bus as an input, detecting a voltage of the bus, and inverting and outputting a detection result; Take output as input,
An output circuit that outputs a voltage to the bus in response to the input, the level detection circuit comprising: a first voltage at which a bus voltage transitions from a ground voltage to a power supply voltage and the output is inverted; A bus hold circuit, wherein a second voltage at which an output is inverted by transition to a ground voltage has different hysteresis characteristics, and the second voltage is larger than the first voltage. 6. The level detection circuit according to claim 5, wherein the first inverter has an output inversion voltage near the ground voltage, the second inverter has an output inversion voltage near the power supply voltage, and an output of the first inverter. As an input, a first differentiating circuit that outputs a differential pulse with a falling waveform of the first inverter output, and an input of the output of the second inverter,
A second differentiating circuit that outputs a differentiated pulse with a rising waveform of the second inverter output, an output of the first differentiating circuit is connected to a set input, and an output of the second differentiating circuit is connected to a reset input. 6. The bus hold circuit according to claim 5, wherein said output circuit comprises an inverter.