JP2000022518A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To convert a level at high speed by converting signals on a low voltage side to the signals on a high voltage side by a first gate means and latching the converted signals by a latch circuit operated by control signals from the timing switch circuit of a high voltage side circuit further. SOLUTION: In a circuit for transmitting the signals on the low voltage side to the circuit on the high voltage side, the gate means 6 on the high voltage side provided with the control signals from the timing switch circuit 10 on the high voltage side is provided, and by activating the gate means 6, the signals on the low voltage side are passed through the gate means and converted to the signals on the high voltage side at high speed. Further, the converted signals are latched by the latch circuit operated by the control signals from the timing switch circuit 10 of the circuit on the high voltage side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device having a MOS structure.

[0002]

2. Description of the Related Art In a conventional MOS integrated circuit device (hereinafter referred to as IC), a circuit for transmitting a first signal on a first low voltage side to a circuit on a second high voltage side. The main circuit used is shown in FIG. The operation of this circuit is as follows.

The circuit on the low voltage side is the inverter means 302 and the signal 303, and the circuit on the high voltage side is other than the signal 303 and the element 302. The operation will be described with an example in which the signal 303 changes from a low level to a high level.

(1) Since the signal 311 is at a low level, the P-type transistor 308 is turned on and the N-type transistor 3
09 turns off. Further, the N-type transistor 306 is turned on and the signal 313 is at a low level, so that the P-type transistor 307 is turned on.

(2) In this state, a high level on the high voltage side is output as the signal 312. Further, the P-type transistor 307 and the P-type transistor 308 are turned on, and the N-type transistor 309 is turned off, so that the signal 312 is at a high level. As a result, the P-type transistor 304 is turned off.

(3) According to (1) and (2), a current flows from the high-voltage side power supply terminal 301 to the ground during a transition period, but becomes a static state after the signal 310 is determined, so that a short-circuit current flows. Absent.

[0007]

However, the conventional method as described above has the following disadvantages.

(1) Many transistors are interposed between the time when the signal 303 changes and the time when the level-converted signal 310 is output, and the level conversion takes time. In addition, since the driving capability of the signal 312 itself becomes low in configuration, it is actually necessary to insert a buffer gate after the signal 312.
This leads to a further increase in time.

(2) On the layout of the IC, it is necessary to supply both a low voltage source and a high voltage source to this level shift circuit, and a large number of power supply routes are required. It is difficult to use because of many restrictions.

(3) In order to perform one level conversion, a large number of transistors are required differently from a normal gate.
In addition, the area of the power supply also requires an area, and as a result, the area of the IC increases.

[0011]

A circuit for transmitting a low-voltage signal to a high-voltage circuit includes high-voltage gate means having a control terminal, wherein the low-voltage signal is transmitted to the high-voltage circuit. When the control signal from the high voltage side timing switching circuit is input to the control terminal of the gate means, the gate means is activated so that the low voltage signal passes through the gate means. It is converted to a signal on the high voltage side. Further, the converted signal is latched by a latch circuit operated by a control signal from a timing switching circuit of the high voltage side circuit.

[0012]

According to the above circuit configuration of the present invention, the low voltage side signal is converted into the high voltage side signal by the first gate means, and the converted signal is further converted into the timing switching circuit of the high voltage side circuit. Since the data is latched by a latch circuit operated by a control signal from the controller, high-speed level conversion is possible.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. 1 is a first low-voltage side circuit block,
2 is a second high voltage side circuit block, 3 is a first low voltage side first circuit, 4 is a control signal from a timing switching circuit of a first signal, and 5 is a first signal The signal output from the low voltage side circuit block, 6 is the first gate means, 7 is the latch means in the second high voltage side circuit block, 8 is the second high voltage side circuit The output of the latch means in the block, 9 is the second timing signal from the timing switching circuit, 10 is the timing switching circuit, 11 is the signal in the first low-voltage side circuit block,
12 is a second circuit in the first low voltage side circuit block, 13 is an output from the timing switching circuit to the first low voltage side circuit block, and 14 is a signal from the first gate means. Output. As an example of the first gate means 6 in FIG. 1, as shown in FIG. 5 and FIG.
Although there is a method using a gate or a NOR gate, it is sufficient that the gate means is operated by a control signal, so that there is no problem even if the gate means is a composite gate or the like.

FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. The present invention will be described with reference to FIGS.

A timing signal 13 is output from the timing switching circuit 10 to the first low-voltage side circuit block 1, and the second circuit 12 in the first low-voltage side circuit block.
And the timing signal 11 is input from this circuit to the first circuit 3 on the first low voltage side. In this case, since the timing signal 13 is output from the high-voltage side circuit block, the signal level is high. However, even if the signal is received by the block 12 operating at low voltage, the signal is input at high voltage. At the input, from power supply VDD to ground VSS
Current does not flow constantly.

The signal 5 output from the first circuit 3 on the first low voltage side changes at the timing shown in FIG. At this time, the signal 4 in FIG. 2 is active immediately before the change of the signal 5 by the timing switching circuit 10.

The signal 1 is output from the timing switching circuit 10.
The first gate means 6 is controlled by the control signal 4 from the timing switching circuit for the first signal output before the first signal.
Control gate is opened by signal 4 in FIG.
Output as 4. At this time, for example, the gate means 6
If it is ND, the signal on the low voltage side is converted into the signal 14 on the high voltage side. Specifically, assuming that the low voltage is 3.0 V and the high voltage is 5.0 V, the output is 5 V when the input level is 0 V. When the input level of the input signal 5 on the low voltage side is 3.0 V, the threshold voltage of the gate means 6 is around 1.5 V, so that the output level is around 4 V, which is a high level, which is the next second level. Is input to the latch means 7 in the circuit block on the high voltage side, and data is held by the timing signal 9. In this state, since the P-channel transistor of the gate means 6 is not completely turned off, a current instantaneously flows from the power supply VDD to the ground VSS, but this current flows only in the first signal of FIG. This is only a short time during which the control signal 4 from the timing switching circuit is valid.

The time required for the gate means 6 to be effective is sufficient if the time until the state of the gate means 6 is determined and data is held in the latch means 7 is sufficient. Sufficiently, the signal 5 on the low voltage side is converted into the signal 14 on the high voltage side very quickly, the data is held in the latch means 7, and the level conversion of a series of signals is as shown in the signal 8 in FIG. Ends with

Next, the case where the processing circuit in the second high voltage side circuit block enters after the conversion of the signal level will be described with reference to FIG.
The embodiment will be described in detail.

FIG. 3 is a circuit diagram showing a first embodiment of the present invention. 1 is a first low-voltage side circuit block,
2 is a second high voltage side circuit block, 3 is a first low voltage side first circuit, 4 is a control signal from a timing switching circuit of a first signal, and 5 is a first signal The signal output from the low voltage side circuit block, 6 is the first gate means, 7 is the latch means in the second high voltage side circuit block, 8 is the second high voltage side circuit The output of the latch means in the block, 9 is the second timing signal from the timing switching circuit, 10 is the timing switching circuit, 11 is the signal in the first low-voltage side circuit block,
12 is a second circuit in the first low voltage side circuit block, 13 is an output from the timing switching circuit to the first low voltage side circuit block, and 14 is a signal from the first gate means. Output. As an example of the first gate means 6 in FIG. 1, as shown in FIG. 5 and FIG.
Although there is a method using a gate or a NOR gate, it is sufficient that the gate means is operated by a control signal, so that there is no problem even if the gate means is a composite gate or the like.

FIG. 2 is a timing chart for explaining the operation of the circuit of FIG. The present invention will be described with reference to FIGS.

A timing signal 13 is output from the timing switching circuit 10 to the first low-voltage side circuit block 1, and the second circuit 12 in the first low-voltage side circuit block is output.
And the timing signal 11 is input from this circuit to the first circuit 3 on the first low voltage side. In this case, since the timing signal 13 is output from the high-voltage side circuit block, the signal level is high. However, even if the signal is received by the block 12 operating at low voltage, the signal is input at high voltage. At the input, from power supply VDD to ground VSS
Current does not flow constantly.

The signal 5 output from the first circuit 3 on the first low voltage side changes at the timing shown in FIG. At this time, the signal 4 in FIG. 2 is active immediately before the change of the signal 5 by the timing switching circuit 10.

The timing switching circuit 10 outputs the signal 1
The first gate means 6 is controlled by the control signal 4 from the timing switching circuit for the first signal output before the first signal.
Control gate is opened by signal 4 in FIG.
Output as 4. At this time, for example, the gate means 6
If it is ND, the signal on the low voltage side is converted into the signal 14 on the high voltage side. Specifically, assuming that the low voltage is 3.0 V and the high voltage is 5.0 V, the output is 5 V when the input level is 0 V. When the input level of the input signal 5 on the low voltage side is 3.0 V, the threshold voltage of the gate means 6 is around 1.5 V, so that the output level is around 4 V, which is a high level, which is the next second level. Is input to the latch means 7 in the circuit block on the high voltage side, and data is held by the timing signal 9. In this state, since the P-channel transistor of the gate means 6 is not completely turned off, a current instantaneously flows from the power supply VDD to the ground VSS, but this current flows only in the first signal of FIG. This is only a short time during which the control signal 4 from the timing switching circuit is valid.

The time required to activate the gate means 6 is sufficient if the time until the state of the gate means 6 is determined and the data is held in the latch means 7 is sufficient. Sufficiently, the signal 5 on the low voltage side is converted into the signal 14 on the high voltage side very quickly, the data is held in the latch means 7, and the level conversion of a series of signals is as shown in the signal 8 in FIG. Ends with

Next, in the case where a plurality of input terminals are present in FIG. 8, a plurality of signals can be easily processed by preparing a plurality of the configurations of the first embodiment. It is possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the second embodiment of the present invention.

FIG. 5 is a circuit diagram showing Example 1 of a first gate means in the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a second example of the first gate means in the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing a first example of the latch circuit according to claim 2;

FIG. 8 is a circuit diagram showing an embodiment according to claim 3;

FIG. 9 is a circuit diagram showing a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... 1st low voltage side circuit block 2 ... 2nd high voltage side circuit block 3 ... 1st low voltage side 1st circuit 4 ... 1st signal Control signal from timing switching circuit 5 ... Signal output from first low voltage side circuit block 6 ... First gate means 7 ... Second high voltage side circuit block Latching means 8 ... Output of the latching means in the second high voltage side circuit block 9 ... Second timing signal from timing switching circuit 10 ... Timing switching circuit 11 ... First Signal in low-voltage side circuit block 12 ... Second circuit in first low-voltage side circuit block 13 ... Output from timing switching circuit to first low-voltage side circuit block 14 ... Output from first gate means 15 ... Processing circuit in the second high-voltage side circuit block 16... Output from the processing circuit in the second high-voltage side circuit block to the latch means in the second high-voltage side circuit block 100. A NAND gate 101 as an example of a first gate means; a NOR gate 102 as an example of a first gate means 102; a circuit 201 of a latch means in a second high-voltage side circuit block 201 ... 1, a signal in the low-voltage side circuit block 202: a signal in the first low-voltage side circuit block 203: an output from the first gate means 204: a second high-voltage side ····································································································································・ Inverter circuit 303 ・ ・ ・Voltage-side input terminal 304 P-channel MOS transistor 305 P-channel MOS transistor 306 N-channel MOS transistor 307 P-channel MOS transistor 308 P-channel MOS transistor 309 N-channel MOS transistor 310: High voltage side output terminal 311: Output terminal of inverter circuit 312: Signal converted to high voltage side 313: Signal in level shift circuit

Claims (4)

[Claims] In a circuit for transmitting a first signal on a first low voltage side to a circuit on a second high voltage side, a first gate means having a first control terminal, and the first signal is a first signal. Connected to the first gate means, and the first output terminal of the first gate means is connected to the second output means.
And a control signal from the timing switching circuit for the first signal is connected to a control terminal of the first gate means. Semiconductor circuit device. 2. The semiconductor circuit device according to claim 1, wherein the input means of the high-voltage side circuit according to claim 1 includes a latch circuit operated by a signal from a control signal from a timing switching circuit of the first signal. 3. The first gate means according to claim 1, wherein:
A processing circuit in a second high-voltage side circuit block between an output terminal of the second high-voltage side and a latch circuit operated by a signal from a control signal from the timing switching circuit of the first signal in claim 2. A semiconductor circuit device characterized by the above-mentioned. 4. A semiconductor circuit device having a plurality of configurations according to claim 1 and claim 2, and a plurality of configurations according to claim 1, 2, and 3.