JP2000022092A - Monoelectronic memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable data to be written in or erased out from a monoelectronic memory device with a low voltage, by a method wherein the monoelectroic memory device can be kept in a bistable state where it can be kept stable both in a memory state and in a non-memory state. SOLUTION: A barrier island 24B is formed on the channel 23A1 of a semiconductor MOSFET through the intermediary of a first tunnel insulating film 24A, and a memory island 24D is formed thereon through the intermediary of a second tunnel insulating film 24C. Moreover, a gate electrode 24F is formed on the memory island 24D through the intermediary of a comparatively thick insulating film 24E.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single-electron memory device.

[0002]

2. Description of the Related Art A conventional element called a single-electron memory is:
Fabricated using a silicon MOS transistor (for example, L. Guo, E. Leobandun)
g, andS. Y. Chou, Appl. Phys. L
ett. 70 volumes, p. 850-852 (1997),
Or A. Nakajima, T .; Futatsug
i, K. Kosemura, T .; Fukano, and
N. Yokoyama, Appl. Phys. Let
t. 70 volumes, p. 1742-1744 (1997)
Year)).

The basic structure of a single-electron memory is similar to a known memory element called a flash memory, and a small conductive film is formed on a channel of a MOSFET having a narrow channel width through an insulating film thin enough to allow electrons to tunnel. It has a structure in which islands of the body are arranged (it will be described in the case of n-channel). FIG. 8 shows a typical structure when this is realized on an SOI substrate in which single crystal silicon is formed on a silicon oxide film. Here, FIG. 8A is a plan view of a single-electron memory element, and FIG. 8B is a cross-sectional view thereof.

In this single-electron memory device, as shown in FIG. 8A, a thin upper single-crystal silicon layer 13 on an SOI substrate 10 is processed into a thin line portion 13A and wide portions 13B at both ends thereof. Then, the deposition film 14 is formed on the fine line portion 13A. That is, as shown in FIG.
An insulating film 14A (eg, a thin silicon oxide film) made of a thin insulating film and capable of tunneling electrons is formed on 3A, and a small conductor layer (referred to as a memory island 14B) is formed thereon.
Is further formed thereon, and a relatively thick insulating film 14C (having a thickness that does not cause electron tunneling) is formed thereon, and another conductive layer (referred to as an upper gate electrode 14D) is formed via the insulating film 14C. Is formed.

In this single-electron memory device, a channel (region through which electrons flow) of a narrow MOSFET is formed in a thin line portion 13A.
13A1 are formed, and the memory islands 14B are formed on the thin line portions 13A via the tunnel insulating films 14A as described above.
Is formed. Then, electrons are injected into the memory island 14B by tunneling from the channel 13A1 of the thin line portion 13A, and the electrons are stored. This state corresponds to the "1" state in which electrons have been written to the memory island 14B. Conversely, when electrons exit from the memory island 14B by tunneling, the state becomes "0" where data is not written or the state where data is erased. Whether these electrons are written to or erased from the memory island 14B is determined by the voltage applied to the upper gate electrode 14D. That is, when a positive voltage is applied to the upper gate electrode 14D with respect to the channel of the thin line portion 13A, the electrons of the channel are tunneled to the memory island 14B by the positive voltage. Conversely, when a negative voltage is applied to the upper gate electrode 14D, it repels and causes the memory island 14D to repel.
From B, it goes out to the channel 13A1 of the thin line portion 13A.

Whether or not electrons have been written to the memory island 14B depends on whether the voltage of the upper gate electrode 14D is set to a predetermined value, the channel 13A1 of the thin line portion 13A located in the lower part of the memory island 14B in the drawing. It can be known by conductance. That is, when electrons are injected into the memory island 14B, the channel 1 of the MOSFET in the thin line portion 13A
The detection is performed by utilizing the fact that the conductance of the channel 13A1 is low because the threshold value of 3A1 is shifted to the positive side.

[0007]

In the conventional single-electron memory device, it is determined whether the electrons stored in the memory island 14B do not enter the channel of the thin line portion 13A after the end of the writing process.
Alternatively, since it is important that electrons do not enter the memory island 14B in the “0” state without going through the writing process,
The tunnel resistance between the channel of the thin line portion 13A and the memory island 14B is set to be considerably high. Therefore, writing,
There is a problem that relatively large positive and negative voltages are required for erasing, respectively.

The writing and erasing operations of this single-electron memory element are basically the same as those of a known flash memory, and this problem cannot be solved by reducing the size of the device. In addition, in a single-electron memory, the above-mentioned memory island 14 is used.
The size of B is reduced so that only a few electrons enter. This point is effective as a power-saving element because the number of stored electrons can be extremely reduced. However, in such a system, when n electrons are put into the memory island 14B,
Assuming that the elementary charge of electrons is e and the total capacity of the memory island 14B is C, the potential of the memory island 14B increases by ne / C. Here, when the size of the memory island 14B is reduced, the n
, The rise in the potential of the memory island 14B cannot be ignored, so that the effect that one electron becomes difficult to enter the next electron becomes remarkable. This means that, when two or more electrons are stored in the memory island 14B, the electrons of the electrons tend to be discharged from the island due to repulsion of the charges of each electron. This is disadvantageous as a memory device.

In the first place, this single-electron memory element has a state in which electrons are stored in principle even if it is assumed that the electrons to be stored are one in which there is no repulsion between the electrons and an optimal design is made. And the state that is not stored has the same energy, and transitions without passing through a state having a higher energy as an intermediate state between the two states. Therefore, it cannot be said that the state is a bistable state. The basic operation of holding the memory is to merely reduce the probability that electrons leave the memory island by increasing the tunnel resistance. Some conventional single-electron memories have a structure different from that of FIG. 8, but the basic operation is the same as that of the single-electron memory of FIG. As described above, the conventional single-electron memory has a drawback that a relatively large voltage is required for writing and erasing since the memory state and the non-memory state cannot be made bistable.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to enable writing and erasing of a memory with a small voltage by enabling a state of being stored and a state of not being stored to be bistable.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method of forming a barrier which is formed on a channel of a MOS transistor made of a semiconductor via at least a first tunnel insulating film. The first conductive island and the first conductive island
A second conductive island serving as a memory formed on the conductive island via a second tunnel insulating film, and an electrode capacitively coupled to at least the second conductive island. . In addition, a first conductive island serving as a barrier formed on at least a single electron island of a semiconductor single electron transistor via a first tunnel insulating film, and a second conductive island formed on the first conductive island. The semiconductor device includes a second conductor island serving as a memory formed through an insulating film, and at least an electrode capacitively coupled to the second conductor island. At least one of the first and second conductor islands is composed of two or more conductor islands, and each conductor island is separated from each other by an insulating film.

[0012]

Next, the present invention will be described with reference to the drawings. In the following embodiment, the MO of silicon will be described.
The description will be made based on the configuration or manufacturing process of the S-type transistor. It goes without saying that a device / process configuration using another material, for example, a compound semiconductor is also possible. In the following description of each embodiment,
The case of n-channel (electrons are carriers) will be described for convenience of explanation. Note that, in the case of a p-channel element as long as the element operates similarly by replacing electrons with holes, the following embodiments can be applied in the same manner as in the case of the n-channel.

(1) First Embodiment First, as a first embodiment of the present invention, an example of a single island type structure similar in structure to the conventional single electron memory already described with reference to FIG. 1 will be described. Here, since the isolation of the element is simple, an SOI in which a single-crystal silicon layer 23 is further formed on the single-crystal silicon 21 via a silicon oxide film 22 (referred to as a buried oxide film) over the silicon oxide film 22
I wafer 20 (SIMOX, bonded wafer, etc.)
The structure of a MOS type transistor using a MOS transistor will be described.
An OS transistor may be used.

As shown in the plan view of FIG.
The thinned upper silicon layer 23 of the wafer 20 is processed into a structure having a narrow region (fine line portion 23A) and wide regions (wide portions 23B) at both ends thereof. Further, on the fine line portion 23A of the upper silicon 23, FIG.
As shown in the cross-sectional view of FIG. 2B, a barrier island 24 made of a first conductor is sandwiched across a first thin tunnel insulating film 24A.
Form B. Then, a memory island 24D made of a second conductor is formed on the barrier island 24B with a second thin tunnel insulating film 24C interposed therebetween.
An upper gate electrode 24F is formed on D with a relatively thick insulating film layer 24E interposed therebetween.

In the manufacturing process of such a single-electron memory device, first, a thin silicon oxide doped with, for example, phosphorus or the like as a first thin tunnel insulating film 24A is formed on a thinned upper silicon 23 of an SOI wafer 20. A film is formed by a thermal oxidation method or the like, and a first barrier island 24B is formed thereon.
For example, a thin polycrystalline or amorphous silicon layer is formed. Next, for example, a thin silicon oxide film is formed as a second tunnel insulating film 24C on the silicon layer by a CVD method or a thermal oxidation method.
Further, on the oxide film, a thin polycrystalline or amorphous silicon layer doped with, for example, phosphorus is formed as a second conductive layer which is the memory island 24D. Subsequently, a silicon oxide film, for example, is formed as an insulating film layer 24E on the silicon layer by a CVD method or a thermal oxidation method. After the formation of the laminated film 24, the portions that become the barrier islands 24B and the memory islands 24D are processed by known electron beam lithography and etching, and etching is performed when the first conductive layer (barrier island 24B) is processed into islands. Suspend,
A new structure having a thin wire portion 24B and wide portions 24A at both ends is obtained to obtain a structure as shown in FIG. The upper layer gate electrode 24F can be formed after processing, or can be formed and placed on the laminated film 24 and processed simultaneously with the processing of the memory island 24D.

Next, the operation of the single-electron memory device thus manufactured will be described. FIG. 2 shows a simplified equivalent circuit of this single-electron memory element. The gate electrode 24F
It is assumed that the capacitive insulating film 24E between the memory island 24D and the memory island 24D is thick and electrons cannot tunnel. Here, the thin line portion 23A
Is formed with a small-sized MOSFET channel 23A1.
Is connected to the barrier island 24B via the tunnel insulating film 24A, so that a tunnel capacitance C1 of the insulating film 24A is sandwiched between the barrier island 24B and the channel 23A1 of the thin wire portion 23A. Further, a circuit configuration is provided in which the memory island 23C is present thereon via the tunnel capacitance C2 of the insulating film 24C, and the gate electrode 24F is further provided thereon via the insulating film 24E. In such a structure, when the size of the barrier islands 24B and the memory islands 24D is small, the capacity (total capacity of the island with respect to the outside world including the tunnel capacity) becomes small. If one electron is added to such an island, the energy of the island is e
^It rises by ² / 2C total. However, the total capacity of the island is C
total and the elementary charge of the electron is e.

First, consider a state where the work functions of all the conductors are equal and no voltage is applied to each electrode. For example, the size of the barrier island 24B is
Considering that the total capacity of the barrier island 24B is made smaller than the total capacity of the memory island 24D, for example, by making it slightly smaller than 4D, and electrons are written into one island, the electrons are stored in the barrier island 2B.
It is more stable in the memory island 24D than in the memory island 4B. (It is not necessary that such a size relationship be established. However, this example is more effective and easy to understand.) This is explained using an example).

When electrons are written to the memory island 24D, the potential of the memory island 24D rises. However, when the electron moves to the barrier island 24B, such a tunnel does not occur because the energy rises more than the memory island 24D. Electron is Memory Island 24D
In order to get out, the electrons need to move once to the barrier island 24B and exit to the channel 23A1 of the thin line portion 23A, but this process cannot be taken. Therefore, one electron can stably exist in the memory island 24D.
In order to forcibly eject electrons from the memory island 24D,
When a negative voltage is applied to the gate electrode 24F, the energy is more stable when electrons move to the barrier island 24B due to the effect of the electric field, the electrons are discharged to the barrier island 24B, and the channel of the finer wire portion 23A is more stable. What is necessary is just to change to the state moved to 23A1.

On the other hand, in order to write electrons into the memory island 24B, a positive voltage is applied to the gate electrode 24F, and the electrons can be drawn into the memory island 24B through the reverse process by the electric field in the opposite direction. is there. Thus, writing,
The method of applying a positive or negative voltage to the gate electrode 24F only at the time of erasing is the same as that of the conventional example described above. But,
In the present invention, it is conventional to hold the electrons of the memory island 24D or to prevent the electrons from entering the memory island 24D from the channel 23A1 of the thin wire portion 23A when there is no electron in the memory island 24D as in the conventional example. Instead of increasing the tunnel resistance, a barrier island 24B is inserted. Therefore, the confinement of electrons and the tunnel resistance are irrelevant (at a finite temperature, the two tunnel insulating films 24
If the tunnel resistance of A and 24C is too small, a cooperative tunnel phenomenon, which is a higher-order tunnel phenomenon, occurs, so that a somewhat high tunnel resistance is required. Since a technique for improving this will be described later), high-speed writing and erasing can be performed with a small applied voltage.

The detection of electrons written in the memory island 24D is performed by detecting the small MOSFET channel 23 in the thin line portion 23A.
It is detected by the conductance between the source S and the drain D of A1. For example, when electrons enter the memory island 24D, the capacitance obtained by connecting the two tunnel capacitors C1 and C2 in series (determined by the capacity between the channel of the thin line portion 23A and the memory island, and in addition, directly from the memory island to the channel of the thin line portion 23A) It is possible to detect the decrease in the conductance of the channel 23A1 of the thin line portion 23A via the capacitance that acts correctly).

In the above description, the method in which no voltage is applied between the channel 23A1 of the thin line portion 23A and the gate electrode 24F in the holding state other than the writing and erasing operations has been described. In order to make the energy of the state without memory exactly the same,
It is preferable to apply a slightly positive voltage to the gate electrode 24F in the holding state (the work function can be adjusted by changing the electrode material). As described above, considering the method of applying the gate voltage in the holding state, it is not necessary to limit the total capacity of the barrier island 24B to be smaller than the total capacity of the memory island 24D as described above. Electrode 2
The energy of the state stored in the memory island 24D at the voltage of 4F and the energy of the state not stored in the memory island 24D may be made exactly the same.

Further, when the size of the island becomes smaller, the energy increase when one electron is added becomes larger than that determined by the capacity of the island due to the quantum confinement effect. It is necessary to incorporate this effect into the optimal design. Further, considering operation at a finite temperature, two tunnel insulating films 24 are required.
If the tunnel resistance of A and 24C is too small, a cooperative tunnel phenomenon, which is a higher-order tunnel phenomenon, occurs. In order to prevent this, the tunnel resistance may not be set low. This hinders high-speed writing and erasing operations. In order to solve this, a large number of barrier islands 24B may be inserted in series. Thereby, the cooperative tunnel phenomenon can be suppressed. In the example of FIGS. 1 and 2, barrier island 24B
However, as shown in FIG. 3, the barrier islands 23B1 and 23B2 and the tunnel insulating film layers 24A1 and 24A1
This is made possible by forming 24A2.

FIG. 3 is an equivalent circuit when two barrier islands are used. The more the number of barrier islands inserted in series is increased, the more the cooperative tunnel phenomenon can be suppressed. However, since the effective capacity between the channel 23A1 of the thin wire portion 23A and the memory island 24D also becomes smaller, the memory island 24D It should be noted that the sensitivity of detecting existing electrons by the channel conductance of the thin wire portion 23A is reduced.

(2) Second Embodiment In a second embodiment, the structure shown in FIG. 1 which is an example of the element formation method of the present invention using SOI, which has been described as an example in the first embodiment, will be described. In the case where a multilayer film is formed in the method described in the above, the second conductor layer (conductor layer to be the memory island 24D)
After forming a polycrystalline or amorphous silicon layer, a multilayer film is processed into an island structure (in the first embodiment, processing is performed after forming an insulating film thereon, but the method described here is also used in the above example. Needless to say, it can be used).

Next, after forming the thin line portion 23A and the wide portion 23B, the structure is thermally oxidized at a temperature of, for example, 1000.degree. By this thermal oxidation, the upper part of the memory island 24D in the uppermost layer is oxidized, and a relatively thick oxide film is formed. At this time, the silicon constituting the memory island 24D is changed to silicon oxide by oxidation, so that the amount of silicon that becomes the memory island 24D decreases. Therefore, it is necessary to increase the initial thickness of the silicon layer in consideration of this. Oxidation occurs not only in such a vertical direction (vertical direction) but also in a horizontal direction (horizontal direction) in the island structure shown in FIG.
It is necessary to consider that the sizes of the memory island 24D and the barrier island 24B are reduced in the horizontal direction. Furthermore, in this oxidation process, the SOI is affected by the diffusion of oxidizing chemical species (moisture or oxygen) through the buried oxide film and the stress caused by oxidation at the fine wire portion 23A or the pattern edge portion.
Oxidation occurs depending on the pattern shape of the upper silicon,
A phenomenon occurs in which both ends of the thin wire become thinner than the thin wire portion 23A and the wide portion 23B.

If the thickness of the upper silicon layer of the initial SOI is set to an appropriate thickness (for example, about 20 nm to 50 nm in the case of oxidation at 1000 ° C.), the thinned portion is used as a tunnel capacitor, and the silicon thin wire portion 23A1 is formed. Can be changed to small silicon islands.
275544: Coulomb blockade element and its manufacturing method). That is, as shown in the equivalent circuit of FIG. 4, a silicon island 24G (single electron island; hereinafter, referred to as a SET island 24G) is formed below the barrier island 24B, and a tunnel capacitance is formed between the silicon island 24G and the wide portions 23B at both ends. C3, C4
Is obtained. And memory island 2 of this structure
A gate electrode 24F is formed on 4D.

In this single-electron memory device, the MOSFET channel 23A1 of the single-electron memory device shown in FIGS.
The device has a structure replaced with A2. In this device, the presence or absence of electrons in the memory island 24D is detected by the source-drain conductance of the single-electron transistor (SET) 23A2 instead of the channel conductance of the MOSFET. Electrons to the memory island 24D are transferred from the source S or the drain D to the SET island 24D.
G and the barrier island 24B. The advantage of this structure is that the SET island 24G and the barrier island 24
4, the device shown in FIG. 4 has an effect of suppressing a cooperative tunnel, like the element of FIG. 3 in which two barrier islands 24B are effectively arranged in series.

Therefore, as shown in the equivalent circuit of FIG. 5, this single-electron memory element operates as a memory even in a structure in which the barrier island 24B is omitted from the device of FIG. here,
When a positive voltage is applied to the memory gate electrode 24F, the Coulomb blockade of the SET island 24G acting as the barrier island 24B is broken, and a single electron from the source S (or drain D) passes through the SET island 24G. Memory Island 2
4D. When the potential of the gate electrode 24F is returned to its original state, the SET island 24G, which is the barrier island 24B, enters a Coulomb blockade state, so that the electrons on the memory island 24D cannot escape. Accordingly, a state is reached in which a single electron is stored in the memory island 24D (write state). To erase this, a negative voltage is applied to the memory gate electrode 24F to break the Coulomb blockade of the SET island 24G and cause the source island S from the memory island 24D via the SET island 24G.
(Or drain D). In this case, the memory island 24D is in the erased state. like this,
Increase / decrease of single electron due to writing / erasing of memory node
It can be read as a change in the conductance of the SET island 24G connected to the memory island 24D via the tunnel capacitance C2.

In this case, the barrier island 24 shown in FIG.
The same operation is performed in the configuration where B is arranged. In this case, since the barrier island 24B is inserted, the Coulomb blockade is more stably formed, and in addition to the effect of suppressing the cooperative tunnel, there is also an effect of making it less susceptible to the influence of floating charges around the island.

(3) Third Embodiment In the above first and second embodiments, the memory island 24D
And the case where the barrier island 24B is constituted by a single silicon island (in the case of being in series, each island is considered to play a role as a barrier island). However, barrier island 24B or memory island 2
Many 4Ds may exist in parallel. Here, an example thereof will be described.

FIG. 6 shows an example. The example of FIG.
In the first embodiment, the barrier islands 24B and the memory islands 24D are each formed by a layer composed of a large number of minute conductive islands. Therefore, barrier islands 24B and M
The channel 23A1 of the OSFET and the barrier island 24B and the memory island 24D are separated from each other via a tunnel insulating film 26 such as a thin silicon oxide film. However, the individual islands 27, 2 in the minute conductor island layer that becomes the barrier island 24B and in the minute conductor island layer that becomes the memory island 24D
8 may be separated by a tunnel insulating film or may be separated by a non-tunnel insulating film.

Various methods are known for producing such a fine conductor island layer. For example, when silicon or tin atoms are ion-implanted into a silicon oxide film and heat treatment is performed, silicon and tin in the oxide film gather in an island shape to form a small silicon or tin island layer. Or,
When silicon is deposited on the surface of the silicon oxide film in a vacuum, silicon atoms adsorbed on the silicon oxide film migrate on the surface of the oxide film to form small silicon islands.

The size and density of the islands are variable depending on the deposition rate of silicon to be deposited, the temperature of the substrate, and the amount of deposition. CV using silane or disilane gas instead of vapor deposition
A similar silicon island can be formed by using the D method. Such a conductive island is composed of another element (semiconductor or metal element such as Ge).
Is also formed when is deposited on an insulating film by vapor deposition or the like.
In addition, there is a method of dispersing on the surface of the insulating film using gold colloid or the like. Since it is necessary to fabricate two small conductive island layers of a barrier island layer and a memory island layer, for example, in a method of forming islands in an insulating film by ion implantation or the like, two layers of ions are formed by changing energy. In the method of forming islands on the surface by vapor deposition or the like, a method of forming islands on the surface is to form a thin tunneling cotton ginning film by vapor deposition or a CVD method. After that, another fine conductive island layer may be formed again.

In the device having this structure, if the size of the islands is not uniform to some extent, the voltage at which Coulomb blockade occurs differs. Therefore, when electrons are stored in the islands,
If the positive voltage applied to the upper gate 24F is small, electrons will not be stored in some islands. On the other hand, once it enters, if there is a small negative gate voltage for erasure, some islands will not be erased.

In this device, electrons stored in a large number of memory islands are detected by the conductance of the channel of the thin wire portion 23A, and the number of electrons stored in the entire island layer is not one, but strictly speaking. It is not a single-electron memory. When the size of each island varies, the number of electrons stored in each memory island varies for each island. Furthermore, although islands where electrons are stored and islands where no electrons are stored are mixed, the conductance of the channel 23A1 of the thin line portion 23A is the same as the length and width of the channel 23A1 of the channel 23A1 of the thin line portion 23A. If the number is large, it appears as an average effect of the stored electrons, so if the number of electrons on the island can be increased or decreased on average, it operates as a memory device.

Conversely, in order to increase the probability of obtaining an element that operates with desired characteristics when the variation in the size of islands is large, the number of islands per width and length of the channel 23A1 of the thin wire portion 23A must be increased. It is necessary to keep. As a matter of course, when the size of the islands is uniform, the operable range is widened (or the difference between the memory state and the non-memory state is increased), and the variation in characteristics among the elements is reduced.

In this example, the case where the barrier island 24B has one layer has been described, but it is possible to use two or more layers as in the above embodiment. Needless to say, a MOSFE for detecting stored electrons is used.
Instead of the T channel, the single-electron transistor described in the second embodiment may be used.

(4) Fourth Embodiment The structure of the third embodiment has a structure in which the memory island 24D has two
Although a small conductor island layer arranged in a dimensional manner is used, as shown in FIG. 7, the barrier island 24B is still a small conductor island layer, and the memory island 24D is the same as a single conductor island. Works. This structure is the same as the extreme configuration of the third embodiment in which the probability of a lateral tunnel in the memory island layer is increased. In this structure, electrons are transferred to the memory island 2
When writing to 4D, a positive voltage is applied to the gate electrode 24F to break the Coulomb blockade of the barrier island 23B and inject electrons from the channel 23A1 of the MOSFET to the memory island 24D. Kade first (maybe at lower voltage)
Electrons are injected through the island.

Conversely, when erasing electrons, they are discharged through the island. Also, when the memory state is maintained, the electrons of the memory island (in this case, from 0 to the number corresponding to the barrier island) are maintained in the memory state within a range where the Coulomb blockade of the island is not broken. Therefore, almost all of the islands where the Coulomb blockade breaks at the outset will determine device characteristics. The smaller the island size,
Since the Coulomb gap is large and can operate stably, it is important to keep the maximum island size small.

As described above, in the single-electron memory element, the barrier island 23B is inserted between the memory island 24D and the channel 23A1 of the MOSFET transistor for detecting the presence or absence of electrons in the thin line portion 23A. Therefore, there is an effect that the state where electrons are stored in the memory island 24D and the state where they are not stored can be stably held, and the writing and erasing of electrons can be performed at high speed with a small applied voltage.
Also, by slightly devising the manufacturing method, a single-electron transistor 2 is used instead of the MOSFET to detect the presence or absence of electrons.
In this structure, the SET island 24G of the single-electron transistor 23A2 is replaced with the barrier island 24G.
It functions as B and can simplify the structure.

[0041]

As described above, according to the present invention, between the second conductive island serving as a memory and the channel of the transistor for detecting the charge stored in the second conductive island,
Since the first conductive island serving as a barrier is formed, electron transfer by a tunnel between the second conductive island and the channel is prevented by the first conductive island. Even if the resistance is not large, the memory state and the non-memory state can exist in a bistable manner, so that writing and erasing of the memory can be performed with a small voltage, and rewriting of the memory can be performed at a high speed. Can be done with

[Brief description of the drawings]

FIG. 1 is a diagram showing a first structural example of a single-electron memory device according to the present invention.

FIG. 2 is a diagram illustrating an example of a first equivalent circuit of a single-electron memory element.

FIG. 3 is a diagram illustrating an example of a second equivalent circuit of the single-electron memory element.

FIG. 4 is a diagram illustrating an example of a third equivalent circuit of the single-electron memory element.

FIG. 5 is a diagram illustrating an example of a fourth equivalent circuit of the single-electron memory element.

FIG. 6 is a diagram showing a second structure example of the single-electron memory element.

FIG. 7 is a diagram showing a third example of the structure of the single-electron memory element.

FIG. 8 is a diagram showing a structural example of a conventional single-electron memory element.

[Explanation of symbols]

Reference numeral 21: silicon substrate, 22: silicon oxide film, 23: single crystal silicon, 23A: thin line portion, 23A1: MOSFE
T channel, 23A2 ... single electron transistor, 23B ...
Wide part, 24 ... Laminated part, 24A ... Tunnel insulating film, 24
B: barrier island, 24C: silicon oxide film, 24D: memory island, 24E: silicon oxide film, 24F: gate electrode,
24G: SET island, 26: oxide film, 27, 28: minute conductive island.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yukinori Ono 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo F-term in Nippon Telegraph and Telephone Corporation (reference) 5F040 DC01 EA08 EB12 5F083 FZ01 HA02

Claims (4)

[Claims] A first conductive island serving as a barrier formed at least via a first tunnel insulating film on a channel of a MOS transistor made of a semiconductor; and a second conductive island provided on the first conductive island. A single-electron memory element comprising: a second conductive island serving as a memory formed through a tunnel insulating film according to (1); and at least an electrode capacitively coupled to the second conductive island. 2. A first conductive island serving as a barrier formed on at least a single electron island of a single electron transistor made of a semiconductor via a first tunnel insulating film, and a second conductive island formed on the first conductive island. 2. A single-electron memory device comprising: a second conductive island serving as a memory formed via a second tunnel insulating film; and at least an electrode capacitively coupled to the second conductive island. . 3. The conductive island according to claim 1, wherein at least one of the first and second conductive islands comprises two or more conductive islands, and each of the plurality of conductive islands is formed of an insulating film. A single-electron memory device characterized by being separated. 4. The conductive island according to claim 2, wherein at least one of the first and second conductive islands comprises two or more conductive islands, and each of the plurality of conductive islands is formed of an insulating film. A single-electron memory device characterized by being separated.