JP2000021197A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To variably set timing of a write command read time (tRWL) for a RAS bar signal shorter than a specified value and a precharging time (tRP) to be desirably measured by executing operation tests at the tRWL for a RAS bar signal shorter than a specified value and the tRP. SOLUTION: When a RAS bar is set to 'L' (active), an internal RAS bar of an output end (a) becomes active, and a potential of a word line is raised to 'H'. Thereafter, a WE bar signal is set to 'L', and a write operation is started (timing t1). After the WE bar is input, the RAS bar is reset via a Delay 1 to 'H' (timing t2). Thus, the potential of the word line is lowered to the 'L', and writing in the memory cell is ended. Thereafter, an external RAS bar is set to the 'H', and reset (timing t3). A tRWL observed at an external signal is (t3-t2), but in a substantial operation, the tRWL becomes (t2-t1) according to the internal RAS bar signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of executing an operation test in a time shorter than a prescribed value that defines a timing interval between two signals determined by the device. It relates to a storage device.

[0002]

2. Description of the Related Art In a dynamic RAM (hereinafter, referred to as a DRAM), which is one type of semiconductor memory device, a sense amplifier amplifies a potential change of a data line due to charging / discharging of a small amount of charge to a memory cell. “1” and “0” are stored, and a memory operation is performed.

For example, to read data from a storage cell, first, a word line, that is, a row (row) in the Y direction is selected by a row address, and data of a memory cell connected to the selected word line is read. It is output to a digit line, that is, a column in the X direction. These data are compared and amplified by the sense amplifier with the data of the dummy cell selected at the same time, and rewritten to the previously read memory cell.

Next, a column switch is selected by a column address to select one of the above-mentioned memory cells,
Data of the selected cell is read onto the I / O bus connected to this column switch. The data read onto the I / O bus is output to the outside via a data amplifier.

The write operation is the same as the read operation up to the operation of amplifying the memory cell data selected by the row address with the sense amplifier and rewriting. After the operation of the sense amplifier, the write data is input to the digit line selected by the column address, and the data is written to the target memory cell.

The number of memory cells selected by one row address is, for example, 2048 in the case of a 1-Mbit memory device. In one memory cycle or refresh cycle, 2048 memory cells are simultaneously refreshed. .

The control signals in this DRAM are as follows:
There are a row address strobe (RAS) bar signal, a column address strobe (CAS) bar signal, and a write enable bar signal (WE). In addition, an output enable (OE) bar signal is prepared as needed.

The RAS bar signal takes in a row address, selects a corresponding word line, activates a sense amplifier, that is, reads and writes, and also refreshes a memory cell selected by the input row address. This is a control signal.

The CAS bar signal fetches a column address, connects the digit line connected to the sense amplifier already activated by the RAS bar signal to an I / O line inside the semiconductor memory device, and inputs and outputs data. This is a control signal to be controlled.

The WE bar signal is composed of the RAS bar signal and C
This is a control signal that activates the AS bar signal and enables a read / write operation.

The OE bar signal is a control signal that activates a read operation to put an input / output terminal in an output state.

DRA controlled by the above control signal
A case of testing the electrical characteristics of M will be described with reference to FIG. 10 which shows a waveform diagram when testing for tRWL (WE ↓ to RAS ↑) as one of the conventional examples.
There is a write command read time tRWL for the RAS bar signal as one of the important elements of the standard value that determines the characteristics of the DRAM.

This write command read time tRWL
Defines the time from the fall timing of the activation of the WE bar signal to the rise timing of the RAS bar signal, and the fall timing of the WE bar signal (W
E ↓) starts the data write operation. Also,
The RAS reset operation is performed at the rising timing of the RAS bar signal (RAS #). That is, it can be seen that the timing of the test operation is determined by the input timing of these external signals.

[0014]

As described above, DRA
The electrical characteristics of M are RAS bar signal, WE bar signal, CA
It is determined by the input timing of the external signal such as the S-bar signal. However, if the timing between the signals cannot be controlled at an interval shorter than the timing to be tested due to the limitation of the measuring device for testing the electrical characteristics of the DRAM, It is impossible to test for timing,
Timing that cannot be tested by measuring equipment (spec)
was there.

The reason is that when testing for the timing between two signals, the internal operation has only a mechanism controlled by the two signals, so that it is necessary to wait from the first input signal to the next input signal. Because.

An object of the present invention has been made in view of the above-mentioned drawbacks of the related art, and a write command read time (tRWL) and a precharge time for a RAS bar signal for a time shorter than a prescribed value determined by a measuring device. (TR
The operation test in P) can be executed, and the timing of tRWL and tRP to be measured is made variable.

[0017]

A feature of the semiconductor memory device according to the present invention is that a timing of a change of a predetermined first external input signal and a timing of a change of a predetermined second external input signal to be inputted subsequently. In a semiconductor memory device in which the interval is defined in advance as a predetermined value and various control signals are set so as to operate according to the predetermined value, at the time of testing, a test is performed based on the first external input signal having a pulse width narrower than this signal. A first internal input signal is generated, and the internal circuit is pseudo-desirably operated by the test internal signal, so that the internal circuit operates in a time shorter than the predetermined value without waiting for the timing change of the first external input signal. Test time control means for reducing the test time.

Further, in the test time control means,
The first external input signal determines a row address strobe (R) for determining the start and activation of operation inside the semiconductor memory device.
AS) Write enable (WE) that is a bar signal and the second external input signal permits writing to a memory cell.
There is a bar signal, and instead of the predetermined value from the rising timing of the WE bar signal to the falling timing of the RAS bar signal, the timing interval from the rising timing of the WE bar signal to the falling timing of the internal signal for testing is changed. Can be set and tested.

Further, in the test time control means, the first external input signal is a RAS bar signal,
The test may be performed by setting a timing interval from the rising timing of the RAS bar signal to the falling timing of the test internal signal instead of the predetermined value from the rising timing to the falling timing of the RAS bar signal.

Furthermore, the above R supplied to the internal circuit
As the AS bar signal, the test internal signal can be used for both the test and the normal operation.

In addition, the test time control means may include the R
The test internal signal may be generated by a logical product of an AS bar signal and a signal obtained by delaying the RAS bar signal by a predetermined time and having a polarity inverted.

Further, the test time control means generates the test internal signal by a logical product of a polarity inversion signal of the RAS bar signal and a signal obtained by delaying the WE bar signal by a predetermined time. You can also.

Further, the test time control means includes:
A logical inversion signal of a logical product of a signal obtained by inverting the polarity of the signal obtained by delaying the WE bar signal by a predetermined time and a test signal set by a test program, and a logical inversion signal of the RAS bar signal. It is also possible to adopt a configuration in which a product is obtained and the test internal signal is generated by this logical product.

In addition, the test time control means may include the R
An AS bar signal is input to a set terminal, and a polarity inversion signal of the WE bar signal and the W signal are input to a reset terminal.
A set program output signal of the SR flip-flop circuit for inputting a signal obtained by delaying the E-bar signal by a predetermined time, a signal obtained by inverting the polarity of the signal obtained by delaying the WE-bar signal by a predetermined time, and a test program. It is also possible to adopt a configuration in which the logical inversion of the result of the logical product with the test signal is further logically obtained, and the test internal signal is generated by the logical product.

Furthermore, the amount of delay of the signal obtained by delaying the WE bar signal by a predetermined time can be made variable.

Furthermore, the above R supplied to the internal circuit
The AS bar signal can be operated by the test internal signal only during a test.

Further, the time from the change timing of the signal obtained by delaying the WE bar signal by a predetermined time to the rise change timing of the internal signal for test is defined as the time of the signal path in normal operation and the signal in test. By setting the size of the transistor in advance so that the time of the path is equal or the time of the signal path at the time of the test is shorter, even if the delay amount fluctuates due to the process condition fluctuation at the time of manufacture, the predetermined value It can be operated to satisfy the value.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The gist of the present invention is that when testing the timing between certain signals, the timing is internally generated from the first signal input, and the same operation as when the next signal is input is performed. The test is performed without waiting for the signal input.

First, a first embodiment of the present invention will be described with reference to the drawings. DRA as an embodiment of the present invention
FIG. 1 shows a circuit diagram of a first embodiment used when testing tRWL (WE ↓ to RAS ↑) in M.
, An inverter 1 for inputting a RAS bar signal input from an external terminal (hereinafter, referred to as an external RAS bar signal) and a delay element (hereinafter, referred to as a Delay) 1 for inputting a WE bar signal from an external terminal. 2) and this Del
The output terminal of the ay1 (2) and the output terminal of the inverter 1 are respectively connected to the input terminals of the two-input NAND3, and the internal RAS bar signal a from the output terminal a of the two-input NAND3. Take out).

That is, the internal R output from the output terminal a
The AS bar signal a is formed from an externally input external RAS bar signal and WE bar signal, and the external RAS bar signal has a logical low level (hereinafter referred to as “L” level).
And the internal RAS signal a is at the "L" level when the WE signal is at the high level (hereinafter referred to as "H" level).

Referring to FIG. 2 showing a waveform diagram when testing tRWL as the first embodiment of the present invention using the above-described configuration, first, an external input signal, that is, external R
The AS bar signal is set to the “L” level (active). The polarity is inverted by the inverter 1 by this “L” level.
At this time, the WE bar signal is not yet activated and is in the "H" level state. Therefore, the internal RAS bar signal a at the output terminal a of NAND3 becomes active, and the potential of the word line rises to "H" level. Become.

Thereafter, the WE signal, which is an external input signal, is set to the "L" level to start the write operation (timing t1).

After inputting the WE bar signal, Delay1 (2)
, One input of NAND3 becomes “L” level,
Internal RAS bar signal a is reset to "H" level (timing t2). Here, the internal RAS bar signal a
Is to perform the same operation as when the external RAS bar signal is reset.

That is, a reset operation such as lowering the potential of the word line is performed regardless of the external RAS signal. As a result, the potential of the word line drops to the “L” level, and the writing to the memory cell ends. Thereafter, the external RAS bar signal is set to the “H” level and reset (at timing t).
3).

In the operation described above, tRW seen from an external signal
L is (t3−t1), but in a substantial operation, the internal R
TRWL becomes (t2-t1) by the AS bar signal a.

The measuring apparatus for measuring a device defines the minimum timing of the input between each signal, and the above-mentioned t
Also when measuring RWL, the minimum input timing of each of WE ↓ to RAS そ れ ぞ れ is determined by the measuring device. T shorter than t3-t1 determined by the device
When it is desired to test the operation of the DRAM by RWL, the test can be performed by operating the circuit of the present invention.

The tRWL timing (t2-t1) of the DRAM to be measured can be made variable by adjusting the delay width by Delay1 (2).

As a second embodiment of the present invention, DRA
M for the precharge time tRP (RAS # to RAS)
↓) The case of testing the timing will be described.
Referring to FIG. 3 which shows a circuit diagram applied when testing the precharge time tRP, this circuit includes an NA which inputs an external RAS bar signal from one external terminal to one input terminal.
ND6 and Delay to delay external RAS bar signal
y2 (4), an output terminal of this Delay2 (4) is connected, and the output terminal is composed of an inverter 5 connected to the other input terminal of the NAND 6, and an inverter 7 connected to the output terminal of the NAND6. Then, the internal RAS bar signal b is extracted from the output terminal (b) of the inverter 7.

That is, the internal R output from the output terminal b
The AS bar signal b is formed from only the external RAS bar signal, and has a logic in which the internal RAS bar signal is at the b "H" level for a shorter period than the external RAS bar signal.

Referring to FIG. 4 showing an operation waveform diagram of the precharge time tRP, the internal RA of the output terminal b of the inverter 7 is changed according to the rising timing of the external RAS bar signal.
The S bar signal b is reset. Then Delay2
(4) and the internal RAS bar signal b via the inverter 5
Attains the "L" level again, and becomes active.

In this operation, the tRP operation is performed using the internal delay without waiting for the next "L" level when the external RAS bar signal changes. Substantial tRP at that time
The time is represented by (t5-t4).

Referring to FIG. 5 showing a third embodiment of the present invention, an inverter 8 for inputting an external RAS bar signal from an external terminal, a Delay 3 (9) for inputting a WE bar signal from an external terminal, Inverter 10 to which the output terminal of Delay 3 (9) is connected, and inverter 1
0 input terminal and the signal line of the test mode signal TM1 are connected to the two-input NAND11, and the two-input NAND1
1 and the two-input NAND 12 whose output terminal is connected to the input terminal of the inverter 8 respectively.
From the output terminal d of the input NAND 12 to the internal RAS bar signal d
Take out.

The tRWL test using the test mode signal TM1 will be described. This test mode signal TM
1 is set by a test program of the test apparatus. In the circuit example of FIG. 5, the time tRWL is always defined by the internal operation. Therefore, if the time tRWL is set internally at a strict tRWL timing, a loose tRW is generated by an external signal.
A problem arises when it is desired to operate at L timing.

In order to solve this problem, the present embodiment is operated only when a tRWL test is performed.
That is, this is an example of a circuit in which the present embodiment functions only in the test mode operation. In this circuit example, the test mode signal TM1 is used.

When performing a tRWL test using the circuit of this embodiment, the test mode is first entered, and the test mode signal TM1 is set to "H" level. At this time, the tRWL operation is performed by first external RAS which is an external input signal.
The bar signal is set to the “L” level (active). The polarity is inverted by the inverter 8 by this “L” level. At this time, since the WE signal is not yet activated and is in the "H" level state, the internal RA of the output terminal d of the NAND 12 is
The S-bar signal d is activated, and the potential of the word line rises to "H" level.

Thereafter, the WE signal, which is an external input signal, is set to the "L" level to start the write operation (timing t7).

After inputting the WE bar signal, delay 3
(9) The output of the NAND 11 goes to the “L” level via the inverter 10, and the output of the internal R
The AS bar signal d is reset to “H” level (timing t8). As mentioned above, here again the internal R
Resetting the AS bar signal d means performing the same operation as resetting the external RAS bar signal.

That is, the potential of the word line falls to "L" level regardless of the external RAS bar signal, and the writing to the memory cell ends. Thereafter, the external RAS bar signal is set to the "H" level to reset (timing t9).

In the above-described operation, tRW seen from an external signal
L is (t9−t7), but in a substantial operation, the internal R
The tRWL becomes (t8-t7) by the AS bar signal d.

In a normal operation not using the test mode, signal TM1 is at "L" level, and the potential at the output terminal of NAND11 attains "H" level.
The internal RAS bar signal d at the output terminal 1 operates only by the external RAS bar signal.

In the test using the present invention, the timing to be tested is adjusted by a delay in the device, and this delay usually has a process dependency during manufacturing. This may cause the delay width to fluctuate,
This means that the test cannot always be performed with the same value as the timing of the design value.

For example, in the case of confirming the operation at the specification value, even if the delay width according to the embodiment of the present invention is designed to have the same timing as the operation at the specification value, if the delay width is increased due to the process variation, the specification value is increased. Since the test is performed at a looser timing, the operation cannot be guaranteed.

Therefore, an example in which operation is guaranteed even when the delay width fluctuates when a test is performed using the present invention will be described as a fourth embodiment.

Referring to FIG. 7 showing a circuit diagram of the fourth embodiment, an SR flip-flop circuit for inputting an external RAS bar signal to a set terminal and one of the reset terminals of the SR flip-flop circuit are connected. An inverter 15 for inputting the WE bar signal, a delay element Delay4 (16) connected to the other reset terminal of the SR flip-flop circuit for inputting and delaying the WE bar signal, and an output terminal of the Delay4 (16). Inverter 17 and NAN having an output terminal connected to one input terminal and a TM1 signal input to the other input terminal.
D18 and an NAND 19 to which the output terminal g of the NAND 18 and the SR flip-flop circuit are connected.

Referring to FIG. 8, which shows an operation waveform diagram in this embodiment, the test mode signal TM1 is
The tRWL test according to the present invention is performed when M1 is at "H" level, and normal operation is performed when TM1 is at "L" level. First, the normal operation will be described.

In the normal operation without using the test mode, TM1 is at "L" level, and when the external RAS bar signal is at "L" level and activated, the output terminal g of the SR flip-flop circuit is at "L" level. The RAS bar signal e at the output terminal e of the NAND 19 to which the "H" level is input is always at the "L" level (active).

When the WE bar signal is set at "L" level while the external RAS bar signal is at "L" level, the inverter 1
5 is applied to the reset terminal of the SR flip-flop circuit, and the output of the other terminal of this reset terminal, Delay 4 (16), is still at the "H" level. And internal RAS
The "L" level state of the bar signal e is latched. That is, in this state, even if the external RAS bar signal is set to the "H" level, the internal RAS bar signal e does not become the "H" level (timing t10).

After the WE bar signal has been set to the "L" level, the output terminal f which has once attained the "L" level is applied to Delay4 (1
The signal again goes to the “H” level after a delay of 6). At this time, if the external RAS bar signal is at "H" level, the output terminal g becomes "L" level, and the internal RAS bar signal e at the output terminal e is output.
Becomes "H" level.

In this operation, the time from the falling timing of the WE bar signal to the “L” level to the rising timing of the internal RAS bar signal (WE ↓ to internal RAS ↑) is t12−t11 = delay4 + 3 inverters. .

On the other hand, referring to FIG. 9 showing operation waveforms in the test mode, the output of NAND 18 is set to “L” by the WE bar signal delayed by Delay 4 (16).
Level, and the internal RAS bar signal e at the output terminal e of the NAND 19 is reset (at timing t1).
5).

At this time, the time from the falling timing of the WE bar signal to the “L” level to the rising timing of the internal RAS bar signal e (WE ↓ to internal RAS ↑) is t15−t13 = delay4 (16) + inverter 3
It is a step.

When comparing the time WE ↓ to the internal RAS ↑ of tRWL in the test mode and in the normal operation,
Until the time of Delay 4 (16), the same delay element is used, so that it is completely the same. The time for the subsequent three stages of inverters is set in advance so as to be the same time or shorter in the test mode operation.

Although it is difficult to make the delays of completely different paths the same time, it is easy to design when the delay element is shared between the normal operation and the test mode as in this circuit example. With such a circuit configuration, even if the external signals WE ↓ to RAS 外部 are shortened during normal operation, the internal R
The AS bar signal does not become "H" level earlier than the test. Therefore, if there is no problem in the operation in the test mode, tRWL in the normal operation can be guaranteed.

Although a DRAM has been described as an embodiment of the present invention, the present invention is not limited to this, and it is apparent that the present invention can be applied to an operation test in which the timing between certain two signals is within a standard value.

[0065]

As described above, the semiconductor memory device of the present invention is capable of receiving a first external input signal (for example, an external RA signal) during a test.
By generating a test internal signal (for example, an internal RAS bar signal) having a smaller pulse width than this signal from the (S bar signal) and performing a desired operation in a pseudo manner using the test internal signal, the first external input Since there is a test time control means for shortening the test time by operating in a time shorter than the normal value without waiting for a signal timing change, the external RAS signal is determined from the fall timing of the WE signal determined by the test apparatus. Signal rising timing (t3-
When it is desired to test the operation at tRWL for a shorter time than t1), the test can be performed by applying the present invention.

The timing of tRWL to be measured, W
The rising timing (t2-t1) of the internal RAS bar signal from the falling timing of the E bar signal can be made variable by adjusting the delay width.

[Brief description of the drawings]

FIG. 1 is a circuit diagram in a case where a test is performed on tRWL as a first embodiment of the present invention.

FIG. 2 shows tRWL (W
FIG. 9 is a waveform diagram when a test is performed for E ↓ to RAS ↑).

FIG. 3 is a circuit diagram in a case where a tRP is tested as a second embodiment of the present invention.

FIG. 4 shows a second embodiment of the present invention, tRP (RA
FIG. 9 is a waveform diagram when a test is performed for S ↑ to RAS ↓).

FIG. 5 is a circuit diagram in a case where a test of tRWL is performed using a test mode signal as a third embodiment of the present invention.

FIG. 6 shows a third embodiment of the invention, tRWL (W
FIG. 9 is a waveform diagram when a test is performed using a test mode signal for E ↓ to RAS ↑).

FIG. 7 is a circuit diagram in a case where a test of tRWL is performed using a test mode signal as a fourth embodiment of the present invention.

FIG. 8 shows tRWL (W) in a normal operation state in which a test mode signal is set to “L” level as a fourth embodiment of the present invention.
FIG. 9 is a waveform diagram when E ↓ to RAS ↑) are tested.

FIG. 9 shows a test mode tRWL (W) in which a test mode signal is set to “H” level as a fourth embodiment of the present invention.
FIG. 9 is a waveform diagram when E ↓ to RAS ↑) are tested.

FIG. 10 shows tRWL (WE ↓ to RA) as one of the conventional examples.
It is a waveform diagram at the time of testing about S ^).

[Explanation of symbols]

1, 5, 7, 8, 10, 15, 17 Inverter 2 Delay 1 3, 6, 11, 12, 13, 14, 18, 19 NA
ND 4 Delay 2 9 Delay 3 16 Delay 4 a, b, d, e Internal RAS bar signal

Claims (11)

[Claims] A timing interval between a predetermined first external input signal change timing and a subsequently input predetermined second external input signal change timing is defined in advance as a predetermined value, and according to the predetermined value, In a semiconductor memory device in which various control signals are set to operate, a test internal signal having a pulse width smaller than that of the first external input signal is generated from the first external input signal during a test. Test time control means for shortening the test time by operating the circuit in a shorter time than the predetermined value without waiting for the timing change of the first external input signal by simulating a desired operation. A semiconductor memory device characterized by the above-mentioned. 2. The test time control means according to claim 1, wherein said first external input signal determines a start and activation of an operation inside a semiconductor memory device by a row address strobe (RA).
S) There is a write enable (WE) bar signal that is a bar signal and the second external input signal permits writing to a memory cell, and the write enable (WE) bar signal from the rising timing of the WE bar signal to the falling timing of the RAS bar signal. 2. The semiconductor memory device according to claim 1, wherein a test is performed by setting a timing interval from a rising timing of the WE bar signal to a falling timing of the test internal signal instead of a predetermined value. 3. The test time control means, wherein the first external input signal is a RAS bar signal,
2. The test according to claim 1, wherein the test is performed by setting a timing interval from a rising timing of the RAS bar signal to a falling timing of the internal signal for testing instead of the predetermined value from the rising timing to the falling timing of the S-bar signal. Semiconductor storage device. 4. The semiconductor memory device according to claim 1, wherein the RAS bar signal supplied to an internal circuit is operated by the test internal signal both during a test and during a normal operation. 5. The test time control means includes:
5. The semiconductor memory device according to claim 4, wherein said test internal signal is generated by a logical product of a bar signal and a signal obtained by delaying the RAS bar signal by a predetermined time and having a polarity inverted. 6. The test time control means according to claim 1, wherein
5. The semiconductor memory device according to claim 4, wherein said test internal signal is generated by a logical product of a polarity inversion signal of a bar signal and a signal obtained by delaying said WE bar signal by a predetermined time. 7. The test time control means outputs a logically inverted signal of a logical product of a signal obtained by delaying the WE signal by a predetermined time and a test signal set by a test program, and Further, the RA
3. The semiconductor memory device according to claim 2, wherein a logical product of the S bar signal and a polarity inversion signal is obtained, and the test internal signal is generated by the logical product. 8. The test time control means, wherein
A set-side output signal of an SR flip-flop circuit, which inputs a bar signal to a set terminal, and inputs a polarity inversion signal of the WE bar signal and a signal obtained by delaying the WE bar signal by a predetermined time to a reset terminal; A signal obtained by ANDing a signal obtained by inverting the polarity of a signal obtained by delaying the WE bar signal by a predetermined time and a test signal set by a test program,
3. The semiconductor memory device according to claim 2, wherein a logical product is further obtained, and said test internal signal is generated by said logical product. 9. The semiconductor memory device according to claim 5, wherein a delay amount of a signal obtained by delaying the WE bar signal by a predetermined time is variable. 10. The semiconductor memory device according to claim 7, wherein said RAS bar signal supplied to an internal circuit is operated by said test internal signal only during a test. 11. The time from a change timing of a signal obtained by delaying the WE bar signal by a predetermined time to a rise change timing of the internal signal for test is a signal path time in a normal operation and a signal path in a test. By setting the size of the transistor in advance so that the time of the signal path is equal to or shorter than the time of the signal path at the time of the test, even if the delay amount fluctuates due to the process condition fluctuation at the time of manufacture, the predetermined value is obtained. 9. The semiconductor memory device according to claim 8, which operates so as to satisfy the following.