JP2000019484A - Liquid crystal display device and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a write insufficiency and to improve the image display quality by making the horizontal write time of a gate shorter than heretofore concerning scanning lines not inverted in polarity and utilizing the resulted excess time and blanking period for extension of the write time of a highlighting drive at the time of polarity inversion. SOLUTION: The excess time α per frame is obtd. by making the write time Tgate-on of respective lines shorter than heretofore (a). Namely, the excess time α is added to the perpendicular blanking period B. The perpendicular blanking period B and the excess time α are used for extension of the write time Tgate-on/reverse at the time of the polarity inversion (b). Namely, the write time Tgate-on is made shorter and is added as the additional time α to the write time at the time of the polarity inversion, by which the response time τON, OFF<Tgate-on in liquid crystals is embodied and the write time insufficiency at the time of the polarity inversion is eliminated. Further, the shortening of a polarity inversion period Treverse, i.e., an increase of polarity inversion times is made possible (c).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of driving the same, and more particularly, to a liquid crystal display device having a large spontaneous polarization, which eliminates insufficient writing at the time of polarity reversal of pseudo DC drive. The present invention relates to an apparatus and a driving method thereof.

[0002]

2. Description of the Related Art Smectic liquid crystal materials having large spontaneous polarization, such as ferroelectric liquid crystals and antiferroelectric liquid crystals, have features such as high-speed response and a wide viewing angle in a surface-stabilized (SS) display mode. Therefore, it is expected as a material for a next-generation liquid crystal display device.

In particular, in recent years, an application to a moving image display in combination with an active matrix driving method has been attempted. In this case, AC driving, which is one of the driving methods performed in a symmetrical arrangement, is effective from the viewpoint of preventing image sticking.

FIG. 19 is an explanatory diagram showing a comparison between the symmetric drive (A) of the liquid crystal and the asymmetric drive (B). In the figure, P indicates the polarization direction of the polarizing plate, whereas L1 and L2 indicate the behavior of molecules when driving the liquid crystal.

[0005]

However, when a liquid crystal material having such a large spontaneous polarization is employed, the image display characteristics are greatly affected by the writing time. On the other hand, the writing time tends to be shortened in accordance with the recent trend of increasing the size and definition of the display. Here, when the response time τ _{ON, OFF} of the liquid crystal is compared with the write time T _gate-on for the liquid crystal, under the condition that τ _{ON, OFF} > T _gate-on (1), one write operation In addition, writing to the final potential is not performed, and a deviation from target luminance due to insufficient writing is becoming remarkable.

As a driving method for solving this problem, a so-called pseudo DC driving method as disclosed in Japanese Patent Application Laid-Open No. Hei 10-133176 has been proposed. This is shown in FIG.
Is a driving method in which a plurality of continuous frames are written with the same polarity in a symmetrical arrangement as shown in (1), and there is an advantage that sufficient luminance can be obtained as compared with AC driving.

FIG. 20 is a waveform diagram showing the difference between AC drive and pseudo DC drive. FIG. 20A shows a drive signal V _sig , a write gate signal V _gate , and an optical response Tr during AC drive.
FIG. 2B shows a drive signal V _sig , a write gate signal V _gate , and an optical response Tr during pseudo DC driving, respectively.

In the pseudo DC drive, as shown in FIG. 20, by reversing the polarity at an appropriate inversion cycle T _reverse , the problem of burn-in which has been a problem in the case of complete DC drive is avoided. be able to.

However, in this driving method, it is required to suppress the change in luminance, that is, the difference in luminance to 1% or less, in writing at the time of polarity inversion. That is, it is necessary to almost completely secure the final potential at one time in writing at the time of polarity inversion.

In order to improve the write response at the time of polarity reversal, a method utilizing the applied voltage dependence of the response characteristics of the liquid crystal material can be considered.

FIG. 21 is a characteristic diagram showing the applied voltage dependency of the rising response characteristic of the liquid crystal material. As can be seen from the figure, the higher the applied voltage, the shorter τ _ON . In other words, by supplying a write charge amount required for a predetermined liquid crystal cell to reach the final potential at a high voltage, it is possible to charge to a desired charge amount in a short time. This is disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 10-133176.

On the other hand, as another method of suppressing a luminance change at the time of polarity inversion, a “blanking (return blanking) period” included in a video signal supplied to a liquid crystal display device is used.
It is also conceivable to use. Here, the "blanking period" refers to a time for cutting off the electron beam when the electron beam completes one sweep and returns to the next starting point in the image pickup tube of a CRT or a television camera. In a normal video signal, a “horizontal blanking period” is always provided after a “horizontal scanning period” corresponding to one horizontal scan. Also, a “vertical blanking period” is provided in which the electron beam returns from the lower right to the upper left of the screen after one “frame scan”. In the present specification, a time corresponding to one frame scan is referred to as a “frame scan period”. That is, in a normal video signal, a “vertical blanking period” is provided between the “frame scanning period” and the next “frame scanning period”.
Is assumed to be included.

The "vertical blanking period" of these
, And the write time T is used only when the polarity is inverted.
_{Gate-on / reverse} can be extended.

FIG. 22 is a timing chart of gate pulses for describing a driving method using the vertical blanking period B. That is, this figure shows the waveforms of the write gate signals T _gate-on and T _{gate-on / reverse} of the (n−1) th to (n + 1) th lines and the Nth line, respectively. Here, a case where the polarity is inverted on the n-th line and the write gate signal T _{gate-on / reverse} is supplied is shown.

FIG. 2A shows a blanking period B
FIG. 4B shows the case where the blanking period B is not used.
Represents a gate pulse in the case of using.

In general, in the driving method of the liquid crystal display device, the "horizontal blanking period" is allotted to the writing time T _gate-on of the _gate corresponding to the horizontal line. That is, in adjacent lines, the gate pulse is supplied so as to rise successively in time. And
Conventionally, as shown in FIG. 1A, a “vertical blanking period B” is provided when one frame scan, that is, a scan up to N lines is completed.

On the other hand, according to FIG. 22B, the “vertical blanking period B” is added to the n-th line write period T _{gate-on / reverse} with the polarity inverted.
That is, the following relationship holds: T _{gate-on / reverse} = T _gate-on + B (2) As described above, at the time of polarity inversion, the writing time T for the blanking period B is used.
By extending the _{gate-on / reverse} , the liquid crystal cell may be able to be charged to a level close to the final potential.
However, as a result of a detailed study by the present inventor, only the extension of the writing time using the blanking period B requires the relationship shown in Expression (1), that is, the condition that the writing time is longer than the response time. It turns out that there are cases where we cannot be satisfied. For example, when the temperature of the liquid crystal decreases and the response speed of the liquid crystal material itself decreases, the writing time extension of about the blanking time B is not necessarily sufficient in writing at the time of polarity inversion. Further, from the viewpoint of the reliability of the liquid crystal material, it is preferable that the polarity reversal period (T _reverse ) be short from the viewpoint of preventing image sticking.

Meanwhile, these and in contrast, significantly improving the response of recent liquid crystal material, the response at the time of writing other than the polarity inversion has been reached a sufficient level, writing time T _Gate-on Also tend to have room.

Further, a ferroelectric and antiferroelectric liquid crystal material having spontaneous polarization is a common TN (Twisted Nemati).
c) Since the equivalent dielectric constant, that is, the capacitance, is larger than that of the liquid crystal, once the potential reaches the final potential, the pixel potential is less likely to be lower than that of the TN liquid crystal. Therefore, as compared with a normal TN liquid crystal, even if the refresh rate of a display image (operation of writing a display signal voltage to a pixel) is thinned, the display image is less likely to deteriorate due to a decrease in pixel potential.

The present invention has been made based on the recognition of such problems and technical background. That is, the purpose is to improve the image display quality and reliability by eliminating insufficient writing during polarity reversal of the pseudo DC driving method in a liquid crystal display device using a liquid crystal material having a large spontaneous polarization. Liquid crystal display device and a driving method thereof.

[0021]

That is, the liquid crystal display device of the present invention supplies a plurality of scanning lines and a plurality of video signal lines arranged in a matrix and a write signal to each of the plurality of scanning lines. Scanning line driving means, and video signal line driving means for supplying a video signal to each of the plurality of video signal lines, and inputting a video signal in which a frame scanning period and a vertical blanking period are alternately provided. A video signal line driving unit that inverts the polarity of a video signal supplied to the video signal line for each of a plurality of frames for each of the plurality of scanning lines. The scanning line driving means, except when the polarity of the video signal is inverted,
A write signal having a first pulse width shorter than a time obtained by dividing the frame scanning period by the number of the scanning lines is supplied, and when the polarity of the video signal is inverted, the vertical blanking period and the shortening are reduced. And using a surplus time generated by the method to supply a write signal having a second pulse width that is longer than the first pulse width. In addition, the extra time and the vertical blanking time obtained by shortening the time are added to the write pulse at the time of polarity inversion, thereby realizing high-quality image display and having high reliability.

On the other hand, according to the method of driving a liquid crystal display device of the present invention, a write signal is supplied to the scanning lines of a liquid crystal display device having a plurality of scanning lines and a plurality of video signal lines wired in a matrix. A method for driving a liquid crystal display device that displays an image by supplying a video signal to a video signal line, comprising: inputting a video signal in which a frame scanning period and a vertical blanking period are alternately provided; For each of the lines, the polarity of the video signal supplied to the video signal line is supplied for each of a plurality of frames with the polarity inverted, and except when the polarity of the video signal is reversed, the pulse width of the write signal is equal to the frame width. This is a first time that is shorter than the time obtained by dividing the scanning period by the number of the scanning lines, and when the polarity of the video signal is inverted, the pulse width of the write signal is Characterized in that the second time is extended than straight blanking period and the shorter the first surplus time and the first time using the resulting,
By adding the extra time and the vertical blanking time obtained by shortening the writing time compared to the conventional method to the writing pulse at the time of polarity inversion, high quality image display is realized and high reliability is also realized. be able to.

Further, the supply of the write signal to the scanning line is deleted when the video signal to be supplied for the scanning line is the same as that of the previous frame, and the second signal generated by the deletion is deleted. Utilizing surplus time, characterized by further extending the pulse width of the write signal when the polarity of the video signal is inverted, by rewriting only a portion that moves between frames,
Further, a surplus time is obtained and added to a write pulse at the time of polarity inversion, thereby realizing high-quality image display and realizing high reliability.

Further, the temperature of the liquid crystal display device is detected, and when the temperature decreases, the degree of shortening is increased or eliminated to increase the degree of extension of the pulse width. High image quality can be maintained in response to a decrease in responsiveness when the image quality decreases.

[0025] Further, it is characterized in that it is determined whether or not to delete based on a signal relating to the motion of the image included in the video signal or information relating to the motion of the image supplied together with the video signal. By using information such as a motion vector to be rewritten, it is possible to efficiently detect a portion requiring rewriting and obtain extra time.

Here, the present invention is suitably applied to a liquid crystal display device having a liquid crystal material having spontaneous polarization. Furthermore, for example, even when the impedance of the driving circuit is high and the response speed including the driving circuit is not sufficient, high-quality image display can be maintained.

In the present invention, the liquid crystal material having spontaneous polarization is preferably a mixture having a structure represented by the following general formula.

[0028]

Embedded image However, in the above formula, C ^* is an asymmetric carbon atom, R is an alkyl group having 1 to 20 carbon atoms, R 'is an alkyl group having 1 to 10 carbon atoms, l, m, n, and o are each 0 or 1. Is an integer,

[0029]

Embedded image Represents a benzene ring, a cyclohexane ring, a bicyclooctane ring, a pyrimidine ring or a dioxane ring, or any one of these substituents. X ₁ , X ₂ ,
And X ₃ are a single bond, —CH ₂ —, —COO—, —OCO
-, - CH = N -, - N = CH-, azo group, azoxy group, -CH = CH -, - CH 2 CH 2 -, - CH 2 O-,
Or —OCH ₂ —. Further, Y _{is, -CH 3 -, - CF 3} -, or represents a halogen element.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, the horizontal writing time T _gate of the gate for the scanning line whose polarity is not inverted is reduced as compared with the conventional case, and the surplus time obtained by this reduction and the blanking period are used when the polarity is inverted. It is used to extend the writing time of the highlight drive.

Further, by utilizing the surplus time obtained by this reduction, the polarity inversion cycle can be shortened, that is, the number of polarity inversions can be increased.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a timing chart for conceptually explaining the drive timing of the liquid crystal display device of the present invention. That is, FIGS.
_Are write gate signals T _gate-on , T _gate-on , T _gate- n and (n + 1) -th and (N + 1) -th
_It shows _{gate-on / reverse} . Here, the polarity is inverted on the n-th line, and the write gate signal T
_{gate-on / reverse} is applied. Also, FIG.
Are the (n-1) th to (n + 1) th lines and the ｛(n + (1)
/ 2) N) -1} to {(n + (1/2) N) +1} line, Nth line, write gate signals T _gate-on and T
_{Gate-on / reverse} is shown. Here, the write gate signal T _{gate-on / reverse} at the time of polarity inversion is applied to the n-th line and the n + (1/2) N-th line.

FIG. 1A shows that a surplus time α per frame can be obtained by reducing the write time T _gate-on of each line as compared with the conventional case. That is, FIG. 7A shows the vertical blanking period B
This conceptually shows that the surplus time α has been added.
In FIG. 3B, the vertical blanking period B and the surplus time α correspond to the write time T at the time of polarity inversion.
Indicates that it is used for _{gate-on / reverse} expansion. That is, the write time T _gate-on is reduced, and the reduced time is added to the write time at the time of polarity inversion by the additional time α.
As a result, τ _{ON, OFF} <T _{gate-on / reverse} (3) is realized, and insufficient writing at the time of polarity inversion is eliminated.
In this way, by extending the write time at the time of polarity inversion, the liquid crystal cell in that line can be sufficiently charged to a predetermined potential to eliminate the deviation from the target luminance.

Further, according to the present invention, as shown in FIG. 1C, the polarity inversion period T _reverse can be shortened, that is, the number of polarity inversions can be increased. That is, the surplus time α
And the vertical blanking period B, it is possible to improve the reliability of the liquid crystal display device by increasing the number of polarity inversions while sufficiently securing the write time T _{gate-on / reverse} at the time of polarity inversion. . Here, FIG. 1C shows, as an example, a case where the number of polarity inversions is doubled and each writing time is extended by (α + B) / 2.

Next, the driving timing of the liquid crystal display device according to the present invention will be described more quantitatively. First,
In the driving timing of the conventional liquid crystal display device, the gate pulse width of each scanning line, that is, the writing time T _gate-on
Is represented by the following equation. T _gate-on = (1 / f _AC −B) × 1 / N (4) Here, f _AC is a driving frequency (Hz) at the time of AC driving, B is a vertical blanking period (second), and N is a scanning line. Number, T
_gate-on represents the writing time (second). In addition,
Equation (3) corresponds to a case where interlace driving is not performed. In case of interlaced drive,
In the equation (3), N may be set to half of the number of scanning lines. From the equation (3), it can be seen that in the conventional driving method, the time obtained by subtracting the vertical blanking time from the required time of one frame and dividing by the number of scanning lines is set as the writing time of each scanning line. .

This driving method is described in, for example, "VESA MO
DE (Video Electronics Standards Association MO
This is a case where normal driving is performed using a video signal standard called “DE)”. FIG. 2 illustrates the write time T _gate-on conventionally used based on the equation (3).
That is, in FIG.
The driving frequency and the writing time are illustrated.

On the other hand, in the present invention, the write time T _gate-on is reduced. This can be expressed by the following equation using the coefficient x. T ′ _gate-on = T _gate-on × x (5) where T ′ _gate-on is the write time (second) after shortening,
x is a coefficient (0 <x ≦
1). As a result of reducing the writing time for each line, a surplus time α per frame is obtained. This can be expressed by the following equation using the parameters of equations (4) and (5). α = {T _gate-on × (1-x)} × N (6) In the equation (6), when interlaced driving is performed, a value of half the number of scanning lines may be used as N. .

When the surplus time α and the vertical blanking period B obtained as described above are added to the writing of the scanning line whose polarity is inverted, the writing time T _{gate-on / reverse is obtained.}
Can be expressed by the following equation. T _{gate-on / reverse} = T ' _gate-on + (B + α) × T _reverse × f _AC / (2 × N) (7) Here, T _reverse represents a polarity inversion cycle (second).

As explained quantitatively above, according to the present invention, whereas the coefficient x = 1 in the past, 0 <x <
1 to obtain a surplus time α, and the surplus time α
By adding the vertical blanking time B and the vertical blanking time B to the write time of the line whose polarity is inverted, display unevenness can be eliminated. Further, the coefficient x is 0.7 from the viewpoint that the write time required for writing at the time of non-polarity inversion is maintained and the time required for writing at the time of polarity inversion is sufficiently obtained.
It is more preferable to set the range of <x <1.

Next, a specific example of this embodiment will be described below in comparison with a comparative example based on a conventional configuration. Comparative Example 1 Thresholdless Antiferroelectric Material Liquid Crystal MLCO
XGA-L filled with 076 (manufactured by Mitsui Petrochemical Industries, Ltd.)
A CD panel (number of pixels: 1024 × 768) was prototyped.
The driving frequency f _AC was set to 60 Hz. FIG.
According to the normal driving method, as shown in FIG.
Based on the MODE standard, the write time T _gate-on is
Inevitably about 21 microseconds. In addition, the polarity reversal period T _reverse is set to 1 second, and as the display drive signal V _sig ,
± 5 V was applied.

FIG. 3A is a timing chart showing a driving waveform of this comparative example. In FIG.
Represents the optical response characteristic of one pixel arbitrarily selected, and is a value obtained by measuring the transmitted light intensity of the pixel at room temperature by a measurement system using a photodetector and an oscilloscope.

In the figure, it can be seen that the polarity is inverted near the center, and the drive signal V _sig is turned to the minus side. Here, looking at the light transmittance Tr immediately after the polarity reversal, the first few writings do not sufficiently rise, and the writing is performed five times, that is, five frames, until the luminance difference converges within several% of the steady value. It turns out that it requires. When the display panel of the liquid crystal display device was actually observed with the naked eye, a line-shaped lack of luminance parallel to the scanning line direction corresponding to the scanning line whose polarity was inverted was seen within four frames outside. Comparative Example 2 Thresholdless Antiferroelectric Material Liquid Crystal MLCO
XGA-L filled with 076 (manufactured by Mitsui Petrochemical Industries, Ltd.)
A CD panel (number of pixels: 1024 × 768) was prototyped.
The driving frequency f _AC was set to 60 Hz. That is, as can be seen from FIG. 2, the conventional VESA MODE
The write time T _gate-on based on the standard is about 21 microseconds. The polarity reversal period T _reverse is 1 second,
± 5 V was applied as the display drive signal V _sig .

Further, in this comparative example, the write time at the time of polarity inversion was extended to about 420 microseconds using the vertical blanking time B (about 790 microseconds). This derivation is based on equations (3) to (6) (x = 1, α = 0
). Further, in this comparative example, the signal voltage V _sig at the time of polarity inversion was increased to ± 7 V in synchronization with writing at the time of polarity inversion.

FIG. 3B is a conceptual diagram showing the drive timing and optical characteristics of this comparative example. As can be seen from the figure, it takes about three frames for the light transmittance Tr to converge to a luminance difference of several% of the steady value. That is, the rise is shorter in comparison with Comparative Example 1 described above. However, in the two frames immediately after the polarity reversal, the transmittance has not sufficiently risen, and even if the panel of the liquid crystal display device is observed with the naked eye, it corresponds to the scanning line in which the polarity has been reversed within the other two frames. Insufficient luminance was observed in a line parallel to the scanning line direction.

Example 1 An XGA-LCD panel filled with a thresholdless anti-ferroelectric material liquid crystal MLC0076 (manufactured by Mitsui Petrochemical Industries, Ltd.) (number of pixels: 1024 × 768)
Was prototyped. Further, the frequency f _AC was set to 60 Hz.
Here, in the normal driving using the conventional VESA MODE standard, the write time T _gate-on is about 21 microseconds, but in the present embodiment, it is reduced to 19 microseconds. Further, the polarity inversion period T _reverse was set to 1 second, and ± 5 V was applied as the display drive signal V _sig .

In this embodiment, in addition to the original blanking time B (about 790 microseconds), the write time T
By reducing the _gate-on , a surplus time of α = 1280 microseconds occurred. Combining these, (4)-
According to the equation (7), the writing time at the time of polarity reversal was extended from 19 microseconds to 100 microseconds. Further, the signal voltage V at the time of polarity inversion is synchronized with the writing at the time of polarity inversion.
_sig was set to ± 7V.

FIG. 3C is a conceptual diagram showing the drive timing and optical characteristics of this comparative example. According to the present embodiment,
As is clear from the figure, in one frame immediately after the polarity inversion, the light transmittance rises to a luminance difference within several% of the steady value. Also, when the liquid crystal display panel was observed with the naked eye,
It was confirmed that the lack of linear luminance parallel to the scanning line direction observed in Comparative Examples 1 and 2 described above disappeared, and an extremely high-quality display was obtained. Example 2 Thresholdless Antiferroelectric Material Liquid Crystal MLCO
XGA-L filled with 076 (manufactured by Mitsui Petrochemical Industries, Ltd.)
A CD panel (number of pixels: 1024 × 768) was prototyped.
Also, the drive frequency f _AC is set to 60 Hz, and the conventional VE
In the normal drive using the SA MODE standard, the point where the write time T _gate-on necessarily becomes 21 microseconds is set to 18 microseconds. Further, in order to enhance the reliability of the liquid crystal display device, the polarity reversal period T _{reverse is set} to 0.5.
Set to seconds. ± 5 V was applied as the display drive signal V _sig .

According to this embodiment, in addition to the original blanking time B (about 790 microseconds), the write time T
By reducing the _gate-on , a surplus time of α = 2050 microseconds was obtained. Combining these, (4)-
According to the equation (7), the writing time at the time of polarity reversal was extended from 18 microseconds to 58 microseconds. Further, the signal voltage V _sig at the time of polarity inversion is synchronized with the writing at the time of polarity inversion.
Was set to ± 7V.

FIG. 3D is a conceptual diagram showing the drive timing and optical characteristics of this comparative example. According to the present embodiment,
As is clear from the figure, in one frame immediately after the polarity inversion, the light transmittance rises to a luminance difference within several% of the steady value. Also, when the liquid crystal display panel was observed with the naked eye,
It was confirmed that the lack of linear luminance parallel to the scanning line direction observed in Comparative Examples 1 and 2 described above disappeared, and an extremely high-quality display was obtained.

Further, in this embodiment, the reliability of the liquid crystal display device can be improved by setting the polarity inversion cycle to 0.5 seconds.

Next, a second embodiment of the present invention will be described. In the present embodiment, a change in the display image is checked for each frame, and writing is omitted for a line having no change, thereby generating extra time, and adding this extra time to the writing time immediately after the polarity inversion. And
Alternatively, by increasing the number of times of polarity inversion, higher quality image display is realized.

FIG. 4 is a schematic block diagram of a liquid crystal display according to a second embodiment of the present invention. As shown in FIG. 1, an X driver 2 and a Y driver 5 are connected to the liquid crystal panel 1, and drive display of liquid crystal cells arranged in a matrix.

The X driver 2 and the Y driver 5 receive the X driver driving signal 3 from the driver control circuit 6 respectively.
And a Y driver drive signal 4 are supplied. The X driver 2 is supplied with a polarity control signal 15 from the polarity inversion control circuit 8 to control the polarity inversion in the pseudo DC drive.

The frame memory 11 has an input display signal 12 (Si) which is an image signal to be displayed on the liquid crystal panel 1.
g. ) Is delayed by one frame to output a one-frame delay display signal 17.

The motion detecting circuit 9 receives the input display signal 12 and
The display signal generated by the built-in frame memory is compared with the display signal delayed by one frame, the movement of the display image is checked, and the scanning line in which there is no movement, that is, the scanning line in which the signal has not changed in one frame, is detected. The resulting motion detection result signal 13 is output to the scanning time reduction control circuit 10. Based on the motion detection result signal 13 from the motion detection circuit 9, the scanning time reduction control circuit 10 calculates a scanning line to be inverted in polarity and a scanning line to be skipped without writing to the liquid crystal panel 1. Is output to the polarity inversion control circuit 8.

The polarity inversion control circuit 8 uses the polarity control signal 15 and the scan control signal corresponding to the interlaced scanning and the long-time driving at the time of polarity inversion in accordance with the interlaced scanning calculation result signal 14 from the scanning time reduction control circuit 10. A certain mask signal 16 is output, and the polarity control signal 15 is output by the X driver 2
The mask signal 16 is supplied to the synchronization control circuit 7.

The synchronization control circuit 7, which is supplied with the one-frame delay display signal 17 from the frame memory 11 and the mask signal 16 from the polarity inversion control circuit 8, performs timing scanning such as delay and adjusts the timing. The rear display signal 20 is output to the driver control circuit 6.

Through the configuration described above, the driver control circuit 6 controls the X driver driving signal 3 which is a driving pulse from the display signal 20 after timing adjustment to the X driver 2 and the Y driver which is a driving pulse to the Y driver 5. The drive signal 4 is output, and is driven by the X driver 2 and the Y driver 5 to write an image on the liquid crystal panel 1.

As a result, an image is displayed on the liquid crystal panel 1 based on the input display signal 12.

FIG. 5 is a circuit block diagram showing a configuration example of the motion detection circuit 9. FIG. 6 is a conceptual diagram illustrating the operation of the motion detection circuit 9. First, the operation of the present circuit will be described with reference to FIG.

FIG. 6 conceptually shows the screen of the f-th frame and the screen of the (f + 1) -th frame. Here, each screen is a ball A on the same background.
Illustrates a state in which is moving. In such a case, in the (f + 1) -th frame, only the ball portion needs to rewrite the image. In the example shown in the figure, the range from the l-th line to the (l + a) -th line only needs to be rewritten. Therefore, the time for writing other lines can be used as surplus time. By adding the surplus time to the writing time of the line whose polarity is inverted, the potential of the liquid crystal cell can be completely raised, and an image of extremely high quality can be displayed.

Next, a configuration example of the motion detection circuit 9 will be described with reference to FIG. As shown in the figure, the input display signal 12 is delayed by one frame in the motion detection frame memory 91 and output to the subtracter 92.

The subtracter 92 compares the delayed input display signal 12 from the motion detection frame memory 91 with the input display signal 12 before being delayed by subtraction processing. In other words, in a region where the subtraction result is zero, a signal having a difference of zero is output, and in a region where the subtraction result is other than zero,
The absolute value of the signal difference is output. In other words, the part where the difference is zero indicates that there was no motion between frames,
A portion other than the difference of zero indicates that there has been movement between frames.

The difference signal from the subtractor 92 is input to the accumulator 93 and is accumulated for each scanning line. The accumulator 93 clears the accumulated value for each scanning line based on the horizontal synchronization signal _Hsync . That is, looking at each scanning line, if there is a movement between frames, the cumulative value of the difference in the accumulator 93 takes a value other than zero, and if there is no movement between the frames, Adder 93
The accumulated value of the difference at is zero.

The output of the accumulator 93 is latched by the latch circuit 94 for each horizontal scan based on the horizontal synchronization signal _Hsync , and is output to the scanning time reduction control circuit 10 as the motion detection result signal 13.

In this embodiment, the motion detection frame memory 9 is used.
Although this is an example of a configuration using the frame memory 11 for one frame and one frame delay, a configuration using both memories in common, for example, a configuration for performing motion detection using the display signal output of the one frame delay memory 11 is also possible. good.

FIG. 7 is a circuit block diagram showing a configuration example of the scanning time reduction control circuit 10.

As shown in the figure, the motion detection result signal 13 input to the scanning time reduction control circuit 10 is input to the microprocessor 101, and the motion detection result for one frame is stored.

The microprocessor 101 calculates the number of polarity inversion lines and the polarity inversion scanning lines based on an algorithm described later, and intercepts the polarity inversion control signal and the synchronization control signal via the output IO circuits 102 and 103. It is output as a scan calculation result signal 14.

FIG. 8 is a flowchart showing the operation of the microprocessor 101. As shown in the figure, normally, the microprocessor 101 has stopped its operation and is in the wait state of step S1.

When the horizontal synchronizing signal _Hsync is input here, an interrupt occurs, and the operation is started to perform the operation from step S2.

In step S2, it is determined whether or not the state at the time of the interruption is the vertical blanking period. If the state is not the vertical blanking period, it is the effective scanning period. The motion detection result signal 13 from the motion detection circuit 9 corresponding to the horizontal scanning period is stored in the memory, and the process returns to step S1 to enter the wait state again.

On the other hand, if it is determined in step S2 that the current period is the vertical blanking period, the process proceeds to step S2.
4 to load the motion detection result signal 13 stored in each horizontal scanning period up to that time.
The number of scanning lines that have moved between frames is counted.

In the following step S5, the counted value of the number of scanning lines with motion is compared with a predetermined specified number of scanning lines with motion.

Based on the result of this comparison, step S6
If it is determined that the amount is less than the specified amount, the process proceeds to step S7, the polarity inversion scanning line number is kept normal, and only one scanning line is set. , The number of polarity inversion scanning lines is increased according to the specified amount.

That is, when the number of scanning lines with movement is larger than the specified amount, the number of scanning lines in which the polarity of the display signal applied to the liquid crystal panel 1 is inverted is increased. For example, if the specified amount is 1
When the number of scanning lines with motion is 21 in 0 lines, in addition to the normal number of polarity inversion lines of 1 line,
The polarity inversion lines are set so that two lines are increased and a total of three lines are inverted.

The number of polarity inversion lines calculated and set as described above, and the polarity signal for each scanning line based on the motion detection result are processed in step S9, and the polarity inversion control signal and the synchronization control signal are processed. Is output as the interlaced scan calculation result signal 14 through the output IO circuits 102 and 103.

When the output of the interlaced scan calculation result signal 14 is completed through the above-described operation, this is determined in step S10, the process returns to the wait state of step S1, and the stop state is resumed. Wait for the result of motion detection of the display signal.

Incidentally, the interlaced scan calculation result signal 14
Are the polarity control data POLDATA and the switching signal PI
O, including address data ADRS. Here, the switching signal PIO is a signal for switching between writing from the microprocessor 101 to the polarity memory 82 and the mask memory 83 and normal reading.

FIG. 9 is a circuit block diagram showing a configuration example of the polarity inversion control circuit 8.

As shown in the figure, the interlaced scan calculation result signal 14 from the scan time reduction control circuit 10 is input through the signal input circuit 81.

The polarity inversion control circuit 8 applies a mask to the polarity signal 82 for storing the polarity of each scanning line, and masks the synchronization signal when extending the driving time of the scanning line for performing the polarity inversion. And a mask memory 83 for stopping the scanning of the Y driver 5.

In the polarity memory 82 and the mask memory 83, the address data ADRS is written from the microprocessor 101 through the address switching circuit 84 controlled by the switching signal PIO. The count value from the counter 86 is given.

[0084] Incidentally, the scanning line number counter 86 has a function of counting up every horizontal synchronizing signal H _sync, is reset by the vertical synchronizing signal V _sync.

The polarity memory 82 and the mask memory 8
3 reads out the contents written by the microprocessor 101 in accordance with the scanning order of the scanning lines.

The polarity control signal 15 read from the polarity memory 82 via the memory output circuit 85 is input to the X driver 2 and controls the polarity of the display signal applied to the liquid crystal panel 1 from the X driver 2. Do.

The mask signal 16 read from the mask memory 83 via the memory output circuit 85 is input to the synchronization control circuit 7, and is used for adjusting the timing of the display signal and the synchronization signal.

FIG. 10 is a circuit block diagram showing a configuration example of the synchronization control circuit 7.

As shown in the figure, the one-frame delay display signal 17 from the frame memory 11 and the mask signal 16 from the polarity inversion control circuit 8 are input to the synchronization control circuit 7. The display signal in the one-frame delay display signal 17 is input to a FIFO (First In First Out) memory 18, and the synchronization signal is input to an OR circuit 19. on the other hand,
The mask signal 16 is input to a terminal for controlling the enable state of the FIFO memory 18 and an OR circuit 19.

In the above configuration, the mask signal 1
If 6 is low level, that is, if no masking is performed, the one-frame delay display signal 17 input to the FIFO memory 18 is immediately transmitted from the FIFO memory 18 and output as the display signal 20 after timing adjustment.
On the other hand, while the mask signal 16 is at the high level, that is, in a state where the mask is performed, the one-frame delay display signal 17 read into the FIFO memory 18 is restricted from being read. Then, when the mask based on the mask signal 16 is released, the reading is started again. That is, the one-frame delay display signal 17 is delayed by the FIFO memory 18 only while the mask signal 16 is at the high level.

The OR circuit 1 is activated by the mask signal 16.
9, the synchronization signal SYNC17 included in the one-frame delay display signal 17 is also masked to become SYNC20. Therefore, when the synchronization signal SYNC17 is masked, the driver control circuit 6
Since no synchronization signal is input to the driver, the driver control circuit 6 does not output a scanning signal.

That is, the synchronization control circuit 7 performs the delay of the display signal and the masking operation of the synchronization signal, and regulates the timing of the display signal and the synchronization signal while restricting the driver control circuit 6 from performing the scanning operation. Is performed. Therefore, in the scanning line to which the mask signal 16 is output, the display signal is delayed and the scanning of the liquid crystal panel 1 is stopped. Therefore, when the polarity of the display signal applied to the liquid crystal panel 1 is inverted,
When the mask signal is output, the writing time can be extended only during the period of the mask signal.

The above operation is as shown in the timing chart of FIG. In the figure, (a) is 1
The horizontal synchronization signal _Hsync in the frame delay display signal 17
(B) is a display signal in the one-frame delay display signal 17, and (n-1) to (n + 5) represent scanning line numbers. FIG. 3C shows the mask signal 16. FIG. 3D shows a horizontal synchronization signal in the display signal 20 after the timing adjustment, and FIG.
It is a display signal inside. It should be noted that (n) in FIG.
-1) to (n + 2) represent scanning line numbers.

As shown in FIG. 11, while the mask signal 16 is at the high level, the horizontal synchronization signal _Hsync is masked.
At the same time, the display signal is also masked.

As described above, the motion of the input display signal 12 is detected, the polarity of the display signal applied to the liquid crystal panel 1 is controlled based on the detection result, and the scanning time is controlled by the mask signal 16 to control the motion. The number of scanning lines for which the polarity is inverted can be made variable in accordance with the number of scanning lines without the mark.

In the above description, the Y driver 5
Although it is assumed that the driver is a progressive scan driver, in such a progressive scan, the interlaced scan lines that do not perform a write scan on the liquid crystal panel 1 are limited to display signals after the scan line that performs polarity inversion. This is because it is necessary to shift the shift register circuit inside the driver until the scan line at which the polarity is inverted is reached. If you turn it over,
By using the Y driver 5 which is not of the progressive scanning type, it is possible to eliminate the limitation of the skip scanning line.

FIG. 12 is a circuit block diagram showing an example of the configuration of the Y driver 5 that can arbitrarily perform scanning. As shown in the drawing, the Y driver drive signal 4 is input in parallel to a plurality of comparators 51 as a plurality of bits of address data. The comparator 51 matches the internal address with the input address data, and outputs a scan signal to a scan line corresponding to the matched portion. That is, the input address data is input to the comparator 51 provided for each output, and is output from the comparator 51 only when the address data matches, the amplified output is amplified to a predetermined potential and scanned. Signal.

FIG. 13 shows the Y driver 5 shown in FIG.
3 is a circuit block diagram illustrating a configuration example of a comparator 51 in FIG.

As shown in the figure, the comparison address generator 53 has a comparison address R corresponding to each scanning line.
ef is stored and input to the exclusive OR circuit 54 together with the Y driver drive signal 4. The exclusive OR circuit 54 associates the signals with each other, and if there is a match, outputs zero.

Therefore, if all bits match, the outputs of all exclusive OR circuits 54 become zero, and the output NOR circuit 52 outputs a high level output.

That is, the output from the output NOR circuit 52 becomes a coincidence output.

By using the Y driver 5 having the structure shown in FIGS. 12 and 13, the scanning order can be freely set. In this case, the scanning time reduction control circuit 10 switches the polarity inversion control circuit 8 and the synchronization control circuit 7
It is sufficient to output the scanning line address as it is to the synchronization control signal among the polarity signal and the synchronization control signal for each scanning line output to the scanning line. Therefore, it is possible to arbitrarily perform scanning and skip scanning lines without changing the basic configuration of the liquid crystal display device driving device shown in FIG. Next, a third embodiment of the present invention will be described. In the present embodiment, the temperature of the liquid crystal panel of the liquid crystal display device is monitored, and when the temperature decreases, the writing time immediately after the polarity inversion is set longer. In other words, depending on the temperature of the liquid crystal panel,
Switch the control mode.

FIG. 14 is a circuit block diagram illustrating the configuration of the liquid crystal display device according to the present embodiment. As shown in the figure, a temperature sensor 105 for detecting the temperature is attached to the liquid crystal panel 1, and a thermocouple signal 104 as an output thereof is input to the scanning time reduction control circuit 10. I have. As the temperature sensor 105, a thermocouple, a thermistor, or other various sensors can be used.

In the present embodiment, by detecting the temperature of the liquid crystal panel 1 and supplying the detected temperature to the scanning time reduction control circuit 10, it is possible to skip the horizontal scanning lines and vary the amount of reduction in the horizontal scanning time. it can.

FIG. 15 is a circuit block diagram showing a configuration example applied to the scanning time reduction control circuit 10 of this embodiment. As shown in the figure, the temperature sensor signal 104 from the polarity control signal 15 is given a change in resistance or the like as a voltage value to the AD converter 106 in an appropriately biased state. The voltage value given to the AD converter 106 is converted into a digital signal,
01 is input.

Since the digitized voltage value corresponds to the temperature of the liquid crystal panel 1, the microprocessor 101 reduces the horizontal scanning time and skips scanning only when this value exceeds a predetermined value. And so on. That is, scanning time reduction control is performed based on the temperature of the liquid crystal panel 1.

FIG. 16 is a characteristic diagram showing an example of the relationship between the temperature and the response speed of a liquid crystal material having spontaneous polarization. As is clear from the figure, when the temperature of the liquid crystal is low, the response speed of the liquid crystal gradually decreases. Therefore, when such a material is used, the writing time at the time of polarity inversion needs to be prolonged in accordance with the deterioration of the response speed. That is, as the temperature decreases, x in Expression (5)
That is, it is necessary to reduce the coefficient indicating the degree of reduction in the writing time. In addition, when reducing the horizontal scanning time, skip the scanning line without motion, that is, change the specified amount in the case of detecting the scanning line with motion and change the writing time to redistribute to the scanning line for performing the polarity inversion. To increase.

As described above, according to the present embodiment, even when the temperature of the liquid crystal panel 1 decreases, it is possible to compensate for insufficient writing at the time of polarity inversion. Next, the fourth aspect of the present invention.
An embodiment will be described. In the present embodiment, the horizontal scanning time, that is, the writing time is created based on a control signal such as an externally applied command. This makes it possible to externally control the control mode of the liquid crystal.

FIG. 17 is a circuit block diagram showing a circuit example of the liquid crystal display device according to the present embodiment. As shown in the figure, in the present embodiment, an external command CMM is given to the scanning time reduction control circuit 10, and based on this, skip horizontal scanning lines and vary the amount of reduction in horizontal scanning time.

FIG. 18 is a circuit block diagram showing a configuration example applied to the scanning time reduction control circuit 10 of this embodiment. As shown in the figure, an external command CMM signal supplied to the scanning time reduction control circuit 10 through the command input line 107 is directly input to the microprocessor 101.

The microprocessor 101 changes its operation in accordance with the external command CMM, and reduces the horizontal scanning time and skips scanning in response to the external command CMM. Also, external command CM
By inputting a motion signal of a compressed image signal as M, it becomes possible to detect a moving scanning line without using the motion detection circuit 9. For example, MPEG (Moving Picture Experts Grou
In the p) method, a signal relating to a “motion vector” for a portion that moves for each frame is included in a video signal.
By using the signal related to this motion vector,
The same processing can be performed by detecting the motion for each frame without using the motion detection circuit 9 described above with reference to FIGS. Furthermore, animation coding, such as face animation coding, has been proposed as a next-generation image coding method. In this face animation coding, not only the movement of the face but also a FAP (Facial Animation Parameter) expressing the expression of the face is transmitted, and the receiving side undergoes deformation of the face screen based on the FAP. Therefore, in the case of a face animation encoding FAP, direct image motion information such as MPEG cannot be obtained. However, by decoding the FAP, image deformation, that is, motion information can be obtained, and the image changes. The detected position can be detected.

Also, in the case of face animation coding, since the decoding process of the image is complicated, the transmitted FA
By making the area around the object targeted by P a wider motion area, simple motion information, that is, position information of an area in which an image should be rewritten can be obtained. Based on the motion information thus obtained, a change in an image for each frame can be detected without using the motion detection circuit 9 described above with reference to FIGS. 5 and 6, and similar processing can be executed.

According to the present embodiment, the external command CMM
, Various parameters other than the temperature change can be given, the horizontal scanning line can be skipped, the horizontal scanning time can be reduced flexibly, and the circuit scale can be reduced. .

[0114]

The present invention is embodied in the form described above, and has the following effects.

First, according to the present invention, the write time of each scanning line is shortened as compared with the related art, and the obtained surplus time is added to the write time immediately after the polarity inversion together with the vertical blanking time, thereby obtaining the polarity inversion. Uneven display at the time can be eliminated.

Further, according to the present invention, the polarity inversion cycle can be increased by using the surplus time obtained in this manner as compared with the prior art, so that the burn-in of the liquid crystal cell is eliminated and the reliability of the liquid crystal display device is improved. Can be improved.

Further, according to the present invention, high quality and high reliability image display as described above can be realized by using a liquid crystal material having a large spontaneous polarization.

Further, according to the present invention, the writing time is extended not only in the physical properties of the liquid crystal material itself but also in a liquid crystal display device having a long response time constant, including peripheral driving circuits. Thereby, high-quality and highly reliable image display can be realized.

Further, according to the present invention, the driving conditions can be optimized by feeding back the temperature and various other control signals, so that the application range of the liquid crystal display device can be expanded more than before, and for example, It is possible to operate stably even in a low temperature environment.

As described in detail above, according to the present invention, a liquid crystal display with high display quality and high reliability can be realized, and the industrial advantage is great.

[Brief description of the drawings]

FIG. 1 is a timing chart conceptually illustrating drive timing in the present invention.

FIG. 2 is an explanatory diagram illustrating a writing time of a conventional liquid crystal panel.

FIG. 3 is a waveform chart for explaining the present invention and a comparative example.

FIG. 4 is a circuit block diagram illustrating a configuration example of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 5 is a circuit block diagram showing a configuration example of a motion detection circuit 9 shown in FIG.

FIG. 6 is a conceptual diagram for explaining the operation of the motion detection circuit 9;

7 is a circuit block diagram showing a configuration example of a scanning time reduction control circuit 10 shown in FIG.

FIG. 8 is a flowchart for explaining arithmetic control for reducing the scanning time of the microprocessor shown in FIG. 7;

9 is a circuit block diagram illustrating a configuration example of a polarity inversion control circuit 8 illustrated in FIG.

FIG. 10 is a circuit block diagram showing a configuration example of a synchronization control circuit 7 shown in FIG.

11 is a timing chart for explaining an operation of the synchronization control circuit 7 shown in FIG.

FIG. 12 is a circuit block diagram showing a configuration example of a Y driver 5 shown in FIG.

13 is a circuit block diagram illustrating a configuration example of a comparator 51 illustrated in FIG.

FIG. 14 is a circuit block diagram illustrating a configuration example of a liquid crystal display device according to a fourth embodiment of the present invention.

15 is a circuit block diagram showing a configuration example of a scanning time reduction control circuit shown in FIG.

FIG. 16 is a characteristic diagram illustrating an example of a relationship between a temperature and a response speed of a liquid crystal material having spontaneous polarization.

FIG. 17 is a circuit block diagram illustrating a configuration example of a liquid crystal display device according to a fifth embodiment of the present invention.

18 is a circuit block diagram illustrating a configuration example of a scanning time reduction control circuit 10 illustrated in FIG.

FIG. 19 is an explanatory diagram of symmetric drive and asymmetric drive of the liquid crystal.

FIG. 20 is a waveform chart for explaining a difference between AC driving and pseudo DC driving.

FIG. 21 is an explanatory diagram showing an applied voltage dependency of a response characteristic of a liquid crystal material.

FIG. 22 is a timing chart for explaining a method using a blanking time to improve response characteristics at the time of polarity inversion.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal panel 2 X driver 3 X driver drive signal 4 Y driver drive signal 5 Y driver 6 driver control circuit 7 Synchronization control circuit 8 Polarity inversion control circuit 9 Motion detection circuit 10 Scanning time reduction control circuit 11 Frame memory 12 Input display signal 13 Motion detection result signal 14 Interlaced scan calculation result signal 15 Polarity control signal 16 Mask signal 17 One frame delay display signal 18 FIFO memory 19 OR circuit 20 Timing adjusted display signal 51 Comparator 52 Output NOR circuit 53 Comparative address generator 54 Exclusive OR Circuit 81 Signal input circuit 82 Polarity memory 83 Mask memory 84 Address switching circuit 85 Memory output circuit 86 Scanning line number counter 91 Frame memory for motion detection 92 Subtractor 93 Accumulator 94 Latch circuit 101 My B processors 102 and 103 output IO circuit 104 temperature sensor signal 105 Temperature sensor 106 AD converter 107 command input line

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Toshi Hasegawa 33 Shinisogocho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside Toshiba Production Technology Laboratory Co., Ltd. (72) Inventor Hisao Fujiwara Shinisogocho, Isogo-ku, Yokohama-shi Kanagawa 33 Toshiba Corporation Production Technology Research Laboratories (72) Inventor Haruhiko Okumura 33 Shinisogocho, Isogo-ku, Yokohama-shi, Kanagawa 33 F-term (Reference) 2H093 NA11 NA34 NA16 NC16 NC27 NC29 NC50 NC57 NC65 ND02 ND12 ND34 ND44 ND52 NF20 NH18 5C006 AA01 AC24 AC28 AF19 AF62 AF73 AF81 BA12 BA13 BC16 BF09 BF14 BF26 BF28 BF38 FA12 FA19 FA21 FA25 FA34

Claims (6)

[Claims] A plurality of scanning lines and a plurality of video signal lines arranged in a matrix; a scanning line driving unit for supplying a write signal to each of the plurality of scanning lines; and a plurality of video signal lines, respectively. And a video signal line driving means for supplying a video signal to the liquid crystal display device, wherein a video signal provided with a frame scanning period and a vertical blanking period alternately is input and an image is displayed. The signal line driving unit is configured to supply a video signal supplied to the video signal line with a polarity inverted for each of a plurality of frames for each of the plurality of scanning lines. Except when the polarity of the video signal is inverted, a write signal having a first pulse width shorter than a time obtained by dividing the frame scanning period by the number of the scanning lines is supplied, When the polarity of the video signal is inverted, a write signal having a second pulse width longer than the first pulse width is written using the vertical blanking period and the extra time generated by the shortening. A liquid crystal display device characterized in that it is configured to supply. 2. A liquid crystal display device having a plurality of scanning lines and a plurality of video signal lines arranged in a matrix, by supplying a writing signal to the scanning lines and supplying a video signal to the video signal lines. A method for driving a liquid crystal display device for displaying an image, comprising: inputting a video signal in which a frame scanning period and a vertical blanking period are alternately provided; and for each of the plurality of scanning lines, When the polarity of the video signal supplied to the video signal line is inverted and supplied, except when the polarity of the video signal is inverted, the pulse width of the write signal is obtained by dividing the frame scanning period by the number of the scanning lines. When the polarity of the video signal is inverted, the pulse width of the write signal is generated by the vertical blanking period and the shortening. A driving time of the liquid crystal display device, wherein the driving time is a second time extended from the first time by utilizing the first surplus time. 3. The supply of the write signal to the scan line is deleted if the video signal to be supplied for the scan line is the same as that of the previous frame,
3. The liquid crystal display device according to claim 2, wherein the pulse width of the write signal when the polarity of the video signal is inverted is further extended using a second extra time generated by the deletion. Drive method. 4. The method according to claim 1, wherein the temperature of the liquid crystal display device is detected, and when the temperature decreases, the degree of the pulse width is increased by increasing or eliminating the degree of shortening. Item 4. The method for driving a liquid crystal display device according to item 2 or 3. 5. The method according to claim 3, wherein the determination is made based on a signal relating to the motion of the image included in the video signal or information relating to the motion of the image supplied together with the video signal. The driving method of the liquid crystal display device according to the above. 6. The driving method for a liquid crystal display device according to claim 2, wherein said liquid crystal display device has a liquid crystal material having spontaneous polarization.