JP2000013694A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device which is necessary to perform space filtering processing and has a little capacity by making an image pickup device output an output of a photo detection element in an optional basic block that is selected by a vertical selecting means and a horizontal selecting means. SOLUTION: A vertical read block selection circuit 202 makes a vertical selection line 205 of an externally designated pixel block active and a horizontal read block selection circuit 203 makes a horizontal selection line 206 of an externally designated pixel block active. The lines 205 and 206 are inputted to a pixel cell 201 and when both the lines 205 and 206 become active, a pixel signal is outputted. Then, the pixel signal of a selected row is inputted to a transfer switch 204. The switch 204 outputs the inputted pixel signal only when the line 206 is active and makes an output high impedance at the other time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a solid-state imaging device for outputting a signal of incident image light.

[0002]

2. Description of the Related Art FIG. 13 is a block diagram of a conventional solid-state imaging device. In the figure, reference numeral 901 denotes a CCD image sensor, 902 denotes an A / D converter (ADC), 903 denotes a memory, 904 denotes a spatial filter, and 905 denotes a D / A converter (DAC).

[0003] In the CCD image pickup device 901, a light detection signal obtained by each photoelectric conversion element is transferred by the CCD in the vertical direction and then by the CCD in the horizontal direction. That is, when all the light detection signals of a certain row arrive at the CCDs arranged in the horizontal direction by being transferred by the CCDs arranged in the vertical direction, all the light detection signals are sequentially transferred in the horizontal direction by the CCDs arranged in the horizontal direction. And output from the output terminal. This is performed sequentially for all rows. Therefore, as shown on the CCD image sensor 901 in FIG. 13, light detection signals (original pixels) are output from the CCD image sensor 901 in the order of the scanning lines.

The original pixels output from the CCD image sensor 901 are subjected to A / D conversion by the ADC 902,
3 is stored. For example, 3 output from the memory 903
Nine original pixels in the × 3 area are input to the spatial filter 904, and the spatial filter 904 performs a filter process such as LPF and BPF based on these original pixels.
The filtered signal is output. The DAC 905 performs D / A conversion on the signal after the filter processing and outputs an analog image signal.

[0005]

According to the prior art described above, in order to make the input signals of the spatial filter 904 uniform,
The pixel signal had to be stored in the memory 903. For example, when using a spatial filter 904 for inputting a pixel signal of a 3 × 3 pixel area, at least the capacity of the memory 903 has to be two lines.
In this case, the image output from the spatial filter is delayed by one line time from the image output from the CCD image sensor 901. In addition, the time from the detection of the pixel signal at each pixel of the CCD image sensor to the output of the pixel signal from the CCD image sensor 901 is delayed by the transfer time in the CCD image sensor 901.

Further, according to the above-described conventional example, the ADC 902, the memory 903,
An IC chip for the spatial filter 904 and the DAC 905 had to be prepared.

An object of the present invention is to provide a solid-state imaging device which requires a small memory capacity for performing spatial filtering.

Another object of the present invention is to provide a solid-state imaging device having a small delay time from the detection of a pixel signal in each pixel to the output of a signal after spatial filtering.

It is another object of the present invention to provide a one-chip solid-state imaging device that outputs a signal after spatial filtering.

[0010]

According to the present invention, there is provided a solid-state imaging device comprising a plurality of photodetectors in a pixel portion, wherein an image signal is generated from incident light incident on the plurality of photodetectors. Vertical direction selecting means for vertically selecting an arbitrary basic block comprising at least two of the plurality of photodetectors; horizontal direction selecting means for horizontally selecting the arbitrary basic block; and the vertical direction selecting means. And combination means for outputting the output of the light detection element in the arbitrary basic block selected by the horizontal direction selection means from the imaging element.

Further, in the solid-state imaging device according to the present invention, in the solid-state imaging device described above, the combination means includes a logical product means provided in the photodetector and an output of the photodetector in the horizontal direction. Selecting means for alternatively selecting a block as a unit.

Further, in the solid-state imaging device according to the present invention, in the above-described solid-state imaging device, the vertical direction selection means selects the photodetectors in the selected basic block in row units, and the combination means includes: It is characterized by comprising logical AND means for each same row in a basic block, and selecting means for selectively selecting the output of the photodetector in units of the basic block in the horizontal direction.

Further, in the solid-state imaging device according to the present invention, in the solid-state imaging device described above, the vertical direction selection means selects the photodetectors in the selected basic block with a time difference in units of rows, and the combination means Storage means for storing the output of the photodetector selected by the vertical direction selecting means with a time difference, and outputting the stored contents of the basic block selected by the horizontal direction selecting means.

Further, in the solid-state imaging device according to the present invention, in the solid-state imaging device described above, further, a block storage means for storing a plurality of units of the output of the image sensor in units of the basic block, and an output of the block storage means. And a spatial filter means for performing a spatial filter operation based on

Further, in the solid-state imaging device according to the present invention, in the solid-state imaging device described above, the spatial filter means inputs the output of the block storage means for a plurality of rows in parallel.
This is an IR filter, and the delay element is provided only in the horizontal direction.

Further, in the solid-state imaging device according to the present invention, in the solid-state imaging device described above, the spatial filter means inputs a plurality of columns of outputs of the block storage means in parallel.
This is an IR filter, and the delay element is provided only in the vertical direction.

Further, in the solid-state imaging device according to the present invention, in the solid-state imaging device described above, the spatial filter means is an FIR filter in which all taps directly input the outputs of the block storage means in parallel. .

Further, the solid-state imaging device according to the present invention is characterized in that, in the solid-state imaging device described above, the spatial filter means further includes an IIR filter element.

Further, in the solid-state imaging device according to the present invention, in the solid-state imaging device described above, the pixel unit, the vertical direction selection unit, the horizontal direction selection unit, the combination unit, the block storage unit, and the filter unit are the same. Characterized by being formed on a semiconductor chip.

Further, the solid-state imaging device according to the present invention is characterized in that the solid-state imaging device further includes a binarization circuit for binarizing the output of the spatial filter.

Further, in the solid-state imaging device according to the present invention, in the solid-state imaging device described above, the pixel unit, the vertical direction selection unit, the horizontal direction selection unit, the combination unit,
The block storage unit, the filter unit, and the second unit
The digitizing circuit is formed on the same semiconductor chip.

[0022]

FIG. 1 is a block diagram showing a configuration of a solid-state imaging device according to an embodiment of the present invention. Referring to FIG. 1, a solid-state imaging device according to an embodiment of the present invention includes a pixel unit 101, a block memory 102 that stores a plurality of blocks in units of image signals read from the pixel unit 101, and a block memory 102 that stores the image signal. Spatial filter 103 that performs spatial filter processing on the output image signal and outputs the result.
It is composed of

Block memory 102 and spatial filter 10
3 can be manufactured by the same process as that of the pixel portion 101.
Can be made into chips.

Next, an embodiment of each section of the solid-state imaging device shown in FIG. 1 will be described.

[First Embodiment] FIG. 2 is a block diagram showing a configuration of a pixel unit 101 according to a first embodiment.

Referring to FIG. 2, reference numeral 201 denotes a pixel cell formed by a photoelectric conversion element and peripheral transistors;
Is a vertical read block selecting circuit for selecting a vertical read pixel block, 203 is a horizontal read block select circuit for selecting a horizontal read pixel block, 207 is an output terminal, and 204 is a selected horizontal block. A transfer switch for outputting an image signal to an output terminal 207; 205, a vertical selection line;
6 is a horizontal selection line. In the present embodiment, as an example, the pixel block is 3 × 3 pixels.

The vertical readout block selection circuit 202
Activates a vertical selection line of a pixel block specified from the outside. The horizontal readout block selection circuit 203 activates a horizontal selection line of a pixel block specified from the outside. The vertical direction selection line 205 and the horizontal direction selection line 20 are input to the pixel cell 201, and a pixel signal is output when both the selection lines become active. Therefore, the pixel signals of the selected row are input to the transfer switch 204. The transfer switch 204 outputs the input pixel signal only when the horizontal selection line 206 is active, and otherwise sets the output to high impedance. Therefore, all the signals of the selected pixel block are simultaneously output from the output terminal 207 in parallel. The output signals of the pixel blocks are written to the block memory 102 simultaneously or sequentially.

In this embodiment, the signals of the selected pixel block can be output immediately and in parallel.

[Second Embodiment] FIG. 3 is a block diagram showing a configuration of a pixel unit 101 according to a second embodiment.

Referring to FIG. 3, reference numeral 301 denotes a pixel cell formed by a photoelectric conversion element and peripheral transistors;
Is a vertical readout block selection circuit for selecting a vertical readout pixel block, 303 is a horizontal readout block selection circuit for selecting a horizontal readout pixel block, 307 is an output terminal, and 304 is a selected horizontal block. A transfer switch for outputting an image signal to an output terminal 307; 305, a vertical selection line;
6 is a horizontal direction selection line, and 308 is an AND gate. In this embodiment, as an example, a pixel block is 3 × 3.
Although the pixels are used, the block size in the vertical direction can be changed with the same configuration.

The vertical read block selection circuit 302
Sequentially activates the vertical selection lines 305 of the rows belonging to the pixel block specified from the outside. The horizontal readout block selection circuit 303 activates a horizontal selection line 306 of a pixel block specified from the outside. The AND gate 308 inputs the vertical direction selection line 305 and the horizontal direction selection line 306, and activates the output (H) when both the selection lines are active (HIGH).
IGH). The pixel cell 301 has an AND gate 3
08 is input, and the pixel signal is output when the output of the AND gate 30 becomes active. Accordingly, the pixel signals of the rows belonging to the selected block are sequentially input to the transfer switch 304. The transfer switch 304 outputs the input pixel signal only when the horizontal selection line 306 is active, and otherwise sets the output to high impedance. Therefore, the signal of the selected pixel block is output in parallel from the output terminal 307 for each row. The output signals of the pixel blocks are simultaneously or sequentially stored in the block memory 102.
Is written to.

In this embodiment, since the signals inside the block are sequentially read in the vertical direction, the reading speed is lower than in the first embodiment. However, the number of conductors for guiding the output of the pixel cell to the transfer switch is different from that of the first embodiment.
Less than in

[Embodiment 3] FIG. 4 is a block diagram showing a configuration of a pixel unit 101 according to Embodiment 3.

Referring to FIG. 4, reference numeral 301 denotes a pixel cell formed by a photoelectric conversion element and peripheral transistors;
Is a vertical read block select circuit for selecting a vertical read pixel block, 303 is a horizontal read block select circuit for selecting a horizontal read pixel block, 305 is a vertical select line, 306 is a horizontal select line, 407, an output terminal; 401, an image signal of the selected horizontal block output to the output terminal 407;
It is a line memory. In this embodiment, as an example, the pixel block is 3 × 3 pixels.

The vertical read block selection circuit 302
Sequentially activates the vertical selection lines 305 of the rows belonging to the pixel block specified from the outside. Pixel cell 3
01 receives a vertical selection line 305 and outputs a pixel signal when the vertical selection line 305 is activated. Therefore, the pixel signals of the rows belonging to the selected block are sequentially input to the three-line memory 401. Three
The line memory 401 outputs a pixel signal of an active horizontal direction selection line 306. Therefore, the output terminal 307
, All signals of the selected pixel block are output in parallel. The output pixel block signals are simultaneously
Alternatively, the data is sequentially written to the block memory 102.

In this embodiment, as in the second embodiment, the signals inside the block are sequentially read in the vertical direction, so that the read speed is lower than in the first embodiment. However, the number of conductors for guiding the output of the pixel cell to the transfer switch can be smaller than in the first embodiment.

Although the spatial filter 103 needs a pixel signal extending over a plurality of blocks in the horizontal direction depending on the position of the output pixel of the spatial filter 103, the pixel signal of the plurality of blocks in the horizontal direction is required. , And may be read out as necessary and stored in the block memory 102. In this case, the capacity of the block memory 102 is sufficient for several blocks.

Depending on the position of the output pixel of the spatial filter 103, the spatial filter 103 needs pixel signals extending over a plurality of blocks in the vertical direction. , And may be read out as necessary and stored in the block memory 102. In this case, the capacity of the block memory 102 is sufficient for several blocks, but may be several blocks for reducing the read frequency.

[Fourth Embodiment] FIG. 5 is a block diagram showing a configuration of a spatial filter 103 according to a fourth embodiment.

Referring to FIG. 5, reference numeral 501 denotes a multiplier;
2 is a delay element, and 503 is an adder. In the present embodiment, as an example, the spatial filter is a 3 × 3 tap two-dimensional F
It is an IR filter.

The signal of each line is input to the spatial filter. The delay element 502 delays the pixel signal input for each line to align the pixel signals x _{i, j} and supplies the same to the multiplier 501. The multiplier 502 multiplies the pixel signal x _{i, j} by the filter coefficient α _{i, j} and outputs a product. However, in this example, −1 ≦ i, j ≦ 1. Adder 50
Reference numeral 3 indicates the sum of the products of all the multipliers 401 and outputs the sum.

Therefore, the output y _{i, j} of the spatial filter according to this embodiment is

[0043]

(Equation 1) Becomes

FIG. 6 is an example of the coefficient α _{i, j} of the spatial filter. When the coefficients shown in FIG. 6B are used, the spatial filter becomes a smoothing filter. When the coefficient shown in FIG. 6C is used, the spatial filter is, for example, a horizontal high-pass filter (HPF) that extracts a horizontal edge. When the coefficients shown in FIG. 6D are used, the spatial filter is, for example, a two-dimensional high-pass filter (HPF) that extracts edges in all directions.

The pixel signals between the lines may be connected by a delay element to reduce the number of input pixel signals of the spatial filter to, for example, one.

The output of the block memory may be directly input to the input pixels (tap) of all the multipliers without connecting each pixel (tap) with the delay element.

Further, in the above description of this embodiment,
Although the spatial filter has been described as an FIR filter, an IIR filter element shown in FIG. 7 may be added to the output stage. 7, 510 is an adder, 502 is a multiplier, and 503 is a delay element.

Further, the horizontal direction and the vertical direction may be switched.

[Fifth Embodiment] FIG. 8 is a block diagram showing a configuration of a spatial filter 103 according to a fifth embodiment. The spatial filter 103 according to the present embodiment is a sub-band filter.

Referring to FIG. 8, reference numeral 601 denotes a one-dimensional horizontal high-pass filter (HPF), 602 denotes a one-dimensional horizontal low-pass filter (LPF), and 603 and 604 denote sub-sampling units.

The larger of the order of the one-dimensional horizontal high-pass filter 601 and the order of the one-dimensional horizontal high-pass filter 602 is set to 2n + 1, and the one-dimensional vertical high-pass filter 6
The larger of the order of the 04 and the order of the one-dimensional vertical high-pass filter 605 is set to 2m + 1. One-dimensional horizontal high-pass filter 601 and one-dimensional horizontal low-pass filter 602
Is 2m + 1.

Each of the one-dimensional horizontal high-pass filter 601 and each of the one-dimensional horizontal low-pass filters 602 receives the pixel signals of each row shown in FIG. That is, for example, the one-dimensional horizontal high-pass filter 601 #
The one-dimensional and one-dimensional horizontal low-pass filter 602 # 1 filters the pixel signals in the area 701, and the one-dimensional horizontal high-pass filter 601 # 2 and the one-dimensional horizontal low-pass filter 602 # 2 , And a one-dimensional horizontal high-pass filter 601 # 2m + 1 and a one-dimensional horizontal low-pass filter 602 # 2m + 1 perform a filtering process on the pixel signal in the region 703. The one-dimensional horizontal high-pass filter 601 and the one-dimensional horizontal low-pass filter 602 and the subsequent sub-sampling unit 603 include a one-dimensional horizontal high-pass filter 601 and a one-dimensional horizontal high-pass filter. The output of 602 is sub-sampled by に in the horizontal direction. The one-dimensional vertical high-pass filter 604 and the one-dimensional vertical low-pass filter 605 are:
2m + 1 sub-sampling units 60 in area 704
The filter processing is performed by inputting the output of No.3. Sub-sampling section 604 at the subsequent stage of one-dimensional vertical high-pass filter 604 and one-dimensional vertical low-pass filter 605
Subsamples the outputs of the one-dimensional vertical high-pass filter 604 and the one-dimensional vertical low-pass filter 605 in the vertical direction. Thus, the sub-sampling unit 60
4, the diagonal high frequency component HHi _{, j} , the horizontal high frequency component HLi _{, j} , the vertical high frequency component LHi _{, j} , and the diagonal low frequency component LLi _{, j}
Is output.

FIG. 10 shows a configuration diagram of the one-dimensional horizontal high-pass filter 601 and the one-dimensional horizontal low-pass filter 602. Referring to the figure, these are composed of a delay element 620 for delaying an input pixel, a multiplier 621, and an adder 622.

FIG. 11 shows a configuration diagram of the one-dimensional vertical high-pass filter 604 and the one-dimensional vertical low-pass filter 605. Referring to the figure, these are multipliers 63
0 and an adder 631.

The one-dimensional horizontal high-pass filter 6
The 01 and one-dimensional horizontal low-pass filter 602 is not configured to connect each pixel (tap) with a delay element, and the output of the block memory is directly input to all the input pixels (tap) of the multiplier. Is also good.

In the above description of the present embodiment,
Although the spatial filter has been described as an FIR filter, the IIR filter element shown in FIG. 7 is replaced by a one-dimensional horizontal high-pass filter 601, a one-dimensional horizontal low-pass filter 602, and a one-dimensional vertical high-pass filter 604. ,
It may be added to the output stage of the one-dimensional vertical low-pass filter 605.

The horizontal direction and the vertical direction may be switched.

[Embodiment 6] Spatial filter 1 shown in FIG.
03 may be a band-pass filter or a high-pass filter, and a binarization circuit shown in FIG. 12 may be added at the subsequent stage so that the binarization circuit outputs a contour extraction signal.

In the binarization circuit shown in FIG.
Reference numerals 1 and 702 denote comparators, and 703 denotes an OR circuit. This outputs a high-level signal when the absolute value of the input signal exceeds a predetermined voltage ΔV.

[0060]

As described above, according to the present invention, since only a block memory is required as a memory, the memory capacity required for performing the spatial filtering can be reduced.

Further, according to the present invention, the signal detected at each pixel is transferred to the block memory in a short time, and the spatial filter has only a small delay element. The delay time until the output point of the signal after the filter processing can be reduced.

Further, according to the present invention, since the block memory and the spatial filter can be manufactured in the same process as the pixel section, it is possible to provide a solid-state imaging device that outputs a signal after the spatial filter processing with one chip. Thus, cost reduction and size reduction can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a pixel unit according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a pixel unit according to a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a pixel unit according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a spatial filter according to Embodiment 4 of the present invention.

FIG. 6 is a diagram illustrating an example of coefficients of the spatial filter illustrated in FIG. 5;

FIG. 7 is a diagram showing a configuration of an IIR filter element.

FIG. 8 is a block diagram showing a configuration of a spatial filter according to Embodiment 5 of the present invention.

9 is a diagram showing an input area of the spatial filter shown in FIG.

FIG. 10 is a diagram showing a configuration of a one-dimensional horizontal high-pass filter and a one-dimensional horizontal low-pass filter shown in FIG.

11 is a diagram showing a configuration of a one-dimensional vertical high-pass filter and a one-dimensional vertical low-pass filter shown in FIG.

FIG. 12 is a block diagram illustrating a configuration of a binarization circuit according to a sixth embodiment of the present invention.

FIG. 13 is a block diagram illustrating a configuration of a conventional solid-state imaging device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Pixel part 102 Block memory 103 Spatial filter 201, 301 Pixel cell 202, 302 Vertical read block selection circuit 203, 303 Horizontal read block selection circuit 204, 304 Transfer switch 401 Three line memory 601 One-dimensional horizontal high-pass filter 602 One-dimensional horizontal low-pass filter 604 One-dimensional vertical high-pass filter 605 One-dimensional vertical low-pass filter

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Katsuhito Sakurai, Inventor 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Tohru 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Within (72) Inventor Tetsunobu Kochi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Takumi Hiyama 3-30-2, Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Narito Sugawa 3-30-2 Shimomaruko, Ota-ku, Tokyo F-term (reference) 4M118 AA10 AB01 AB08 BA10 BA30 FA06 5C024 AA01 CA00 CA31 FA01 FA11 GA31 HA01 HA02 HA17 HA19 HA24

Claims (12)

[Claims] 1. A solid-state imaging device that includes a plurality of photodetectors in a pixel unit and generates an image signal from incident light incident on the plurality of photodetectors, the solid-state imaging device including at least two of the plurality of photodetectors. Vertical direction selecting means for selecting an arbitrary basic block in the vertical direction; horizontal direction selecting means for selecting the arbitrary basic block in the horizontal direction; and the vertical direction selecting means selected by the vertical direction selecting means and the horizontal direction selecting means. A combination means for outputting the output of the photodetector in an arbitrary basic block from the image sensor. 2. The solid-state imaging device according to claim 1, wherein the combination unit outputs a logical product unit provided in the photodetector and an output of the photodetector in units of the basic block in the horizontal direction. A solid-state imaging device comprising: a selection unit that selects an alternative. 3. The solid-state imaging device according to claim 1, wherein the vertical direction selecting means selects the photodetectors in the selected basic block on a row-by-row basis, and the combining means selects the photodetecting elements in the basic block. A solid-state imaging device comprising: a logical AND means for each same row; and a selecting means for selectively selecting an output of the photodetector in units of the basic block in the horizontal direction. 4. The solid-state imaging device according to claim 1, wherein the vertical direction selection means selects the photodetectors in the selected basic block with a time difference in a unit of a row, and the combination means selects the light detection elements with a time difference. A solid-state imaging device, comprising: a storage unit that stores an output of the light detection element selected by a vertical direction selection unit and outputs a storage content of the basic block selected by the horizontal direction selection unit. 5. The solid-state imaging device according to claim 1, further comprising: a block storage unit configured to store a plurality of units of the output of the imaging element in units of the basic block; A spatial filter means for performing a spatial filter operation based on the output of the means. 6. The solid-state imaging device according to claim 5,
The solid-state imaging device according to claim 1, wherein the spatial filter unit is an FIR filter that inputs outputs of the block storage unit for a plurality of rows in parallel, and a delay element provided is only in a horizontal direction. 7. The solid-state imaging device according to claim 5,
The solid-state imaging device according to claim 1, wherein the spatial filter unit is an FIR filter that inputs a plurality of columns of outputs of the block storage unit in parallel, and a delay element provided is only in a vertical direction. 8. The solid-state imaging device according to claim 5,
The solid-state imaging device according to claim 1, wherein the spatial filter unit is an FIR filter in which all taps directly input the output of the block storage unit in parallel. 9. The solid-state imaging device according to claim 6, wherein said spatial filter means further comprises:
A solid-state imaging device comprising an IR filter element. 10. The solid-state imaging device according to claim 5, wherein the pixel unit, the vertical direction selection unit, the horizontal direction selection unit, the combination unit, the block storage unit, and the filter unit are the same. A solid-state imaging device formed on a semiconductor chip. 11. The solid-state imaging device according to claim 5, wherein an output of said spatial filter is further binarized.
A solid-state imaging device comprising a value conversion circuit. 12. The solid-state imaging device according to claim 5, wherein the pixel section, the vertical direction selection section, the horizontal direction selection section, the combination section, the block storage section, the filter section, and the second section. A solid-state imaging device, wherein the digitizing circuit is formed on the same semiconductor chip.