JP2000013456A - Frequency error estimating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure high estimation accuracy even under any transmission line having inter-code interference. SOLUTION: An inputted reception signal is outputted through a matched filter 3 to a multiplier 4 and at the same time, this signal is outputted to the multiplier 4 as it is without passing through the matched filter 3. The reception signals of these two systems are multiplied with a modulation multi-level value M at multipliers 4A and 4B and a carrier component having phase information is extracted. D symbol delay detection is respectively applied to the signals of two systems by delay detectors 5A and 5B, the information of phase change between D symbols is detected and information in the phase changes of two systems is synthesized by an adder 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency error estimating circuit applied to an adaptive equalizer used for a receiver in the field of mobile communication, and more particularly, to a frequency error caused by instability of a local oscillator. The present invention relates to a frequency error estimating circuit that estimates and corrects an error.

[0002]

2. Description of the Related Art FIG. 10 shows, for example, "Configuration of MLSE Receiver Having Frequency Offset Correction Function in TDMA Digital Mobile Communication" (Okanogami et al., IEICE Transactions Vol. J73-BII, No. 11, 1990
-11, pp. 736-744) is a block diagram showing a conventional frequency error estimating circuit. In FIG. 10, reference numeral 100 denotes a conventional frequency error estimating circuit.

[0003] This frequency error estimating circuit 100 is shown in FIG.
As shown in (1), a matched filter 3, a multiplier 4, an averaging filter 7, a rectangular / polar coordinate converter 8, and a divider 9 are provided. The matching filter 3 has an input terminal 1 for a reception signal.
And filters the input received signal to obtain a correlation value. The multiplier 4 multiplies the correlation value by M. The averaging filter 7 averages the M-multiplied correlation value over an N symbol length to obtain phase change information. The rectangular / polar coordinate converter 8 converts phase change information from rectangular coordinates to polar coordinates. The divider 9 is connected to the output terminal 2 of the estimated frequency error, obtains a phase change between one symbol from the information of the phase change subjected to the polar coordinate conversion, and outputs this as an estimated frequency error.

Next, the operation will be described. In the frequency error estimating circuit 100 shown in FIG. 10, the input received signal is filtered by the matched filter 3, and the correlation value is obtained. After that, in the multiplier 4, the correlation value is multiplied by the modulation multilevel number M, and the modulation component is removed. Further, the averaging filter 7 averages the correlation values over a length of N symbols. At this time, since information on the phase change between N symbols is obtained, the obtained information on the phase change is divided by the modulation multilevel number M and the averaged symbol number N. as a result,
A phase change between one symbol, that is, a frequency error is estimated.

In this frequency error estimating circuit 100,
The matched filter 3 is provided so that a frequency error can be estimated under a transmission path where any intersymbol interference occurs. Now, let us consider estimating the frequency error under the transmission path where the intersymbol interference of the transmission path memory length L occurs. Assuming that the transmission path impulse response is c _i (i = 0, 1,..., L), the reception signal rk after quasi-synchronous detection at time _k
Is

(Equation 1) Can be represented by Here, θ _k is a phase caused by a frequency error at time k, and I _k is a transmission symbol at time k.

First, the received signal is multiplied by M without applying a matched filter. Now assuming that the occurrence of each transmission symbol is independent from the randomness of the received signal s _k is transmitted symbols M multiplication,

(Equation 2) Can be approximated as follows. Here, if the magnitude of the frequency offset is sufficiently small with respect to the transmission rate,

(Equation 3) The received signal s _k which can be approximated, and M multiplied with,

(Equation 4) And phase information can be obtained.

However, depending on the state of intersymbol interference,

(Equation 5) In this case, phase information cannot be obtained.

[0008] On the other hand, consider a case where a matched filter 3 is applied to a received signal. The matched filter output y _k of the received signal is

(Equation 6) Becomes From equations (1) and (5),

(Equation 7) Can be expressed as

Here, A _I in equation (6) is an autocorrelation function of the transmission path impulse response.

(Equation 8) It is. Here, when the matched filter output y _k is multiplied by M,
An approximation similar to that for obtaining the above equation (4) can be performed, and the matched filter output f _k multiplied by M is

(Equation 9) Becomes If the output y _k of the matched filter is averaged over N symbol lengths, information on the phase change between N symbols can be obtained. The frequency error is estimated based on this information.

[0010]

Since the conventional frequency error estimating circuit is configured as described above, the matched filter 3 is always applied to the received signal. In some cases, the frequency error can be estimated without using the matched filter 3. In this case, the estimation accuracy may be higher when the matched filter 3 is not applied, so that there is a problem that the estimation accuracy may be reduced by filtering.

Further, the conventional frequency error estimating circuit 100 has a problem that the reliability of the phase information is low and the estimation accuracy is reduced because the information on the phase change is obtained only by the average of N symbols.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a frequency error estimating circuit capable of securing high estimation accuracy under a transmission path having any intersymbol interference. And

[0013]

Means for Solving the Problems The above-mentioned problems are solved,
In order to achieve the above object, a frequency error estimating circuit according to the present invention is a frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal. First
Multiplying means, second multiplying means for directly multiplying the received signal, and phase change detecting means for detecting phase change information based on the signals multiplied by the first and second multiplying means, respectively. It is characterized by the following.

According to the present invention, since the received signal is filtered and then multiplied, the same received signal is also multiplied as it is, and the information of the phase change is detected based on each multiplied signal. It is possible to select the higher estimated value according to the state of
As a result, a frequency error with high estimation accuracy can be obtained even if any intersymbol interference occurs.

[0015] A frequency error estimating circuit according to the next invention comprises:
The first multiplier has a matched filter for filtering a received signal.

According to the present invention, in a system that passes through a matched filter and a system that does not pass through a matched filter, a received signal is filtered by a matched filter in a system that passes through a matched filter. You can gain the ability.

A frequency error estimating circuit according to the next invention is as follows.
The first multiplier has a fixed filter for fixing a tap coefficient and filtering a received signal.

According to the present invention, in the system that passes through the fixed filter and the system that does not pass through the fixed filter, the received signal is filtered by the fixed filter whose tap coefficient is fixed, so that a matched filter is obtained. The need to estimate the transmission path characteristics
The hardware scale can be reduced as compared with the case where a matched filter is used.

A frequency error estimating circuit according to the next invention has
The phase change detecting means detects two types of phase change information by delay detection of the signals respectively multiplied by the first and second multiplying means, and synthesizes the two types of phase change information. And

According to the present invention, phase change information of two systems is detected by delay detection of a signal multiplied by two systems,
Since the information on the phase changes of the two systems is combined, more accurate phase information can be obtained, thereby improving the estimation accuracy.

A frequency error estimating circuit according to the next invention is as follows.
In a frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of the received signal, a filtering unit for filtering the received signal, and any one of the received signal and the received signal filtered by the filtering unit Selection means for selecting and outputting one of them, multiplication means for multiplying one of the output signals selected by the selection means, and phase change detecting phase change information based on the signal multiplied by the multiplication means. And a detecting means.

According to the present invention, one of the received signal and the filtered received signal is selected, and the information of the phase change is detected after multiplying one of the selected output signals. The signal with the higher estimation accuracy is selected in accordance with the state of the intersymbol interference, so that a frequency error with a higher estimation accuracy can be obtained even if any intersymbol interference occurs.

A frequency error estimating circuit according to the next invention is as follows.
The phase change detection means detects phase change information by delay detection of the signal multiplied by the multiplication means.

According to the present invention, the information of the phase change is detected by the delay detection of the multiplied signal.
More accurate phase information can be obtained, thereby improving estimation accuracy.

A frequency error estimating circuit according to the next invention is as follows.
In a frequency error estimating circuit for estimating the frequency error between the local oscillation frequency of the receiver and the carrier frequency of the received signal, filtering means for filtering the received signal, and multiplying means for multiplying the received signal filtered by the filtering means, Phase change detection means for detecting phase change information by performing delay detection on the signal multiplied by the multiplication means.

According to the present invention, the received signal is filtered, the filtered received signal is multiplied, and then the delay detection is performed to detect the phase change information. And thus the estimation accuracy is improved.

A frequency error estimating circuit according to the next invention is as follows.
The filtering means has a matched filter for filtering a received signal.

According to the present invention, since the received signal is filtered by the matched filter, it is possible to obtain a better equalization capability in the state of intersymbol interference.

A frequency error estimating circuit according to the next invention has
The filtering means has a fixed filter for fixing a tap coefficient and filtering a received signal.

According to the present invention, the received signal is filtered by the fixed filter having a fixed tap coefficient, so that it is not necessary to estimate the transmission path characteristics necessary for obtaining a matched filter, and the matched filter is not used. The hardware scale can be reduced as compared with the case where there is a case.

A frequency error estimating circuit according to the next invention is as follows.
In a frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal, a first terminal for inputting a matched filter output obtained by applying a matched filter to the received signal, and inputting the received signal A second terminal;
A pair of multipliers for multiplying the received signals input to the first and second terminals, and a pair of delay detectors for detecting information on a phase change from the output signals multiplied by the pair of multipliers, It is characterized by having.

According to the present invention, the estimation of the frequency error based on the signal obtained by applying the matched filter to the received signal and the estimation based on the received signal not subjected to the matched filter are performed at the same time. An estimated value with a higher estimation accuracy can be selected according to the state, whereby a frequency error with a higher estimation accuracy can be obtained even if any intersymbol interference occurs. Further, since the delay detection is used to detect the phase change information, more accurate phase information can be obtained, and the estimation accuracy is improved.

A frequency error estimating circuit according to the next invention is as follows.
The image processing apparatus further includes an adder that synthesizes information on the phase change detected by each of the pair of delay detectors.

According to the present invention, the phase change information detected by the pair of differential detectors is synthesized by the adder, so that the received signal is passed through a matched filter and the received signal is not passed. And more accurate phase information can be obtained.

A frequency error estimating circuit according to the next invention is as follows.
In a frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal, a first terminal for inputting a matched filter output obtained by applying a matched filter to the received signal, and inputting the received signal A second terminal;
A switch for selecting one of the first and second terminals, a multiplier for multiplying the output signal selected by the switch, and information on a phase change from the output signal multiplied by the multiplier. And a delay detector for detecting.

According to the present invention, one of the signal obtained by applying a matched filter to the received signal and the received signal not applied by the matched filter is selected by the switch.
The signal with the higher estimation accuracy is selected according to the state of the intersymbol interference, whereby a frequency error with a higher estimation accuracy can be obtained even if any intersymbol interference occurs. Also,
Since the delay detection is used to detect the phase change information, more accurate phase information can be obtained, and the estimation accuracy is improved.

A frequency error estimating circuit according to the next invention has
In a frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal, a frequency multiplier for multiplying a signal obtained by applying a matched filter to a received signal, and a signal multiplied by the frequency multiplier are used. A delay detector for detecting information on a phase change.

According to the present invention, the signal obtained by subjecting the received signal to the matching filter by the multiplier is multiplied, and the information on the phase change is detected from the multiplied signal by the delay detector. The phase change can be detected by utilizing the phase change, whereby more accurate phase information can be obtained and the estimation accuracy can be improved.

A frequency error estimating circuit according to the next invention has
In a frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of the receiver and a carrier frequency of the received signal, a first terminal for inputting a fixed filter output obtained by applying a fixed filter having a fixed tap coefficient to the received signal, A second terminal for inputting the received signal, a pair of multipliers for multiplying the received signals respectively input to the first and second terminals, and a phase change from the output signal multiplied by the pair of multipliers. A pair of differential detectors for detecting information.

According to the present invention, a fixed filter output obtained by applying a fixed filter having a fixed tap coefficient to a received signal is inputted from the first terminal, a received signal is inputted from the second terminal, and the received signal is inputted by a pair of multipliers. Since the received signals respectively input to the first and second terminals are multiplied, and a pair of delay detectors detects phase change information from the output signals multiplied by the corresponding pair of multipliers. This eliminates the need for estimating the transmission path characteristics necessary for obtaining a matched filter, and can reduce the hardware scale. In addition, since the estimation of the frequency error based on the signal obtained by applying the fixed filter to the received signal and the estimation based on the received signal not applied with the fixed filter are performed at the same time, the accuracy of the estimation accuracy depends on the state of the intersymbol interference. A higher estimation value can be selected to be selected, so that a frequency error with high estimation accuracy can be obtained even if any intersymbol interference occurs. Furthermore, by detecting a phase change using differential detection, more accurate phase information can be obtained and estimation accuracy can be improved.

A frequency error estimating circuit according to the next invention has
The image processing apparatus further includes an adder that synthesizes information on the phase change detected by each of the pair of delay detectors.

According to the present invention, the phase change information detected by the pair of differential detectors is synthesized by the adder. Therefore, the received signal is passed through a fixed filter and the received signal is not passed. And more accurate phase information can be obtained.

The frequency error estimating circuit according to the next invention
In a frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of the receiver and a carrier frequency of the received signal, a first terminal for inputting a fixed filter output obtained by applying a fixed filter having a fixed tap coefficient to the received signal, A second terminal for inputting the reception signal, a switch for selecting one of the first and second terminals, a multiplier for multiplying the output signal selected by the switch, And a delay detector for detecting phase change information from the multiplied output signal.

According to the present invention, a fixed filter output obtained by applying a fixed filter having a fixed tap coefficient to a received signal is input to the first terminal, the received signal is input to the second terminal, and the first and the second terminals are switched by the switch. One of the second terminals is selected, the output signal selected by the switch is multiplied by the multiplier, and the information of the phase change is detected from the multiplied output signal by the delay detector. Therefore, there is no need to estimate the transmission path characteristics necessary for obtaining a matched filter, and the hardware scale can be reduced. In addition, since either a signal obtained by applying a fixed filter to the received signal or a received signal not applied with the fixed filter can be selected by a switch, a signal having a higher estimation accuracy is selected according to the state of intersymbol interference, and Thus, a frequency error with high estimation accuracy can be obtained even if any intersymbol interference occurs. Further, since the delay detection is used to detect the phase change information, more accurate phase information can be obtained, and the estimation accuracy is improved.

A frequency error estimating circuit according to the next invention has
In a frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal, a multiplier for multiplying a signal obtained by applying a fixed filter having a fixed tap coefficient to the received signal, and the multiplier And a delay detector for detecting information on a phase change from the signal multiplied by (1).

According to the present invention, a signal obtained by applying a fixed filter having a fixed tap coefficient to a received signal by the multiplier is multiplied, and information on a phase change is detected from the multiplied signal by the delay detector. Therefore, there is no need to estimate the transmission path characteristics necessary for obtaining a matched filter, and the hardware scale can be reduced. Further, by detecting a phase change using differential detection, more accurate phase information can be obtained and estimation accuracy can be improved.

[0047]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a frequency error estimating circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

Embodiment 1 First, the configuration will be described. FIG. 1 is a block diagram showing a configuration example of the frequency error estimating circuit according to the first embodiment of the present invention. In FIG.
1A shows a frequency error estimating circuit according to the first embodiment. The frequency error estimating circuit 1A includes a matched filter 3, multipliers 4A and 4B,
It comprises D symbol differential detectors 5A and 5B, an adder 6, an averaging filter 7, a rectangular / polar coordinate converter 8, and a divider 9. In the above configuration, the matching filter 3, the averaging filter 7, the rectangular / polar coordinate converter 8, and the divider 9 are the same as those in the above-described conventional configuration, and therefore, the same symbols are used and the description is omitted. The input terminal 1 is connected to the matching filter 3 and each input of the multiplier 4B.

In the first embodiment, two types of processing systems are provided from the input terminal 1 to the averaging filter 7. The first processing system includes an input terminal 1, a matched filter 3, a multiplier 4
A and D symbol delay detector 5A, an adder 6, and an averaging filter 7, and the second processing system includes an input terminal 1, a multiplier 4B, a D symbol delay detector 5B, an adder 6, , An averaging filter 7. The difference between these two processing systems is whether the matched filter 3 is provided on the path or not.

The multipliers 4A and 4B have the same function, and multiply the input signal by M as in the conventional multiplier 4. A first terminal 41 connected to the output of the matched filter 3 is provided at the input of the multiplier 4A, and a second terminal 42 connected to the input terminal 1 is provided at the input of the multiplier 4B.
The D symbol differential detectors 5A and 5B have the same function. The D symbol differential detectors 5A and 5B detect a phase change between the D symbols multiplied by the M multipliers 4A and 4B, respectively. The adder 6 includes a D symbol differential detector 5A,
In step 5B, information on the phase change of the detected D symbol is synthesized.

Next, the operation will be described. In the configuration shown in FIG. 1, an input received signal is first input to the multiplier 4 through the matched filter 3 and input to the multiplier 4 without being applied to the multiplier 4. It is separated into two systems, the second processing system. Then, the received signals separated into the two are respectively multiplied by the multipliers 4.
A and 4B are multiplied by the modulation multi-level number M. As a result, the modulation component is removed from each signal, and a carrier component having phase information is extracted.

Subsequently, D-symbol delay detection is performed on the two signals in the delay detectors 5A and 5B, and information on the phase change between the D symbols is detected. Here, the information of the two systems of phase change is synthesized by the adder 6, and the synthesized signal is averaged by the averaging filter 7. Thereby, the influence of noise is reduced. The signal thus averaged is converted by the coordinate converter 8 from rectangular coordinates to polar coordinates. Finally, the information on the phase change between the D symbols (polar coordinates) is expressed by the divider 9 as the modulation multilevel number M and the differential detection symbol number D.
To obtain a phase change between one symbol, that is, a frequency error.

Next, consider a multiple open loop type frequency error estimating circuit in which d (d is a natural number) frequency error estimating circuits 1A are arranged in parallel as shown in FIG. FIG. 2 is a block diagram showing an example of a multiple open loop type frequency error estimating circuit to which the above frequency error estimating circuit is applied. The multiple open loop estimating circuit shown in FIG. 2 has the same configuration and the same function as the frequency error estimating circuit 1A, and includes frequency error estimating circuits 1A1 to 1Ad provided in parallel with the input terminal 1; A selector 10 that is connected to the outputs of the estimation circuits 1A1 to 1Ad, selects a frequency error candidate that is expected to be closest to the actual frequency error as an estimated value, and outputs the estimated value to the output terminal 2. .

Here, the number of differential detection symbols is D ₁ <D ₂ <
... <D _d is set. Frequency error estimation circuit 1
A1 to 1Ad have a wide frequency error detection range when the number of differential detection symbols is small, but have low estimation accuracy. On the other hand, when the number of differential detection symbols is increased, the detection range of the frequency error is narrow, but the estimation accuracy is high. For example, constituting the multiple open-loop frequency error estimating circuit consisting of three frequency error setting the differential detection symbol number D _i as follows estimation circuit 1A1～1A3. That is, if i = 3,

(Equation 10) Becomes

FIG. 3 shows the three frequency error estimating circuits 1A.
The method for removing the frequency uncertainty of the multiple open loop frequency error estimating circuit composed of 1 to 1A3 will be described. When the actual frequency error is π / 4, three frequency error estimating circuits 1A1
As a frequency error candidate of an estimated value for １1A3, as shown in FIG. 3, one of A11 and two of A21 and A23 corresponding to the number of differentially detected symbols due to frequency uncertainty.
And 4 of A31, A32, A33 and A34
There are individuals. In this multiple open loop type frequency error estimating circuit, first, two candidates (one A23, one A23,
A21 closest to A31 is selected from one A21). Next, A31 closest to A21 is selected from the four candidates (A31, A32, A33 and A34). As a result, the frequency error candidate A31 is output as an estimated value.

That is, since the above multiple open loop type frequency error estimating circuit operates while removing the frequency uncertainty,
The detection range of the frequency estimation error determined by differential detection symbol number D _1, is determined by D _d the estimation accuracy differential detection symbol number. Therefore, the multiple open loop type frequency error estimating circuit can simultaneously realize a wide detection range and high estimation accuracy.

As described above, according to the first embodiment, the input received signal is passed through a matched filter for obtaining a better equalization capability depending on the state of inter-symbol interference, and is passed through a matched filter. Not divided into two systems, part 2
After detecting information of phase change at the same time using two signals,
Since two pieces of phase information are combined, high estimation accuracy can be maintained even in the case of transmission path characteristics in which estimation accuracy is reduced due to the influence of a matched filter.

Further, since the delay detection is used to detect the phase change information, more accurate phase information can be obtained, and the estimation accuracy is improved. Further, by using a plurality of delay detection waveform estimation circuits, the present invention can be extended to a multiple open loop type frequency error estimation circuit that simultaneously achieves high estimation accuracy and a wide pull-in range.

Embodiment 2 By the way, the first embodiment described above
In the above, the input received signal is divided into two systems, and the estimation accuracy is enhanced by simultaneously estimating the frequency error using the two signals. However, the present invention is not limited to this, and will be described below. As in the second embodiment, by selecting one of the two input signals that is expected to have higher estimation accuracy, it is possible to ensure high estimation accuracy even if any intersymbol interference occurs. Is also good.

First, the configuration will be described. FIG. 4 is a block diagram showing one configuration example of the frequency error estimating circuit according to the second embodiment of the present invention. In FIG. 4, reference numeral 1B denotes a frequency error estimating circuit according to the second embodiment. This frequency error estimating circuit 1B includes, for example, as shown in FIG.
Matched filter 3, multiplier 4, D symbol differential detector 5,
Averaging filter 7, rectangular / polar coordinate converter 8, divider 9,
And a switch 11.

In the above configuration, the matched filter 3, the multiplier 4, the averaging filter 7, the rectangular / polar coordinate converter 8, and the divider 9 are the same as those in the conventional configuration described above, and therefore, the same symbols are used. Description is omitted. The D-symbol differential detector 5 has the same configuration and functions as the above-described D-symbol differential detectors 5A and 5B, and a detailed description thereof will be omitted. Further, the input terminal 1 is connected to the matching filter 3 and each input of the switch 11.

In the second embodiment, two types of processing systems are provided from the input terminal 1 to the multiplier 4. The first processing system includes an input terminal 1, a matching filter 3, and a switch 1.
1 and a multiplier 4, and the second processing system includes an input terminal 1, a switch 11, and a multiplier 4. The difference between these two processing systems is whether the matched filter 3 is provided on the path or not, and the difference from the first embodiment is that the processing system is switched by the switch 11.

The switch 11 has a first terminal 11 A connected to the output of the matched filter 11, a second terminal 11 B connected to the input terminal 1, and a third terminal 11 C to the multiplier 4. This switch 11 switches to the first processing system which inputs the output of the matched filter 3 and outputs it to the multiplier 4 when the estimation accuracy becomes higher when the matched filter 3 is applied, and the switch 11 does not apply the matched filter 3. Is switched to the second processing system which inputs the received signal directly from the input terminal 1 and outputs it to the multiplier 4 when the estimation accuracy becomes higher.

Next, the operation will be described. In the configuration shown in FIG. 4, first, the input received signal is applied to the first processing system input to the multiplier 4 through the matched filter 3 and the matched filter 3 in the same manner as in the first embodiment. And a second processing system that is directly input from the input terminal 1 to the multiplier 4. Then, based on the transmission path impulse response estimated when the matched filter 3 is generated, the switch 11 is used to select a signal of the two systems that is expected to have higher estimation accuracy.

Next, the selected signal is multiplied by a multi-level modulation M in a multiplier 4. As a result, the modulation component is removed, and a carrier component having phase information is extracted. Subsequently, D-symbol differential detection is performed in the delay detector 5, and information on a phase change between D symbols is detected. Further, the information is averaged by the averaging filter 7, and as a result, the influence of noise is reduced. afterwards,
The averaged signal is converted from rectangular coordinates to polar coordinates by a coordinate converter 8. Finally, the divider 9 divides the information on the phase change between the D symbols by the modulation multi-level number M and the number D of the differential detection symbols to obtain the phase change between one symbol, that is, the frequency error.

Here, the operation of the switch 11 will be described in more detail. FIG. 5 is a diagram illustrating an example of a transmission path impulse response for which a frequency error cannot be estimated. As described above, when estimating a frequency error in a transmission path on which intersymbol interference occurs, the frequency error may not be estimated depending on the state of the transmission path. For example, under the transmission path as shown in FIG. 5, the frequency error cannot be estimated unless processing such as the matched filter 3 is performed.

Therefore, in the second embodiment, the transmission path impulse response which greatly affects the estimation of the frequency error is observed, and the transmission path impulse response is desirably applied to the matched filter 3 as shown in FIG. Denotes a processing system including the matched filter 3 (first processing system), and in other cases, a processing system not including the matched filter 3 (second processing system)
Is selected by the switch 11, high estimation accuracy can be realized even if any intersymbol interference occurs.

The criteria for selecting the two processing systems in the switch 11 are not limited to the transmission path impulse response described above, and the switch 11 can be switched according to other criteria arbitrarily set by the user. You may. In this case, a switching signal is given by a control mechanism outside the frequency error estimating circuit 1B.

Since the frequency error estimating circuit 1B detects the information on the phase change between the D symbols by using the delay detection, the frequency error estimating circuit 1B has the same function as the first embodiment. Can be extended.

As described above, according to the second embodiment, either the signal obtained by applying the matched filter 3 to the received signal or the received signal not applied by the matched filter 3 is switched by the switch 11.
, A signal having a higher estimation accuracy is selected according to the state of the intersymbol interference, so that a frequency error with a higher estimation accuracy can be obtained even if any intersymbol interference occurs. .

Further, since the delay detection is used to detect the information of the phase change, more accurate phase information can be obtained, and the estimation accuracy is improved. Further, by using a plurality of frequency error estimating circuits 1B for the delay detection waveform,
The present invention can be extended to a multiple open-loop frequency error estimating circuit that simultaneously realizes high estimation accuracy and a wide pull-in range.

Embodiment 3 By the way, the first embodiment described above
In the second and third embodiments, the input received signal is divided into two systems. However, the present invention is not limited to this. The frequency error can be reduced by only one system including a matched filter as in the third embodiment described below. The estimation may be performed to increase the estimation accuracy.

First, the configuration will be described. FIG. 6 is a block diagram showing a configuration example of the frequency error estimating circuit according to the third embodiment of the present invention. 6, reference numeral 1C denotes a frequency error estimating circuit according to the third embodiment. The frequency error estimating circuit 1C includes a matched filter 3, a multiplier 4, a D symbol delay detector 5, an averaging filter 7, a rectangular / polar coordinate converter 8, and a divider 9, as shown in FIG. Have.

In the above configuration, the matching filter 3, the multiplier 4, the averaging filter 7, the rectangular / polar coordinate converter 8, and the divider 9 are the same as those in the conventional configuration described above, and therefore, the same symbols are used. Description is omitted. Further, the D-symbol differential detector 5 has the same configuration and function as in the above-described second embodiment, and a detailed description thereof will be omitted. Therefore, the input terminal 1 is connected only to the input of the matched filter 3.

Next, the operation will be described. In the configuration shown in FIG. 6, first, the received signal is filtered by the matched filter 3 and then input to the multiplier 4. Subsequently, after the signal is multiplied by M in the multiplier 4, the delay detector 5
Is subjected to differential detection. As a result, phase change information between D symbols is extracted. Next, information averaging is performed by the averaging filter 7 to reduce the influence of noise. After that, the phase information is divided by the modulation multi-level number M and the differential detection symbol number D, and a frequency error is detected.

Since the frequency error estimating circuit 1C detects the information on the phase change between the D symbols by using the delay detection, the multiple open loop type frequency error estimating circuit is used in the same manner as in the first embodiment. Can be extended to circuits.

As described above, according to the third embodiment, since the frequency error is estimated using only the output of the matched filter 3, the estimation accuracy is higher than in the first and second embodiments. Is deteriorated, but since the information of the phase change is obtained by the differential detection, the estimation error can be reduced as compared with the conventional frequency error estimation circuit. Further, by using a plurality of the frequency error estimating circuits 1C for the delay detection waveform, it is possible to extend the frequency error estimating circuit to a multiple open loop type that simultaneously realizes high estimation accuracy and a wide pull-in range.

Embodiment 4 By the way, the first embodiment described above
In the above, the phase information was extracted by applying the matched filter 3 to the received signal. However, the present invention is not limited to this.
As in the fourth embodiment described below, phase information may be extracted by applying a fixed filter having a fixed tap coefficient.

First, the configuration will be described. FIG. 7 is a block diagram showing a configuration example of a frequency error estimating circuit according to Embodiment 4 of the present invention. In FIG. 7, 1D indicates a frequency error estimating circuit according to the fourth embodiment. This frequency error estimating circuit 1D includes, for example, multipliers 4A and 4B, D symbol delay detectors 5A and 5B, an adder 6, an averaging filter 7, a rectangular / polar coordinate converter 8, and a divider as shown in FIG. 9 and a fixed filter 12. The fixed filter 12 is a filter having a fixed value tap coefficient set in advance based on expected transmission path characteristics.

In the above configuration, the multipliers 4A and 4B, the D-symbol delay detectors 5A and 5B, the adder 6, the averaging filter 7, the rectangular / polar coordinate converter 8, and the divider 9 are implemented as described above. Since the configuration is the same as that of the first embodiment, the description is omitted using the same reference numerals. The input terminal 1 is connected to the fixed filter 12 and each input of the multiplier 4B.

Also in the fourth embodiment, the first embodiment is used.
Similarly, the two types of processing systems from the input terminal 1 to the averaging filter 7 are provided. The first processing system includes an input terminal 1, a fixed filter 12, a multiplier 4A, a D symbol delay detector 5A, an adder 6, and an averaging filter 7, and the second processing system includes an input terminal 1 , Multiplier 4B,
It comprises a D symbol differential detector 5B, an adder 6, and an averaging filter 7. The difference between these two processing systems is whether the fixed filter 12 is provided on the path or not.

Next, the operation will be described. In the configuration shown in FIG. 7, the received signal is first divided into two signals as in the first embodiment, and one of the signals is directly input to the multiplier 4B. The other signal is subjected to a fixed filter 12, and the output of the filter is input to the multiplier 4A. Here, the fixed filter 12 is different from the above-described matched filter 3 that actually estimates the transmission path characteristics and determines the tap coefficient based on the estimated value.

The subsequent processing is the same as in the first embodiment. That is, the signal that has passed through the fixed filter 12 and the signal that has not passed through the filter are subjected to M-multiplication and D-symbol delay detection, and information on the phase change between D symbols is obtained for each signal. Two pieces of information are combined. Next, information averaging is performed by the averaging filter 7 to reduce the influence of noise. Thereafter, the averaged signal is subjected to coordinate transformation from rectangular coordinates to polar coordinates. Finally, the information on the phase change is divided by the modulation multilevel number M and the differential detection symbol number D, and a frequency error is obtained.

Since the frequency error estimating circuit 1D detects the information on the phase change between the D symbols by using the delay detection, the multiple open loop type frequency error estimating method is performed in the same manner as in the first embodiment. Can be extended to circuits.

As described above, according to the fourth embodiment, two systems, the first processing system for passing the input received signal through fixed filter 12 and the second processing system not passing the fixed filter, are used. After the information of the phase change is detected at the same time using the two signals, the two phase information are combined, so that high estimation accuracy can be maintained regardless of the characteristics of the transmission path.

In this case, since the fixed filter 12 is used instead of the matched filter 3, the estimation accuracy is inferior to that of the first embodiment.
Since the transmission path estimation is not used to determine the tap coefficient of, the increase in the hardware scale can be suppressed as a whole configuration.

Further, by detecting a phase change using differential detection, more accurate phase information can be obtained, and the estimation accuracy can be improved. In addition, by using a plurality of the frequency error estimating circuits 1D for the delayed detection waveform, it is possible to extend the frequency error estimating circuit to a multiple open loop type frequency error estimating circuit that simultaneously realizes a high estimation accuracy and a wide pull-in range.

Embodiment 5 By the way, the second embodiment described above.
In the above, the phase information was extracted by applying the matched filter 3 to the received signal. However, the present invention is not limited to this.
As in the fifth embodiment described below, phase information may be extracted by applying a fixed filter having a fixed tap coefficient.

First, the configuration will be described. FIG. 8 is a block diagram showing one configuration example of the frequency error estimating circuit according to the fifth embodiment of the present invention. 8, reference numeral 1E denotes a frequency error estimating circuit according to the fifth embodiment. This frequency error estimating circuit 1E includes, for example, a multiplier 4, a D symbol differential detector 5, an averaging filter 7,
A quadrature / polar coordinate converter 8, a divider 9, a switch 11, and a fixed filter 12 are provided.

In the above configuration, the multiplier 4, the D symbol delay detector 5, the averaging filter 7, the rectangular / polar coordinate converter 8, the divider 9, and the switch 11 are the same as those in the second embodiment. Therefore, the description is omitted using the same reference numerals. The input terminal 1 is connected to each input of the fixed filter 12 and the switch 11.

In the fifth embodiment, two types of processing systems are provided from the input terminal 1 to the multiplier 4. The first processing system includes an input terminal 1, a fixed filter 12, a switch 11, and a multiplier 4, and the second processing system includes an input terminal 1, a switch 11, and a multiplier 4. . The difference between these two processing systems is whether the fixed filter 12 is provided in the path or not.
The difference from the fourth embodiment is that the processing system is switched by the switch 11.

Next, the operation will be described. In the configuration shown in FIG. 8, first, an input received signal is applied to a fixed filter 12 and a multiplier 4
And a second processing system which is directly input to the multiplier 4 without applying the fixed filter 12. The signal of the two systems, the one that is expected to have higher estimation accuracy, is the switch 11
Is selected using.

Thereafter, the same processing as in the second embodiment is performed. That is, the signal selected by the switch 11 is multiplied by the modulation multi-level number M in the multiplier 4 to remove the modulation component. As a result, a carrier component having phase information is extracted. Subsequently, D-symbol differential detection is performed in the delay detector 5, and information on a phase change between D symbols is detected. Further, the information is averaged by the averaging filter 7, thereby reducing the influence of noise.

Thereafter, the signal averaged by the coordinate converter 8 is converted from rectangular coordinates to polar coordinates. Finally, the divider 9 divides the information on the phase change between the D symbols by the modulation multi-level number M and the number D of the differential detection symbols to obtain the phase change between one symbol, that is, the frequency error.

Further, since the frequency error estimating circuit 1E detects the information on the phase change between D symbols by using the delay detection, the multiple open loop type frequency error estimating is performed in the same manner as in the first embodiment. Can be extended to circuits.

As described above, according to the fifth embodiment, either the signal obtained by applying the fixed filter 12 to the received signal or the received signal not applied by the fixed filter 12 is selected by the switch 11. The signal with the higher estimation accuracy is selected in accordance with the state of the intersymbol interference, so that a frequency error with a higher estimation accuracy can be obtained even if any intersymbol interference occurs.

In this case, since the fixed filter 12 is used instead of the matched filter 3, the estimation accuracy is inferior to that of the second embodiment described above.
Since the transmission path estimation is not used to determine the tap coefficient of, there is an effect that an increase in hardware scale can be suppressed as a whole configuration.

Further, since the delay detection is used to detect the information of the phase change, more accurate phase information can be obtained and the estimation accuracy is improved. Further, by using a plurality of frequency error estimating circuits 1E of the delay detection waveform,
The present invention can be extended to a multiple open-loop frequency error estimating circuit that simultaneously realizes high estimation accuracy and a wide pull-in range.

Embodiment 6 FIG. By the way, the third embodiment described above.
In the above, the phase information was extracted by applying the matched filter 3 to the received signal. However, the present invention is not limited to this.
As in the sixth embodiment described below, phase information may be extracted by applying a fixed filter having a fixed tap coefficient. In other words, Embodiments 4 and 5 described above
In the above, the input received signal is divided into two systems. However, the present invention is not limited to this, and the sixth embodiment described below is used.
As described above, the frequency error may be estimated by one system that applies the received signal to the fixed filter 12.

First, the configuration will be described. FIG. 9 is a block diagram showing a configuration example of the frequency error estimating circuit according to the sixth embodiment of the present invention. In FIG. 9, 1F indicates a frequency error estimating circuit according to the sixth embodiment. This frequency error estimating circuit 1F includes, for example, a multiplier 4, a D symbol differential detector 5, an averaging filter 7,
A quadrature / polar coordinate converter 8, a divider 9, and a fixed filter 12 are provided.

In the above configuration, the multiplier 4, the D symbol delay detector 5, the averaging filter 7, the rectangular / polar coordinate converter 8, the divider 9, and the fixed filter 12 are the same as those of the fifth embodiment. For the same reason, the description is omitted using the same reference numerals. The input terminal 1 is connected to the fixed filter 12
Connected only to the input.

Next, the operation will be described. In the configuration shown in FIG. 9, first, the received signal is filtered by the fixed filter 12 and then input to the multiplier 4. Subsequent steps are the same as in the third embodiment described above. Subsequently, the input signal is multiplied by M in the multiplier 4, and thereafter, the output of the multiplier 4 is subjected to delay detection in the delay detector 5. In this way, information on the phase change between D symbols is extracted. Next, information averaging is performed by the averaging filter 7 to reduce the influence of noise. Thereafter, the phase information averaged by the modulation multi-level number M and the differential detection symbol number D is divided, and a frequency error is detected.

Further, since the frequency error estimating circuit 1F detects the information on the phase change between D symbols by using the delay detection, the frequency error estimating circuit 1F can be applied to the multiple open loop type frequency error estimating circuit as in the first embodiment. Can be extended.

As described above, according to the sixth embodiment, since the frequency error is estimated using only the output of the fixed filter 12, the estimation accuracy is lower than that of the third embodiment. However, in this case, the matched filter 3
Instead of using the fixed filter 12, the increase in hardware scale can be suppressed as a whole configuration.

Further, by detecting a phase change using differential detection, more accurate phase information can be obtained and estimation accuracy can be improved. Further, by using a plurality of the frequency error estimating circuits 1F for the delayed detection waveform, it is possible to extend the frequency error estimating circuit to a multiple open loop type frequency error estimating circuit that simultaneously realizes a high estimation accuracy and a wide pull-in range.

Although the present invention has been described with reference to the first to sixth embodiments, various modifications can be made within the scope of the present invention, and these are not excluded from the scope of the present invention.

[0107]

As described above, according to the present invention, a received signal is filtered and then multiplied, and at the same time, the same received signal is also multiplied as it is, and phase change information is detected based on each multiplied signal. As a result, it is possible to select a higher estimation value with a higher estimation accuracy according to the state of intersymbol interference, thereby obtaining a frequency error with a higher estimation accuracy even if any intersymbol interference occurs. There is an effect that a frequency error estimating circuit that can be obtained is obtained.

According to the next invention, in the system that passes the matched filter and the system that does not pass the matched filter, the received signal is filtered by the matched filter in the system that passes the matched filter. There is an effect that a frequency error estimating circuit capable of obtaining a conversion capability can be obtained.

According to the next invention, in a system in which a fixed filter is passed and a system in which a fixed filter is not passed, a reception signal is filtered by a fixed filter having a fixed tap coefficient. This eliminates the need for estimating the transmission path characteristics required to obtain the frequency error, and provides an effect of obtaining a frequency error estimating circuit capable of reducing the hardware scale as compared with the case where a matched filter is used.

According to the next invention, the information of the phase change of the two systems is detected by the delay detection of the signal multiplied by the two systems, and the information of the phase change of the two systems is synthesized. It is possible to obtain the phase information, thereby providing an effect that a frequency error estimating circuit with improved estimation accuracy can be obtained.

According to the next invention, one of the received signal and the filtered received signal is selected, and one of the selected output signals is multiplied before detecting information on the phase change. Therefore, a signal having a higher estimation accuracy is selected according to the state of the intersymbol interference, thereby obtaining a frequency error estimating circuit capable of acquiring a frequency error with a higher estimation accuracy even if any intersymbol interference occurs. The effect is that it can be done.

According to the next invention, the phase change information is detected by delay detection of the multiplied signal, so that more accurate phase information can be obtained, thereby improving the frequency at which the estimation accuracy is improved. There is an effect that an error estimating circuit can be obtained.

According to the next invention, since the received signal is filtered, the filtered received signal is multiplied, and then delayed detection is performed to detect the phase change information, so that more accurate phase information can be obtained. Is obtained, whereby the frequency error estimating circuit with improved estimation accuracy is obtained.

According to the next invention, since the received signal is filtered by the matched filter, it is possible to obtain a frequency error estimating circuit capable of obtaining a better equalization capability in the state of intersymbol interference. .

According to the next invention, the received signal is filtered by the fixed filter having the fixed tap coefficient, so that it is not necessary to estimate the transmission path characteristics necessary for obtaining the matched filter, and the matched filter can be used. An effect is obtained that a frequency error estimating circuit capable of reducing the hardware scale can be obtained as compared with the case where it is used.

According to the next invention, the estimation of the frequency error based on the signal subjected to the matched filter to the received signal and the estimation based on the received signal not subjected to the matched filter are performed at the same time. , It is possible to select an estimated value with a higher estimation accuracy, thereby obtaining a frequency error with a higher estimation accuracy even if any intersymbol interference occurs. Further, since the delay detection is used to detect the information of the phase change, more accurate phase information can be obtained, and an effect of obtaining a frequency error estimating circuit with improved estimation accuracy can be obtained.

According to the next invention, the information on the phase change detected by the pair of differential detectors is synthesized by the adder, so that the received signal is passed through a matched filter and the received signal is not passed. Without bias to either one of
There is an effect that a frequency error estimating circuit capable of obtaining more accurate phase information can be obtained.

According to the next invention, one of the signal obtained by subjecting the received signal to the matched filter and the received signal not subjected to the matched filter is selected by the switch, so that the estimation is performed according to the state of the intersymbol interference. The signal with the higher accuracy is selected, so that a frequency error with higher estimation accuracy can be obtained even if any intersymbol interference occurs. Further, since the delay detection is used to detect the information of the phase change, more accurate phase information can be obtained, and an effect of obtaining a frequency error estimating circuit with improved estimation accuracy can be obtained.

According to the next invention, the signal obtained by subjecting the received signal to the matching filter by the multiplier is multiplied, and the information of the phase change is detected from the multiplied signal by the delay detector. Can be used to detect a phase change, thereby providing an effect that a more accurate phase information can be obtained and a frequency error estimating circuit that can increase the estimation accuracy can be obtained.

According to the next invention, a fixed filter output obtained by applying a fixed filter having a fixed tap coefficient to a received signal is input from a first terminal, a received signal is input from a second terminal, and a pair of multipliers is input. Thus, the received signals respectively input to the first and second terminals are multiplied, and the information of the phase change is detected from the output signals multiplied by the corresponding pair of multipliers by the pair of delay detectors. Therefore, there is no need to estimate the transmission path characteristics necessary for obtaining a matched filter, and the hardware scale can be reduced.
Since the estimation of the frequency error based on the signal obtained by applying the fixed filter to the received signal and the estimation based on the received signal not applied with the fixed filter are performed at the same time, the one with higher estimation accuracy according to the state of intersymbol interference Can be selected to select the estimated value of, and thereby, a frequency error with high estimation accuracy can be obtained even if any intersymbol interference occurs.
By detecting the phase change using the differential detection, it is possible to obtain a frequency error estimating circuit capable of obtaining more accurate phase information and improving the estimation accuracy.

According to the next invention, since the information of the phase change detected by the pair of differential detectors is synthesized by the adder, the received signal is passed through a fixed filter and the received signal is not passed. Without bias to either one of
There is an effect that a frequency error estimating circuit capable of obtaining more accurate phase information can be obtained.

According to the next invention, a fixed filter output obtained by applying a fixed filter having a fixed tap coefficient to the received signal is input to the first terminal, and the received signal is input to the second terminal.
One of the first and second terminals is selected by the switch, the output signal selected by the switch is multiplied by the multiplier, and the information of the phase change is obtained from the multiplied output signal by the delay detector. Since the detection is performed, it is not necessary to estimate the transmission path characteristics necessary for obtaining a matched filter, and the hardware scale can be reduced.
Since either a signal obtained by applying a fixed filter to the received signal or a received signal not applied by the fixed filter can be selected by a switch, a signal having a higher estimation accuracy is selected according to the state of the intersymbol interference. Even if intersymbol interference occurs, a frequency error with high estimation accuracy can be obtained,
Further, since the delay detection is used to detect the information of the phase change, it is possible to obtain a more accurate phase information and to obtain a frequency error estimating circuit with improved estimation accuracy.

According to the next invention, a signal obtained by applying a fixed filter having a fixed tap coefficient to a received signal by a multiplier is multiplied, and information on a phase change is detected from the multiplied signal by a delay detector. As a result, it is not necessary to estimate the transmission path characteristics necessary for obtaining a matched filter, the hardware scale can be reduced, and by detecting a phase change using delay detection, This has the effect of obtaining a frequency error estimating circuit that can obtain more accurate phase information and increase the estimation accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a frequency error estimation circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a multiple open-loop frequency error estimation circuit according to the first embodiment;

FIG. 3 is a diagram illustrating a method of removing frequency uncertainty in a multiple open loop type frequency error estimation circuit.

FIG. 4 is a block diagram illustrating a configuration example of a frequency error estimating circuit according to a second embodiment of the present invention;

FIG. 5 is a diagram illustrating an example of a transmission path impulse response from which a frequency error cannot be estimated.

FIG. 6 is a block diagram illustrating a configuration example of a frequency error estimation circuit according to a third embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration example of a frequency error estimation circuit according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration example of a frequency error estimating circuit according to a fifth embodiment of the present invention.

FIG. 9 is a block diagram illustrating a configuration example of a frequency error estimating circuit according to a sixth embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration example of a conventional frequency error estimation circuit.

[Explanation of symbols]

1 input terminal, 2 output terminal, 3 matching filter, 4,
4A, 4B multiplier, 5, 5A, 5B D symbol differential detector, 6 adder, 7 averaging filter, 8 rectangular / polar coordinate converter, 9 divider, 10 selector, 11 switch, 11A, 41 1st terminal , 11B, 42 second terminal, 12 fixed filter.

Claims (17)

[Claims] 1. A frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal, wherein first frequency multiplying means for filtering and multiplying the received signal; A frequency error estimating circuit comprising: a second multiplying means for multiplying; and a phase change detecting means for detecting information on a phase change based on the signals multiplied by the first and second multiplying means. . 2. The frequency error estimating circuit according to claim 1, wherein said first multiplying means has a matched filter for filtering a received signal. 3. The frequency error estimating circuit according to claim 1, wherein the first multiplier has a fixed filter for fixing a tap coefficient and filtering a received signal. 4. The phase change detecting means detects information on phase changes in two systems by delay detection of the signals multiplied by the first and second multiplying means, and outputs the information on phase changes in the two systems. 4. The frequency error estimating circuit according to claim 1, wherein the frequency error is estimated. 5. A frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal, wherein: a filtering means for filtering the received signal; Selecting means for selecting and outputting one of the received signals; multiplying means for multiplying one of the output signals selected by the selecting means; and information on a phase change based on the signal multiplied by the multiplying means. A frequency change estimating circuit, comprising: 6. The frequency error estimating circuit according to claim 5, wherein said phase change detecting means detects phase change information by delay detection of the signal multiplied by said multiplying means. 7. A frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal, a filtering means for filtering the received signal, and a multiplication of the received signal filtered by the filtering means. A frequency error estimating circuit, comprising: a multiplying unit that performs a delay detection on the signal multiplied by the multiplying unit to detect phase change information. 8. The frequency error estimating circuit according to claim 5, wherein said filtering means has a matched filter for filtering a received signal. 9. The frequency error estimating circuit according to claim 5, wherein said filtering means has a fixed filter for fixing a tap coefficient and filtering a received signal. 10. A frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal, wherein: a first terminal for inputting a matched filter output obtained by applying a matched filter to the received signal; A second terminal for inputting a received signal; a pair of frequency multipliers for multiplying the received signal input to the first and second terminals; information on a phase change from an output signal multiplied by each of the pair of frequency multipliers And a pair of differential detectors for detecting a frequency error. 11. The frequency error estimating circuit according to claim 10, further comprising an adder for synthesizing information on the phase change detected by each of the pair of differential detectors. 12. A frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal, a first terminal receiving a matched filter output obtained by applying a matched filter to the received signal, A second terminal for inputting a received signal; a switch for selecting one of the first and second terminals; a multiplier for multiplying an output signal selected by the switch; and a multiplier for the multiplier A delay detector for detecting information on a phase change from the output signal thus obtained, and a frequency error estimating circuit comprising: 13. A frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal, comprising: a multiplier for multiplying a signal obtained by applying a matched filter to the received signal; A delay detector for detecting phase change information from the multiplied signal; and a frequency error estimating circuit comprising: 14. A frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal, wherein a fixed filter output obtained by applying a fixed filter having a fixed tap coefficient to the received signal is input. A first terminal, a second terminal for inputting the received signal, a pair of multipliers for multiplying the received signals input to the first and second terminals, and an output multiplied by the pair of multipliers, respectively. A frequency error estimating circuit, comprising: a pair of differential detectors for detecting phase change information from a signal. 15. The frequency error estimating circuit according to claim 14, further comprising an adder for synthesizing information on a phase change detected by each of said pair of differential detectors. 16. A frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal, wherein a fixed filter output obtained by applying a fixed filter having a fixed tap coefficient to the received signal is input. A first terminal, a second terminal for inputting the reception signal, a switch for selecting one of the first and second terminals, and a multiplier for multiplying an output signal selected by the switch. And a delay detector for detecting information on a phase change from the output signal multiplied by the multiplier. 17. A frequency error estimating circuit for estimating a frequency error between a local oscillation frequency of a receiver and a carrier frequency of a received signal, wherein the multiplier multiplies a signal obtained by applying a fixed filter having a fixed tap coefficient to the received signal. And a delay detector for detecting information on a phase change from the signal multiplied by the multiplier.