JP2000013448A - Transport stream demultiplexer provided with buffer and detection record for every packet and made into fifo structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify transport stream demultiplexer processing, to reduce circuit scale, to accelerate a section filtering operation and the PID detection of a PAT, and to generate the clock for decoding MPEG 2 by setting a fine controlled frequency to a certain central frequency. SOLUTION: This demultiplexer is composed of packet buffers 107, 109 and 111 of 188 bytes and status registers 108, 110 and 112 including header byte detection flag, PID validity flag, PID index number, water level gauge full flag and packet flag. These components can be accessed in the unit of a packet as one group and processed in the manner of FIFO operation by write and read packet counters 114-117. The PID register for PAT is provided for accelerating the initial synchronization of a channel. In order to accelerate section filtering operation, a circuit exclusive for DMA transfer and filtering is used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transport stream data demultiplexer device used in digital televisions and the like.

[0002]

2. Description of the Related Art A conventional transport stream demultiplexer transfers byte-aligned data of continuously received bytes or bits to a FIFO, and reads and analyzes the data in a register window of bytes and words. The method was common.

[0003]

SUMMARY OF THE INVENTION At first glance, demultiplexing of a transport stream using FIFO is performed at first glance.
Although it looks like a suitable processing method, both necessary and unnecessary packets are unconditionally stored in the FIFO.
You have to work to discard 88 bytes. At this time, in order to smoothly detect the header and PID of the next packet, it is necessary to read and execute the packet in byte units, and it takes time to remove the packet.

[0004] Also, due to the nature of the transport packet, it is necessary to randomly access important data for packet analysis from the first byte to around 40 bytes. It takes time to read the data into the memory of the host and analyze it. Alternatively, there is a method in which a special register is prepared in advance and only necessary data is cut out.
The circuit scale tends to be large.

Furthermore, when a new packet is to be taken in according to a change in the channel or the like, it is necessary to first take in a packet of only a PAT (program association table) and prepare for analysis. Not adopted. Therefore, PA
In order to detect only T, it was necessary to disable all of the 48 PID registers, re-enable after detecting the PAT, and the load on the CPU was heavy.

When the FIFO memory is read, the pointer cannot be returned to its original state. Therefore, there is a problem that flexibility is increased when different transfer processing, section filtering processing, and the like are performed on the same data.

[0007]

According to the present invention, a buffer in units of packets and a status flag register for holding an analysis result of a pre-processing stage thereof are used instead of a FIFO as an input buffer. FIFO for each packet
It uses a circuit to select the earliest received packet buffer and status flag register.

In the present invention, a plurality of packet buffers and a status flag register are used. The packet buffer uses a dual-port type memory having separate addresses and data for input and output, and has a structure in which 188-byte packet data can be randomly accessed from the host CPU.

The packet buffer stores input transport data in order from the first byte. The status flag includes the validity of the header byte, the PID detection result,
Water level meter full flag indicating how many bytes are stored in the buffer,
A packet full flag indicating whether the entire packet has been taken is provided.

When the host CPU completes the analysis and transfer of the 188-byte packet data, a mechanism is provided for discarding the current packet buffer and status flag and analyzing the data and status of the next plane.

Further, in order to smoothly synchronize the packets when the channel is changed, a PID register dedicated to the PAT is provided, and only the PAT packet is fetched. After detection, a circuit is used which invalidates the PID of the PAT and shifts to a normal PID detection mode.

Since 188-byte data is always randomly accessible, filter data stored in another area and section data stored in a packet buffer are continuously read using a DMA transfer circuit, and section filtering is performed. , And hold the result as a status flag.

Further, a PLL circuit and a PWM circuit are combined to realize a fine frequency generation circuit centered on 27 MHZ used as a reference signal for MPEG2 processing.
Basically, two VCO circuits having the same characteristics are used.
The VCO operated by the PLL circuit has a fundamental frequency of 27 MHz.
Is generated, and a value obtained by adding a PWM pulse as fine adjustment data to the VCO voltage of the PLL circuit is applied to the VCO operated by the PWM circuit. By doing so, a very fine frequency near 27 MHZ is generated.

[0014]

The validity of a packet, ie, header and PID
After performing the detection, if it is determined that the packet is unnecessary, all 188 bytes are discarded from the buffer,
Since new data is stored, only valid data is stored in the buffer for the host CPU, so that there is no waste in processing. Also, it is rational because the buffer on multiple sides can always be used to the maximum.

First, a valid packet and its detection result are stored in a randomly accessible buffer and status register, and when the packet becomes full, the same processing is performed on the next packet and status register and stored. CP
Since U can concentrate on the packet to be processed and its status, it is not necessary to worry about the timing of detecting the next packet. Therefore, the analysis software is simplified.

Since the corresponding packet can be randomly accessed, a circuit for specially holding a splice countdown, an error indicator, and the like is not required, so that the circuit scale can be reduced.

When the analysis of the current packet is completed, the packet is simply operated by operating the packet pointer for the analysis of the next packet, so that the packet can be removed instantaneously.

Since a PID for PAT detection is provided for exclusive use, PAT information can be fetched first at the time of channel switching, and thereafter, by shifting to normal PID detection, unnecessary PID detection can be performed. Eliminates rewriting time and significantly reduces overhead.

Since the PSI section filtering processing using the DMA transfer is performed, the processing time can be significantly reduced and the circuit size can be reduced.

By combining a PLL circuit and a PWM circuit to generate a fine tuning frequency of 27 MHZ, the reference frequency of the PLL circuit can be increased, and the low-pass filter circuit can be simplified. Further, since a frequency near 27 MHZ is generated by the PLL circuit and PWM is used for fine adjustment, the 27 MHZ control algorithm can be simplified. Further, by providing fine adjustment data of about 16 bits in the PWM circuit, the frequency can be adjusted very finely. And
Since the cycle frequency of the PWM circuit can be increased,
The low-pass filter circuit at the subsequent stage can be easily designed.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The contents of the present invention and a circuit for realizing the same will be described below in detail with reference to the drawings. Figure 1 shows the FIFO using multiple packet buffers and status registers.
FIG. 4 is a circuit diagram of an input stage of a transport stream to be structurally processed. The serial data of the transport is converted into 8-bit parallel data, and the parallel data is directly input to the header synchronization circuit (101). And 0x
When 47 header bytes are detected and the number of times for synchronization set in advance is satisfied, the buffer address + timing generation circuit (102) at the next stage is started. (10
2) The buffer address of the circuit is counted up from 0 to 187, and is repeated from 0. Further, it generates timing signals such as header capture and PID capture.

The header detection circuit (103) becomes 1 when the header is 0x47, and becomes 0 otherwise. When the PID detection is completed by the PID detection circuit (104) with success, the PID valid flag is set to 1 and the index number at that time is held. Water level detection circuit (10
5) Compare the preset water level meter with the number of bytes input so far, and when the water level is full,
Set to 1. The packet full detection circuit (106) is 18
It becomes 1 when 8 bytes are input. The detection result is held in the status register.

The 188-byte packet and the detected status flag operate as one group. For example, packet buffer 1 of (107) and status register 1 of (108). Writing to this group is performed by writing packet pointer (11
Manage in 5). This write pointer specifies one group of packet buffer + status with 2 bits. Only the packet whose PID is valid is held, and when the packet end signal comes, the packet write control circuit (114) operates to increment the write packet pointer.

If a valid PID cannot be detected, the current status flag is cleared, the write packet pointer is kept as it is, the data is fetched again into the same packet buffer, and the status register is recorded again. At this time, no control signal is output from the packet write control circuit. When the packet buffers on the three sides are full, before the transport buffer is full, it notifies the preceding circuit that the transport input circuit is being prepared, and all the packets are full, and the input is completed. Ban.

The CPU can read the packet buffer and the status register specified by the 2-bit read packet pointer (117). The selection of the data is executed by the bus MUX (113). At reset, both the write packet pointer and the read packet pointer are 0. When the data analysis and transfer are completed, the packet read flash circuit (11
In 6), the read packet pointer is incremented. By doing so, a FIFO configuration for each packet is realized, and the processing can be rationally performed.

FIG. 2 is a flow chart of interrupt generation when one packet buffer and status register are selected. A header byte detection flag (202) is set at the head position of the packet buffer (201).
Thereafter, PID detection is executed, and the PID valid flag (2
03) and a PID index number (204).
The water level meter full flag (205) becomes 1 when bytes equal to or larger than a predetermined water level value are input to the buffer.
When the packet input reaches the maximum value of 188 bytes, the packet full (206) flag becomes 1.

Then, the interrupt selection enable FF (2
07) One or more interrupts are enabled by the circuit, and one signal is obtained by the IRQ selection circuit (208), and the packet enable interrupt flag is finally set to 1 by the interrupt enable (209) flag and the interrupt enable circuit (210). To notify the host CPU.

FIG. 3 shows a detection circuit including PAT_PID and normal PID. In the conventional PID detection, one comparison circuit is provided in one PID register for speeding up the processing, so that the circuit configuration is considerably large. In the present invention, the PID register has a structure such as register output for an address so as to access a RAM or a register file. By doing so, the circuit configuration was reduced. The reason is that the history of the current packet can always be held in the status register, so that the PID detection does not require a particularly high speed.

When the PID position detection signal becomes 1, the data at that time is held in the PID data holding register (303), and at the same time, the address counter (301) is reset. Also, the PID valid flag is cleared. PAT
When the _PID register (305) is set and the PAT enable (304) flag is 1, only the PAT_PID is selected by the multiplexer circuit (306), and PID detection is executed by the comparison decision circuit (308).

If PAT_PID is equal to the input PID data, the PID valid flag (309) is set to 1
And the PAT enable is reset at the same time. At this time, a number specially assigned to PAT_PID is set in the PID index register (310). When PAT_PID enable is zero, normal PID detection is performed.

In normal PID detection, every time the address counter is incremented from 0, data corresponding to the address is fetched from the PID register file and compared. At this time, the comparison decision is valid only when the enable is 1. The enable selection circuit of (307) is PAT
Used to select whether to detect PID or other PID. P
When the ID address is zero, detection of PCR_PID is executed. If they match, the detection is canceled immediately, the PID valid flag is set to 1, and the address at that time is stored in the PID index register. If, after checking all PIDs, they do not match at all, detection is terminated and P
Set the ID valid flag to 0.

FIG. 4A shows an example of section data included in a PSI packet of a transport stream. In this example, a PSI packet (401) in the case of only the payload is shown. The first four bytes are the TS header part, followed by byte data indicating a pointer field, which specifies the start position of the section data.

FIG. 4B shows an example of a memory storing a mask byte in the upper 8 bits of a 16-bit width and a filter byte in the lower 8 bits for filtering the section data. In the memory (402), mask bytes and filter bytes are previously stored in word units, and individual bytes of the section data can be filtered.

In section filtering, first, XOR is performed on the section data and the filter byte, and then, when the result of ANDing with the mask byte is zero,
Record this section in external memory. Discard this section if it is non-zero. All section data, that is, section data 0 to section data 14
And the result is output from the match flag of (415).

FIG. 4C shows a section filtering circuit using DMA transfer. Normal DMA transfer includes a byte counter (404) for specifying the number of bytes to be transferred, a source address 1 (405), and a destination address.
(406) is used.

The byte counter specifies the total number of filtering bytes of the section data. It is decremented each time a section byte is checked. When the value of the byte counter becomes zero, the (407) circuit becomes one, and the DMA transfer-based section filtering ends.

The source address 1 is an address for taking in byte data of the section data area (408), and is incremented each time it is taken in. The read section data is held in the section data register (409).

The source address 2 (406) is for taking in 16-bit data of the filter data area (410). The lower byte is in the filter byte register (411) and the upper byte is in the mask byte register (412). Is stored. The section data and the filter data are compared by the XOR circuit (413),
The coincidence is detected by the D-OR circuit (414).

When section filtering by DMA transfer starts, the match flag (415) is set to 1. If any discrepancy occurs even once, it will be reset,
finish. After the DMA section filtering process is completed, the match flag of the section filtering is set.
Checked by host CPU.

FIG. 5 is a diagram showing 27 MH with a PLL and a PWM circuit.
FIG. 3 is a schematic diagram of a Z-center frequency fine-tuning transmission circuit. The center frequency can be set to other than 27 MHZ. The PLL reference counter (502) divides the frequency of the crystal oscillator,
For generating a reference clock, for example, 4
In the case of MHZ crystal, 1 MHZ can be set. In this case, the frequency division ratio of the selector counter (501) of the PLL is 27.

The selector and reference clocks are P
DO: Compared by the phase comparator (503), integrated by the low-pass filter circuit (504), and converted by the 1/1 amplifier (505) as the voltage of the VCO for PLL (506).
Applied. The PLL VCO transmits 27 MHZ, and its clock is fed back to the PLL selector counter.

The 16-bit fine frequency data is held in a fine frequency register (507), converted into a 1/0 duty waveform by a PWM pulse generating circuit (508), and converted into a 27 MHZ voltage by an adding circuit (509). Is added. At this time, the pulse waveform is integrated by a low-pass filter and applied to the PWM VCO circuit.

Originally, the PLL VCO circuit and the PWM VCO circuit are designed to have the same characteristics.
For the center voltage of 27MHZ generated by the PLL circuit,
The transmission frequency is changed by the fine adjustment voltage.

FIG. 6A is a detailed diagram of the frequency fine adjustment circuit section. The PWM pulse generation circuit (508) outputs pulses in high and low periods and a pulse for generating a high impedance period. These signals are converted by a ternary conversion circuit (601) into signals having three levels of high, low, and high impedance.

FIG. 6B is a reference example of a pulse waveform generated from the PWM circuit. 16x data, 0x
8000 is the central value. High impedance is always output at the center value, and the 27 MHZ voltage
02) to the low-pass filter circuit.

When the value is larger than 0x8000, a high level is output at a rate of 1 / 32K, and the finely adjusted high pulse voltage is applied to the low-pass filter together with the 27 MHZ voltage through the resistor (603). 0x8002
In the case of the above, the high pulse voltage for two 32K is 27M.
It is added to the HZ voltage.

On the other hand, if 1 less than 0x8000,
Low pulse voltage is 1 / 32K like 0x7FFF
, And are applied to the PWM VCO circuit. In the case of 0x7FFE, two 32K low pulse voltages are drawn.

Basically, since the cycle frequency of the PWM pulse can be designed to be high internally, a low-pass filter (5
10) can be designed easily. Further, since the PLL reference frequency is a prime frequency such as 27 MHZ, its reference clock cycle can be set high, thereby facilitating the design of the internal low-pass filter (504).

Since the frequency of 27 MHZ requires fine adjustment in units of Hertz, it is difficult to realize it by using only the PLL circuit because the reference clock becomes long. In addition, a circuit configuration using only PWM requires extra time to search for a center frequency of 27 MHZ.
If this PLL and PWM mixing circuit is used, 27 MHZ
The neighborhood can be set immediately, and the fine adjustment can be easily managed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an input stage of a transport stream to be processed in a FIFO structure using a plurality of packet buffers and status registers.

FIG. 2 is a flowchart of interrupt generation when one packet buffer and a status register are selected.

FIG. 3 is a detection circuit including a PAT_PID and a normal PID.

FIG. 4A is an example of section data included in a PSI packet of a transport stream.
(B) is an example of a memory that stores a mask byte in the upper 8 bits of a 16-bit width and a filter byte in the lower 8 bits in order to filter the section data. (C) is a section filtering circuit using DMA transfer.

FIG. 5 is a schematic diagram of a frequency fine-tuning oscillation circuit centered on 27 MHZ by a PLL and a PWM circuit.

FIG. 6A is a detailed diagram of a frequency fine adjustment circuit unit.
(B) is a reference example of the pulse waveform generated from the PWM circuit.

[Explanation of symbols]

 101 Header Synchronization Circuit 102 Buffer Address + Timing Generation Circuit 103 Header Detection Circuit 104 PID Detection Circuit 105 Water Level Detection Circuit 106 Packet Full Detection Circuit 107 188 Byte Packet Buffer 1 108 Status Register 1 109 188 Byte Packet Buffer 2 110 Status Register 2 111 188 byte packet buffer 3 112 status register 3 113 bus MUX 114 packet write control circuit 115 write packet pointer 116 packet read flash circuit 117 read packet pointer 201 transport stream packet buffer 202 header byte detection flag 203 PID valid flag 204 PID index number 205 Water level gauge Flag 206 packet full flag 207 interrupt selection enable FF 208 IRQ selection circuit 209 interrupt enable bit 210 interrupt enable circuit 301 address counter 302 PID register file + enable bit 303 PID data holding register 304 PAT enable 305 PAT_PID register 306 multiplexer 307 enable selection circuit 308 Comparison decision circuit 309 PID valid flag 310 PID index register 401 Example of PSI packet buffer 402 Example of section filter data 403 DMA transfer circuit 404 Byte counter 405 Source address 1 406 Source address 2 407 Byte counter zero detection circuit 408 Section data area Pa Packet buffer 409 Filter data area-Built-in memory 410 Section register 411 Filter byte register 412 Mask byte register 413 XOR circuit 414 AND-OR circuit 415 Match flag 501 PLL selector counter 502 PLL reference counter 503 Phase comparator 504 Low-pass filter circuit 505 One pair 1 voltage amplifier 506 PLL voltage control oscillator 507 Fine frequency register 508 PWM pulse generation circuit 509 Addition circuit 510 Low pass filter circuit 511 VCO circuit for PWM 601 Ternary conversion circuit 602 Resistance 603 Resistance

Claims (11)

[Claims] 1. Speeding up packet analysis by preparing a plurality of packet buffers that can be randomly accessed for reception of a transport stream and a plurality of status flags for recording the analysis results of the packets, and making them into a FIFO structure in packet units Transport stream demultiplexer device that enables 2. The apparatus according to claim 1, wherein a necessary transport packet and an unnecessary transport packet are detected in real time, and when the unnecessary packet is stored in a buffer, the packet data and the status flag are added to the last packet. A transport stream demultiplexer device having a mechanism for emptying when a byte is input and restoring from the next packet. 3. A transport stream demultiplexer device which uses a circuit for selecting a part or a combination of a plurality of bits of the status flag of claim 1 to generate an interrupt and facilitate analysis. 4. The status flag according to claim 3, wherein
ID (program identification data)
Device that has the detection result and its index number. 5. The apparatus according to claim 3, wherein the status flag has a flag indicating a water gauge full state when data is stored in a packet buffer at a level higher than a preset water gauge. 6. An apparatus having a packet full status flag as the status flag according to claim 3, when the entire 188-byte packet is stored in the packet buffer. 7. The apparatus according to claim 3, wherein the header detection flag is set to 1 when a header byte is detected in the first byte of the packet. 8. A PID register for detecting the validity of a packet in the apparatus according to claim 1, wherein the PID register has a memory structure to be accessed in address units, and the PID register takes a plurality of clocks.
A transport stream demultiplexer device that adopts a method of detecting the size of the circuit and greatly reduces the size of the circuit. 9. The PID detection circuit according to claim 8, wherein PAT_P
An ID (program association table) register is added, and when the PID data is valid, the comparison of the other PID registers is invalidated and detected.
A transport stream demultiplexer device that simplifies PID detection processing when a channel is changed by adopting a method in which once the PAT_PID data is detected, the PAT_PID data is immediately invalidated, and normal PID detection is performed. 10. A DMA transfer is performed on PSI (program specific information) section data stored in the packet buffer of claim 1 and filter data previously stored in a separate area, wherein the section data is in units of 1 byte and the filter data is 2 bytes. A transport stream demultiplexer that reads in bytes and performs section filtering for a predetermined number of bytes. 11. A fine-tuning frequency generating circuit having a certain center frequency, using a voltage-controlled oscillator (510) having the same characteristics as a voltage-controlled oscillator (506) of a PLL circuit unit for generating a center frequency, using fine-tuning frequency data. From the value of the register (507) holding the PWM pulse circuit (50
8) Generate three types of fine-adjustment pulse waveforms of high, low and high impedance, add to the voltage of the center frequency generated by the PLL circuit, and shape the voltage by the low-pass filter circuit (509) to obtain a voltage-controlled oscillator (51
A device that realizes fine frequency transmission with respect to the center frequency by adding to (0).