JP2000013142A - Voltage control piezoelectric oscillator - Google Patents

Voltage control piezoelectric oscillator

Info

Publication number
JP2000013142A
JP2000013142A JP10178514A JP17851498A JP2000013142A JP 2000013142 A JP2000013142 A JP 2000013142A JP 10178514 A JP10178514 A JP 10178514A JP 17851498 A JP17851498 A JP 17851498A JP 2000013142 A JP2000013142 A JP 2000013142A
Authority
JP
Japan
Prior art keywords
layer
wiring
pattern
ground pattern
oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10178514A
Other languages
Japanese (ja)
Inventor
Satokatsu Nakamura
里克 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP10178514A priority Critical patent/JP2000013142A/en
Publication of JP2000013142A publication Critical patent/JP2000013142A/en
Pending legal-status Critical Current

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  • Oscillators With Electromechanical Resonators (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To always secure a large frequency variable range without the aid of a set side substrate pattern and to stabilize ground pattern and to reduce power noise by means of providing a wide ground pattern by constituting a hollow layer which is made into a cavity by removing a substrate peripheral part in an inner layer held by a ground pattern layer and a wiring layer on a multilayer substrate. SOLUTION: In a multilayer substrate where a circuit constituting an oscillator is wired/mounted, a hollow layer 104 which is made into a cavity by removing a peripheral part is provided in an inner layer held by a back ground pattern layer 106 and a surface wiring layer 102 where element parts 103 are mounted and wired. The dielectric constant of air is small to a degree which is almost similar to vacuum. Parasitic capacity generated among the wiring pattern of an oscillation circuit part, a part electrode terminal and a ground pattern can be suppressed to be small and a wide frequency variable range can be secured in the oscillator provided with the hollow layer 104 between the wiring layer 102 and the ground pattern layer 106.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は外部から印可する制
御電圧によって周波数の制御が可能な電圧制御圧電発振
器に関するものである。
The present invention relates to a voltage controlled piezoelectric oscillator whose frequency can be controlled by a control voltage applied from the outside.

【0002】[0002]

【従来の技術】圧電発振器は圧電振動子と発振、波形整
形、分周回路等を単一のパッケージ内にまとめたもので
電子機器を構成する重要な電子部品の一つになってい
る。近年電子機器の小型化・薄型化の流れを受けて、圧
電発振器も従来のDIP型のものから表面実装型のもの
に主流が移りつつある。表面実装型圧電発振器は、多層
基板上に要素部品の配線および実装が行なわれ、モール
ド樹脂や金属キャップ等によってパッケージ化されたも
のが最も一般的であり、通常基板裏面層もしくは内面層
に、層のほぼ全体がアースパターンで覆われたアースパ
ターン層が設けられ、グランドの安定化、電源ノイズの
除去とともに、発振器が部品として実装される電子機器
セット側基板との間の電気的干渉の防止が図られてい
る。
2. Description of the Related Art A piezoelectric oscillator is one of important electronic components that constitute an electronic device by integrating a piezoelectric vibrator and an oscillation, waveform shaping, frequency dividing circuit and the like in a single package. In recent years, with the trend of downsizing and thinning of electronic devices, the mainstream of piezoelectric oscillators is shifting from the conventional DIP type to the surface mount type. The most common type of surface mount type piezoelectric oscillator is one in which component parts are wired and mounted on a multilayer substrate and packaged with a mold resin, a metal cap, or the like. Is provided with a ground pattern layer that is almost entirely covered with a ground pattern, stabilizing the ground, removing power supply noise, and preventing electrical interference with the electronic equipment set-side board on which the oscillator is mounted as a component. It is planned.

【0003】圧電発振器のうち、外部から印可する制御
電圧によって発振周波数の制御が可能なものを電圧制御
圧電発振器と呼び、主に移動体通信や画像表示分野の同
期用途として幅広く用いられている。電圧制御圧電発振
器の基本構成は図2に示される如くであり、圧電振動子
201に直列に接続された可変容量素子203に対し
て、外部から制御電圧を加えて容量値を変化させること
で、出力クロック信号の周波数を変化させる仕組みであ
る。
[0003] Among the piezoelectric oscillators, those whose oscillation frequency can be controlled by a control voltage applied from the outside are called voltage-controlled piezoelectric oscillators, and are widely used mainly for synchronization in mobile communication and image display fields. The basic configuration of the voltage controlled piezoelectric oscillator is as shown in FIG. 2. By applying a control voltage from the outside to the variable capacitance element 203 connected in series to the piezoelectric vibrator 201 to change the capacitance value, This is a mechanism for changing the frequency of the output clock signal.

【0004】[0004]

【発明が解決しようとする課題】アースパターン層を備
えた多層基板上に電圧制御発振器を構成した場合、回路
配線パターンおよび部品電極端子とアースパターンとの
間に発生する寄生容量によって、周波数の可変範囲が減
少してしまうという問題が生じる。この問題に対する対
策として、部品および配線パターン下のアースパターン
を窓状に除去することで、周波数可変範囲の確保を狙っ
た発明が特開平10−22734号に記されている。
When a voltage controlled oscillator is formed on a multilayer substrate having an earth pattern layer, the frequency can be varied by the parasitic capacitance generated between the circuit wiring pattern and the component electrode terminal and the earth pattern. There is a problem that the range is reduced. As a countermeasure against this problem, Japanese Patent Application Laid-Open No. Hei 10-22734 discloses an invention which aims to secure a variable frequency range by removing a ground pattern under a component and a wiring pattern in a window shape.

【0005】しかし実際の使用状況を考えた場合、圧電
発振器は電子機器セット基板に密着して実装された状態
で使用されることが多いため、アースパターンが窓上に
除去された上記発明の発振器の周波数可変範囲はセット
基板側の配線パターンに大きく影響されることになる。
例えばアースパターンを除去した窓状部直下にセット基
板側のアースパターンが配されていた場合、アースパタ
ーン除去の効果は打ち消され、発振回路配線とセット基
板アースパターン間に発生する浮遊容量により、周波数
可変範囲は狭められてしまう。窓状部下のセット基板パ
ターンがアースパターンでない場合には狙い通りの周波
数可変範囲が得られるが、このように周波数可変範囲が
セット基板配線パターンによって左右されるような発振
器はユーザー側から見ても非常に使いにくい製品になっ
てしまう。
However, considering the actual use situation, since the piezoelectric oscillator is often used in a state of being mounted in close contact with the electronic device set board, the oscillator of the present invention in which the ground pattern is removed from the window is provided. Is greatly affected by the wiring pattern on the set substrate side.
For example, if the ground pattern on the set board side is placed directly below the window-shaped part from which the ground pattern has been removed, the effect of the ground pattern removal is negated, and the stray capacitance generated between the oscillation circuit wiring and the set board ground pattern causes the frequency to drop. The variable range is narrowed. If the set board pattern under the window is not a ground pattern, a desired frequency variable range can be obtained.However, such an oscillator whose frequency variable range is influenced by the set board wiring pattern can be viewed from the user side. It becomes a very difficult product to use.

【0006】また回路構成全部品および配線パターン下
のアースパターンを除去する上記発明においては、アー
スパターン面積が大きく削られてしまうため、グランド
の安定化および電源ノイズの除去というアースパターン
を設ける本来の意味が損なわれてしまう問題も生じる。
In the above-mentioned invention in which all the circuit components and the earth pattern under the wiring pattern are removed, the area of the earth pattern is greatly reduced. Therefore, the original ground pattern for stabilizing the ground and removing the power supply noise is provided. There is also a problem that the meaning is lost.

【0007】[0007]

【課題を解決するための手段】上記課題を解決するため
本発明の電圧制御圧電発振器は、アースパターン層と配
線層とに挟まれた内面層に、基板周辺部を除いて空洞化
された中空層を備える多層基板上に構成されていること
を特徴とする。
In order to solve the above-mentioned problems, a voltage controlled piezoelectric oscillator according to the present invention has a hollow inside a cavity except for a peripheral portion of a substrate, on an inner surface layer sandwiched between an earth pattern layer and a wiring layer. It is characterized by being constituted on a multilayer substrate having layers.

【0008】また他の構成として本発明の電圧制御圧電
発振器は、アースパターン層と配線層とに挟まれた内面
層に、発振回路部分の配線パターンおよび部品電極端子
の直下が空洞化された中空層を備える多層基板上に構成
されていることを特徴とする。
According to another aspect of the present invention, there is provided a voltage controlled piezoelectric oscillator according to the present invention, wherein an inner surface layer sandwiched between an earth pattern layer and a wiring layer has a hollow structure in which a wiring pattern of an oscillation circuit portion and a part directly below a component electrode terminal are hollowed out. It is characterized by being constituted on a multilayer substrate having layers.

【0009】[0009]

【発明の実施の形態】(実施の形態1)圧電振動子に直
列に容量が付加され、発振回路が形成されたときの発振
周波数は次式で近似されることがよく知られている。 f=fs(1+C1/2(C0+CL)) ここでfsは圧電振動子の直列共振周波数、C0とC1
はそれぞれ振動子の並列等価容量および直列等価容量、
CLは負荷容量を示す。電圧制御圧電発振器ではこの負
荷容量CLの一部に可変容量素子を用い、外部からの制
御電圧によって容量値を変化させることで、発振周波数
を可変にしている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) It is well known that the oscillation frequency when a capacitor is added in series to a piezoelectric vibrator and an oscillation circuit is formed can be approximated by the following equation. f = fs (1 + C1 / 2 (C0 + CL)) where fs is the series resonance frequency of the piezoelectric vibrator, C0 and C1
Are the parallel equivalent capacitance and the series equivalent capacitance of the vibrator, respectively.
CL indicates the load capacity. In the voltage controlled piezoelectric oscillator, a variable capacitance element is used as a part of the load capacitance CL, and the oscillation frequency is made variable by changing the capacitance value by an external control voltage.

【0010】固有のfs、C0、C1に対して負荷容量
CLと周波数変化量Δf=f−fsの関係は一般に図3
のグラフの様な形になり、負荷容量CLの値が小さい領
域ほど周波数変化量の傾きが大きいという傾向を持つ。
このため電圧制御発振器においては、できるだけ負荷容
量CLの小さい領域において発振回路を形成し、可変容
量素子の限られた容量可変範囲の中で最大限の周波数可
変幅を確保できるように設計される。
The relationship between the load capacitance CL and the frequency variation Δf = f−fs with respect to the specific fs, C0 and C1 is generally shown in FIG.
In the graph, there is a tendency that the slope of the frequency change amount becomes larger as the value of the load capacitance CL becomes smaller.
Therefore, in the voltage controlled oscillator, an oscillation circuit is formed in a region where the load capacitance CL is as small as possible, and the voltage controlled oscillator is designed so as to secure a maximum frequency variable width within a limited variable capacitance range of the variable capacitance element.

【0011】層のほぼ全体がアースパターンで覆われた
アースパターン層を備えた多層基板上に回路を構成した
場合、回路配線パターンおよび部品電極端子とアースパ
ターン層間に対向面積に比例した寄生容量が発生する
が、該寄生容量は大きい場合でも数ピコファラット程度
であるため、通常の回路の場合問題にされることは少な
い。
When a circuit is formed on a multilayer substrate having an earth pattern layer in which almost all of the layers are covered with an earth pattern, a parasitic capacitance proportional to the facing area between the circuit wiring pattern and the component electrode terminals and the earth pattern layer is generated. Although it occurs, even if the parasitic capacitance is large, it is only a few picofarats, so that it is rarely a problem in the case of a normal circuit.

【0012】しかし上述したように負荷容量が非常に小
さい領域で発振回路が形成され、負荷容量の変化によっ
て周波数可変範囲が決まる電圧制御圧電発振器において
は、発振回路配線パターンおよび部品電極端子とアース
パターン層間に生じる寄生容量が周波数可変範囲に大き
な影響を及ぼす。具体的に言えば寄生容量が付加される
ことにより合成負荷容量が嵩上げされ、周波数可変範囲
が低減されてしまう。図3のグラフで説明すると、寄生
容量Cpにより容量可変範囲がΔCL1からΔCL2に
シフトされた場合、容量可変幅は同じであるにもかかわ
らず、周波数可変範囲がΔf1からΔf2に大きく低減
されてしまう。
However, as described above, in the voltage controlled piezoelectric oscillator in which the oscillation circuit is formed in a region where the load capacitance is extremely small and the frequency variable range is determined by the change in the load capacitance, the oscillation circuit wiring pattern, the component electrode terminals, and the ground pattern Parasitic capacitance generated between layers greatly affects the frequency variable range. Specifically, the addition of the parasitic capacitance raises the combined load capacitance and reduces the frequency variable range. Referring to the graph of FIG. 3, when the variable capacitance range is shifted from ΔCL1 to ΔCL2 by the parasitic capacitance Cp, the frequency variable range is greatly reduced from Δf1 to Δf2, even though the variable capacitance width is the same. .

【0013】上記課題を解決するための本発明の基本構
成を図1に示す。発振器を構成する回路が配線・実装さ
れた多層基板において、裏面アースパターン層と、部品
の実装および配線が行われている表面配線層とに挟まれ
た内面層に、周辺部を除いて空洞化された中空層を備え
ることを特徴としている。
FIG. 1 shows a basic configuration of the present invention for solving the above problems. In a multi-layer board on which the circuits that make up the oscillator are wired and mounted, the inner surface layer sandwiched between the backside ground pattern layer and the front wiring layer where components are mounted and wired is hollowed out, excluding the periphery It is characterized by having a hollow layer formed.

【0014】2つの電極間に発生する容量は両電極間に
充填されている物質の誘電率に比例する。プリント基板
材料として使用されることが多いガラスエポキシ樹脂の
場合、真空に対する比誘電率は4から5程度と大きな値
を持ち、また高精度発振器用として用いられることが多
い無機セラミック基板の場合には、比誘電率はさらに大
きく10程度である。このため発振回路部分の配線パタ
ーンおよび部品電極端子とアースパターン間に発生する
寄生容量も大きなものになってしまう。
The capacitance generated between the two electrodes is proportional to the dielectric constant of the material filled between the two electrodes. In the case of glass epoxy resin, which is often used as a printed circuit board material, the relative dielectric constant with respect to vacuum has a large value of about 4 to 5, and in the case of an inorganic ceramic substrate, which is often used for high-precision oscillators, , The relative permittivity is even larger, about 10. For this reason, the parasitic capacitance generated between the wiring pattern of the oscillation circuit portion and the component electrode terminal and the ground pattern also becomes large.

【0015】これに対して空気の誘電率は真空とほぼ同
程度の小さなものであり、配線層とアースパターン層間
に中空層を備える本発明の発振器では、発振回路部分の
配線パターンおよび部品電極端子とアースパターン間に
発生する寄生容量を非常に小さなものに抑えることが可
能で、広い周波数可変範囲を確保することができる。
On the other hand, the permittivity of air is as small as about the same as vacuum, and in the oscillator of the present invention having a hollow layer between the wiring layer and the ground pattern layer, the wiring pattern of the oscillation circuit portion and the component electrode terminals The parasitic capacitance generated between the ground pattern and the ground pattern can be suppressed to a very small value, and a wide frequency variable range can be secured.

【0016】図1では表面に配線層102、裏面にアー
スパターン層106を持った2層基板に本発明を適用し
た場合について説明しているが、より多くの層を持った
多層基板に適用した場合にも同様の効果が得られる。こ
の場合図4に示すように配線は表面層402および表面
層に近接した数層で行い、中空層404を挟んでアース
パターン層406を設け、裏面層407に電極を配する
構成となる。なお多層基板ではアースパターン層に加
え、層のほぼ全体が電源パターンで覆われた電源パター
ン層が設けられるケースも多いが、この場合の電源パタ
ーン層はアースパターン層と交流的には等価であり、寄
生容量低減のためにはアースパターン層と同様な扱いが
必要である。
FIG. 1 shows a case where the present invention is applied to a two-layer substrate having a wiring layer 102 on the front surface and an earth pattern layer 106 on the rear surface. However, the present invention is applied to a multi-layer substrate having more layers. In this case, the same effect can be obtained. In this case, as shown in FIG. 4, wiring is performed in the surface layer 402 and several layers close to the surface layer, an earth pattern layer 406 is provided with the hollow layer 404 interposed therebetween, and electrodes are arranged on the back layer 407. In many cases, in addition to the ground pattern layer, a power supply pattern layer in which almost the entire layer is covered with a power supply pattern is provided on the multilayer substrate, but the power supply pattern layer in this case is equivalent to the ground pattern layer in terms of AC. In order to reduce the parasitic capacitance, the same treatment as the ground pattern layer is required.

【0017】上記した中空構造基板の製法としては、中
空箇所に相当する内面が削除された2枚の基板を張り合
わせて作成する方法や、あらかじめ中空箇所が除去され
た基板材料を積層させていく方法等によって製造が可能
である。
As a method of manufacturing the above-mentioned hollow structure substrate, a method of laminating two substrates each having an inner surface corresponding to a hollow portion removed, or a method of laminating substrate materials from which a hollow portion has been removed in advance. It can be manufactured by the above method.

【0018】(実施の形態2)図1および図4に説明し
た発振器では、基板周辺部を除いて層全体が空洞化され
た中空層が基板内部に設けられているため、配線層から
ベタアース層および外部電極への配線は空洞化されてい
ない基板周辺の狭い部分を用いて行わなくてはならず、
外部電極数が多い場合には配線を通すことが難しくなっ
てくる。
(Embodiment 2) In the oscillator described in FIGS. 1 and 4, a hollow layer in which the entire layer is hollowed out except for the peripheral portion of the substrate is provided inside the substrate. And wiring to the external electrode must be performed using a narrow part around the substrate that is not hollowed out,
When the number of external electrodes is large, it becomes difficult to pass wiring.

【0019】回路配線パターンおよび部品電極端子とア
ースパターン層間に生じる寄生容量によって周波数可変
範囲が小さくなってしまうことを上述したが、この対象
になる配線パターンおよび部品電極端子は発振回路部分
に限定され、その他回路の配線パターンおよび部品電極
端子や部品パッケージ等に対して寄生容量が付いても周
波数可変範囲にはほとんど影響を及ぼさない。
Although it has been described above that the frequency variable range is reduced by the parasitic capacitance generated between the circuit wiring pattern and component electrode terminals and the ground pattern layer, the target wiring pattern and component electrode terminals are limited to the oscillation circuit portion. Even if a parasitic capacitance is added to other circuit wiring patterns, component electrode terminals, component packages, and the like, it hardly affects the frequency variable range.

【0020】例えば電圧制御圧電発振器として一般に多
く用いられる図5に示す回路が単体部品によって構成さ
れている場合を考えると、周波数可変幅に影響を及ぼす
のは発振回路ループ内に生じるCp1、Cp2、Cp3
の各寄生容量であり、制御電圧入力端子503に付くC
p4、波形整形用増幅器505に付くCp5、Cp6等
の寄生容量はほとんど影響がない。また図5には記述さ
れていないが、波形整形用増幅器505の後段に分周回
路や出力制御回路等が設けられている場合にも、これら
回路の配線パターンおよび部品電極端子とアースパター
ン間に生じる寄生容量は周波数可変幅にほとんど影響を
及ぼさない。
For example, considering the case where the circuit shown in FIG. 5 which is generally used as a voltage controlled piezoelectric oscillator is constituted by a single component, the influence on the frequency variable width is caused by Cp1, Cp2, Cp2, and Cp2 generated in the oscillation circuit loop. Cp3
Of the control voltage input terminal 503.
Parasitic capacitances such as p4 and Cp5 and Cp6 attached to the waveform shaping amplifier 505 have almost no effect. Although not shown in FIG. 5, even when a frequency dividing circuit, an output control circuit, and the like are provided at the subsequent stage of the waveform shaping amplifier 505, the wiring pattern of these circuits and the component electrode terminals and the ground pattern may be provided. The generated parasitic capacitance hardly affects the frequency variable width.

【0021】したがって発振回路を構成する配線パター
ンおよび部品電極端子の直下のみが空洞化された中空層
を、配線層とアースパターン層間に備える多層基板上に
発振器を構成した場合も、層全体が空洞化された中空層
を設けた場合と同様の周波数可変範囲確保の効果があ
る。ただ発振回路部の配線および部品電極端子のパター
ン形状そのままに空洞化部分を設けることは製造上大変
であるため、図6に示すように上記部分を最低限含んだ
周辺部を単純な形状で空洞化することが現実的である。
中空層604において空洞化されていない部分は上下層
間の配線に用いる他、該層内での配線に利用することも
可能である。
Therefore, even when an oscillator is formed on a multilayer substrate having a hollow layer in which only the wiring pattern and component electrode terminals constituting the oscillation circuit are hollowed immediately below the wiring layer and the ground pattern layer, the entire layer is also hollow. This has the same effect of ensuring a variable frequency range as in the case where the hollow layer is provided. However, since it is difficult in manufacturing to provide a hollowed portion with the pattern shape of the wiring of the oscillation circuit portion and the electrode terminal of the component as it is, as shown in FIG. Is realistic.
The portion of the hollow layer 604 that is not hollowed out can be used not only for wiring between the upper and lower layers, but also for wiring in the layer.

【0022】図5では単体部品で回路が構成されている
場合を考えたが、発振器用ICが用いられた場合も同様
に考えることができる。図7において2点鎖線で囲まれ
た部分が発振器用ICで構成されている場合、Cp1、
Cp2、Cp3の寄生容量は周波数可変範囲に影響を及
ぼすため、IC701と可変容量素子間の配線および各
電極直下、IC701と圧電素子702両端間の配線お
よび各電極直下は少なくとも空洞化されている必要があ
る。電圧制御発振回路としてはこの他にも両負荷容量に
可変容量素子を設ける構成や、圧電振動子に隣接して可
変容量素子を設ける構成等様々なバリエーションがある
が、本発明はいずれの構成にも適用が可能である。
In FIG. 5, the case where the circuit is constituted by a single component is considered, but the case where an oscillator IC is used can be similarly considered. In the case where the portion surrounded by the two-dot chain line in FIG.
Since the parasitic capacitance of Cp2 and Cp3 affects the frequency variable range, at least the wiring between the IC 701 and the variable capacitance element and immediately below each electrode, and the wiring between the IC 701 and both ends of the piezoelectric element 702 and immediately below each electrode must be at least hollow. There is. There are various other variations of the voltage-controlled oscillation circuit, such as a configuration in which a variable capacitance element is provided for both load capacitors, and a configuration in which a variable capacitance element is provided adjacent to the piezoelectric vibrator. Is also applicable.

【0023】[0023]

【発明の効果】以上述べたように本発明の電圧制御圧電
発振器は、セット側基板パターンによらず常に大きな周
波数可変範囲を確保でき、また広いアースパターンを備
えることで、グランドの安定化や電源ノイズの低減にも
優れている。
As described above, the voltage-controlled piezoelectric oscillator of the present invention can always secure a large frequency variable range regardless of the set-side substrate pattern, and has a wide ground pattern to stabilize the ground and provide a power supply. Excellent noise reduction.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の圧電発振器の基本構成である。FIG. 1 shows a basic configuration of a piezoelectric oscillator according to the present invention.

【図2】電圧制御発振回路の基本構成図である。FIG. 2 is a basic configuration diagram of a voltage controlled oscillation circuit.

【図3】負荷容量対周波数変化量のグラフである。FIG. 3 is a graph of load capacity versus frequency change.

【図4】多層基板を用いた場合の本発明の構成図であ
る。
FIG. 4 is a configuration diagram of the present invention when a multilayer substrate is used.

【図5】電圧制御発振回路に発生する寄生容量を示した
図である。
FIG. 5 is a diagram showing a parasitic capacitance generated in the voltage controlled oscillation circuit.

【図6】請求項2の圧電発振器の基本構成である。FIG. 6 shows a basic configuration of a piezoelectric oscillator according to a second embodiment.

【図7】発振器用ICを使用した場合の寄生容量を示し
た図である。
FIG. 7 is a diagram illustrating parasitic capacitance when an oscillator IC is used.

【符号の説明】[Explanation of symbols]

101 パッケージ 102、403、602 基板配線層 103 要素部品 104、404、604 基板中空層 106、406、606 アースパターン層 107 外部電極 108 アースパターン 201、502 圧電振動子 202 発振回路 203、504 可変容量素子 501 発振用増幅器 101 Package 102, 403, 602 Substrate wiring layer 103 Elemental component 104, 404, 604 Substrate hollow layer 106, 406, 606 Earth pattern layer 107 External electrode 108 Earth pattern 201, 502 Piezoelectric vibrator 202 Oscillator circuit 203, 504 Variable capacitance element 501 Oscillation amplifier

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 圧電振動子、増幅器、可変容量素子を含
む負荷容量等からなる構成回路が多層基板上に配線・実
装された電圧制御圧電発振器であり、上記多層基板は、
裏面層もしくは裏面に隣接する内面層に層のほぼ全面が
アースパターンで覆われたアースパターン層を備え、該
アースパターン層と、部品の実装および配線が行われて
いる配線層とに挟まれた内面層に、周辺部を除く層全体
が空洞化された中空層を備えることを特徴とする電圧制
御圧電発振器。
1. A voltage controlled piezoelectric oscillator in which a constituent circuit including a piezoelectric vibrator, an amplifier, and a load capacitance including a variable capacitance element is wired and mounted on a multilayer substrate.
The back surface layer or the inner surface layer adjacent to the back surface has an earth pattern layer in which almost the entire surface is covered with an earth pattern, and is sandwiched between the earth pattern layer and a wiring layer in which components are mounted and wiring is performed. A voltage controlled piezoelectric oscillator comprising a hollow layer in which an entire layer except a peripheral portion is hollowed out on an inner surface layer.
【請求項2】 圧電振動子、増幅器、可変容量素子を含
む負荷容量等からなる構成回路が多層基板上に配線・実
装された電圧制御圧電発振器であり、上記多層基板は、
裏面層もしくは裏面に隣接する内面層に層のほぼ全面が
アースパターンで覆われたアースパターン層を備え、該
アースパターン層と、部品の実装および配線が行われて
いる配線層とに挟まれた内面層に、発振回路部分の配線
パターンおよび部品電極端子の直下が空洞化された中空
層を備えることを特徴とする電圧制御圧電発振器。
2. A voltage controlled piezoelectric oscillator in which a constituent circuit including a piezoelectric vibrator, an amplifier, and a load capacitance including a variable capacitance element is wired and mounted on a multilayer substrate.
The back surface layer or the inner surface layer adjacent to the back surface has an earth pattern layer in which almost the entire surface is covered with an earth pattern, and is sandwiched between the earth pattern layer and a wiring layer in which components are mounted and wiring is performed. A voltage-controlled piezoelectric oscillator comprising, on an inner surface layer, a hollow layer in which a wiring pattern of an oscillation circuit portion and a component electrode terminal are directly hollowed.
JP10178514A 1998-06-25 1998-06-25 Voltage control piezoelectric oscillator Pending JP2000013142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10178514A JP2000013142A (en) 1998-06-25 1998-06-25 Voltage control piezoelectric oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10178514A JP2000013142A (en) 1998-06-25 1998-06-25 Voltage control piezoelectric oscillator

Publications (1)

Publication Number Publication Date
JP2000013142A true JP2000013142A (en) 2000-01-14

Family

ID=16049813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10178514A Pending JP2000013142A (en) 1998-06-25 1998-06-25 Voltage control piezoelectric oscillator

Country Status (1)

Country Link
JP (1) JP2000013142A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030055681A (en) * 2001-12-27 2003-07-04 삼성전기주식회사 Teperature compensated crystal oscillator and method for manufacturing the same
JP4795602B2 (en) * 2000-01-31 2011-10-19 京セラキンセキ株式会社 Oscillator
JP2013243481A (en) * 2012-05-18 2013-12-05 Seiko Epson Corp Temperature compensation information generation method, manufacturing method of electronic component, oscillation element, oscillator and electronic apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4795602B2 (en) * 2000-01-31 2011-10-19 京セラキンセキ株式会社 Oscillator
KR20030055681A (en) * 2001-12-27 2003-07-04 삼성전기주식회사 Teperature compensated crystal oscillator and method for manufacturing the same
JP2013243481A (en) * 2012-05-18 2013-12-05 Seiko Epson Corp Temperature compensation information generation method, manufacturing method of electronic component, oscillation element, oscillator and electronic apparatus

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