JP2000012524A - Dry etching - Google Patents

Dry etching

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Publication number
JP2000012524A
JP2000012524A JP10176924A JP17692498A JP2000012524A JP 2000012524 A JP2000012524 A JP 2000012524A JP 10176924 A JP10176924 A JP 10176924A JP 17692498 A JP17692498 A JP 17692498A JP 2000012524 A JP2000012524 A JP 2000012524A
Authority
JP
Japan
Prior art keywords
voltage
dry etching
etching method
bias
amplitude
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10176924A
Other languages
Japanese (ja)
Inventor
Naoyuki Koto
直行 小藤
Masashi Mori
政士 森
Shinichi Taji
新一 田地
Kazunori Tsujimoto
和典 辻本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10176924A priority Critical patent/JP2000012524A/en
Publication of JP2000012524A publication Critical patent/JP2000012524A/en
Pending legal-status Critical Current

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  • Plasma Technology (AREA)
  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a dry etching method which can realize a high selectivity and a residue minimization simultaneously. SOLUTION: In the dry etching method, a high frequency voltage is modulated in an amplitude modulation(AM) manner and then applied as a bias voltage in a plasma etching apparatus. It is desirable in the AM modulation that the amplitude have a minimum of 50 V or more and a maximum of 100 V or more, the high frequency voltage to be modulated be a sinusoidal or pulsed voltage of 2 MHz or more, and one cycle period of the modulation be 10 ms or less.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はプラズマ処理方法に
係り、特に被処理物にバイアス電圧を印加する方法に関
する。
The present invention relates to a plasma processing method, and more particularly to a method for applying a bias voltage to an object to be processed.

【0002】[0002]

【従来の技術】従来のプラズマ処理装置のバイアス印加
手段のうち、最も代表的なRFバイアスと呼ばれるもの
の構成を図2に示す。被処理物1は静電吸着用セラミッ
ク2,高周波整合回路3を介して高周波電源4に接続さ
れている。高周波電源4からは正弦波状の高周波電圧が
印加される。このときプラズマ5から供給される電子が
イオンに比べて数百倍大きいため静電チャック用セラミ
ック2の試料側には負の電荷が蓄積される。
2. Description of the Related Art FIG. 2 shows the configuration of the most typical RF bias means among the bias applying means of a conventional plasma processing apparatus. The workpiece 1 is connected to a high frequency power supply 4 via a ceramic 2 for electrostatic adsorption and a high frequency matching circuit 3. A sine-wave high frequency voltage is applied from the high frequency power supply 4. At this time, since electrons supplied from the plasma 5 are several hundred times larger than ions, negative charges are accumulated on the sample side of the ceramic 2 for electrostatic chuck.

【0003】この負の電荷のため、図3のように負にシ
フトした電圧が被処理物上に現れる。この負電圧によっ
てエッチング種である正イオンが加速され被処理物に垂
直入射することによって、垂直形状の加工が可能にな
る。高周波電圧としては、周波数400KHz,800
KHz,2MHz,13.56MHz が主に用いられて
いる。この他、実験レベルでは、「1995年ドライプ
ロセス シンポジウムプロシーディングp33−37」
のようにRFバイアスをon/off 変調する方式もある。
Due to this negative charge, a negatively shifted voltage appears on the workpiece as shown in FIG. The negative voltage accelerates positive ions as etching species and vertically enters the object to be processed, thereby enabling vertical processing. As the high frequency voltage, a frequency of 400 KHz, 800
KHz, 2 MHz and 13.56 MHz are mainly used. In addition, at the experimental level, "1995 Dry Process Symposium Proceedings p33-37"
There is also a method in which the RF bias is modulated on / off as shown in FIG.

【0004】この他アイデアとしては、特許1095402 号
や特開平6−61182号などにおいてパルス波形の電圧をバ
イアスとして印加する方法が考案されている。しかし、
高周波バイアスをAM変調する方式については、これま
でなかった。
As another idea, a method of applying a voltage having a pulse waveform as a bias has been devised in Japanese Patent No. 1095402 and Japanese Patent Application Laid-Open No. 6-61182. But,
There has not been a method of AM modulating a high frequency bias.

【0005】[0005]

【発明が解決しようとする課題】図4に示す試料構造の
ように下地材料上6に形成した被エッチング材料上7に
マスク8を形成した試料をエッチングする場合、従来の
方法では、下地材料やマスク材料に対する被エッチング
材料の選択性と被エッチング材料のエッチング残り(残
さ)の低減を両立することが難しかった。2MHz以上
の高周波バイアス電圧を印加した場合やパルス状のバイ
アス電圧を印加した場合は、高選択性を得ることはでき
るが、残さが発生しやすいという問題がある。一方、2
MHz未満の低周波バイアスを印加した場合やバイアス
をon/off 変調した場合は、残さは発生し難いが、マス
ク材料に対する選択性が低い問題がある。
When a sample having a mask 8 formed on a material to be etched 7 formed on a base material 6 like a sample structure shown in FIG. It has been difficult to achieve both selectivity of the material to be etched with respect to the mask material and reduction of the etching residue (residue) of the material to be etched. When a high-frequency bias voltage of 2 MHz or more is applied or when a pulse-like bias voltage is applied, high selectivity can be obtained, but there is a problem that residues tend to occur. Meanwhile, 2
When a low-frequency bias of less than MHz is applied or when the bias is modulated on / off, a residue hardly occurs, but there is a problem that selectivity to a mask material is low.

【0006】本発明は、このトレードオフを解消し、高
選択かつ低残さのエッチング方法を提供するものであ
る。
The present invention solves this trade-off and provides a highly selective and low residue etching method.

【0007】[0007]

【課題を解決するための手段】本発明の方法では、プラ
ズマエッチング装置において、高周波電圧を図1のよう
にAM変調したものをバイアス電圧として印加する。A
M変調は、振幅の最小値が50V以上、最大値が100
V以上とする。また、変調される高周波電圧としては、
2MHz以上の正弦波状の電圧もしくはパルス状の電圧
を用いることが望ましい。また、変調の1サイクルの周
期としては10ms以下が望ましい。
According to the method of the present invention, in a plasma etching apparatus, a high-frequency voltage which is AM-modulated as shown in FIG. 1 is applied as a bias voltage. A
The M modulation has a minimum amplitude of 50 V or more and a maximum amplitude of 100 V.
V or more. Also, as the modulated high-frequency voltage,
It is desirable to use a sine wave voltage or a pulse voltage of 2 MHz or more. Further, it is desirable that the cycle of one cycle of modulation is 10 ms or less.

【0008】[0008]

【発明の実施の形態】(実施例1)図5はメタル用S−
ECRエッチング装置に本発明のバイアスを適用した装
置の例である。この装置では、UHF電源9で発生した
450MHzのUHF波を同軸線路10,整合器11,
アンテナ12を通して、処理室13に導入し、導入され
たUHF波とコイル14で作られる電子サイクロトロン
共鳴によって高密度のプラズマを生成できる構造になっ
ている。またバイアス電圧は、発振器15から発生する
正弦波状信号を信号発生器16より生成した信号を用い
てAM変調し増幅器により増幅することによって生成し
た。このバイアス電圧が高周波整合器3,静電吸着用セ
ラミック2を介して被エッチング試料1に印加される構
造になっている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG.
It is an example of an apparatus in which the bias of the present invention is applied to an ECR etching apparatus. In this device, a 450 MHz UHF wave generated by a UHF power supply 9 is transmitted through a coaxial line 10, a matching device 11,
The antenna is introduced into the processing chamber 13 through the antenna 12, and has a structure capable of generating high-density plasma by the introduced UHF wave and electron cyclotron resonance generated by the coil 14. The bias voltage was generated by AM-modulating a sinusoidal signal generated by the oscillator 15 using a signal generated by the signal generator 16 and amplifying the signal by an amplifier. The bias voltage is applied to the sample 1 to be etched via the high-frequency matching device 3 and the ceramic 2 for electrostatic attraction.

【0009】被エッチング試料としては、Siウエーハ
上のゲート配線上に堆積させた下地材料のCVD酸化膜
上に、被エッチング材料のチタン,窒化チタン(Ti
N),チタン,アルミニウム・銅・シリコン混晶(Al
−Cu−Si),窒化チタン(TiN)の順で堆積さ
せ、その上にレジストマスクを形成させたものを用い
た。
As a sample to be etched, titanium or titanium nitride (Ti) as a material to be etched is formed on a CVD oxide film as a base material deposited on a gate wiring on a Si wafer.
N), titanium, aluminum / copper / silicon mixed crystal (Al
-Cu-Si), titanium nitride (TiN), and a resist mask formed thereon.

【0010】Cl2 ガスプラズマを用いて0.4Pa ,
UHF電力800Wの条件で本発明の変調バイアスを印
加してエッチングを行った。ここでバイアスとしては、
図1のような、変調される高周波の周波数が13.56
MHz 、振幅が100Vおよび200V、変調の1サ
イクルの周期1ms、200V時のデューティ(Duty)
比が10%の高周波電圧を用いた。エッチング後の試料
の表面の電子顕微鏡写真を模写したものを図6に示す。
Using Cl 2 gas plasma, 0.4 Pa,
Etching was performed under the condition of a UHF power of 800 W while applying the modulation bias of the present invention. Here, the bias is
As shown in FIG. 1, the frequency of the modulated high frequency is 13.56.
MHz, amplitude is 100 V and 200 V, one cycle of modulation is 1 ms, duty at 200 V (Duty)
A high frequency voltage having a ratio of 10% was used. FIG. 6 shows an electron micrograph of the surface of the sample after etching.

【0011】比較のため従来の高周波バイアス(振幅1
00V,周波数13.56MHz)を印加した場合のエ
ッチング後の試料表面の電子顕微鏡写真の模写を図7に
示す。従来法のバイアスではエッチング後の試料の表面
に島状の残さが見られるのに対して、本発明のバイアス
では、残さの大きさ,数とも低減されている。この効果
は、銅を含む材料をエッチングする際に顕著である。
For comparison, a conventional high frequency bias (amplitude 1)
FIG. 7 shows a simulated electron micrograph of the sample surface after etching in the case of applying a voltage of 00 V and a frequency of 13.56 MHz. With the bias of the conventional method, an island-like residue is observed on the surface of the sample after etching, whereas with the bias of the present invention, both the size and the number of the residue are reduced. This effect is remarkable when etching a material containing copper.

【0012】本発明のバイアスの場合のマスク材料のホ
トレジストのエッチング速度と被エッチング材料のAl
−Cu−Siのエッチング速度の関係を図8に示す。本
発明のバイアスでは、従来の13.56MHz のバイア
スと同等かそれ以上の高選択性が維持されることがわか
った。また、本バイアスでは、下地のCVD酸化膜に対
しても同様に高選択性が維持されることがわかった。
In the case of the bias of the present invention, the etching rate of the photoresist of the mask material and the Al of the material to be etched.
FIG. 8 shows the relationship between the etching rates of —Cu—Si. It has been found that the bias of the present invention maintains high selectivity equal to or higher than the conventional 13.56 MHz bias. In addition, it was found that this bias maintains high selectivity similarly for the underlying CVD oxide film.

【0013】図9は変調の1サイクルの周期と被エッチ
ング材料のAl−Cu−Siのエッチング速度の関係を
示す。1サイクルの周期が10ms以下の領域で高いA
l−Cu−Siのエッチング速度が得られることがわか
る。本実施例では、バイアス電圧の振幅として100V
および200Vを用いたが、小振幅時の電圧を50V以
上に、高振幅時の電圧を100V以上にすれば同様の効
果が得られる。また、本実施例では変調される高周波電
圧として周波数13.56MHz の正弦波状の電圧を用
いたが、2MHz以上の正弦波状の電圧もしくはパルス
状の電圧を用いれば同様の効果が得られる。
FIG. 9 shows the relationship between the cycle of one cycle of modulation and the etching rate of Al-Cu-Si as a material to be etched. High A in a region where the cycle of one cycle is 10 ms or less
It can be seen that an etching rate of 1-Cu-Si can be obtained. In the present embodiment, the amplitude of the bias voltage is 100 V
And 200 V, the same effect can be obtained by setting the voltage at the small amplitude to 50 V or more and the voltage at the high amplitude to 100 V or more. In this embodiment, a sinusoidal voltage having a frequency of 13.56 MHz is used as the modulated high-frequency voltage. However, a similar effect can be obtained by using a sinusoidal voltage or a pulsed voltage of 2 MHz or more.

【0014】本実施例は、被エッチング材料Al−Cu
−Si、マスク材料がホトレジスト、下地材料がCVD
酸化膜の場合について述べたが、他の被エッチング材料
や他のマスク材料、他の下地材料についても同様の効果
がある。
In this embodiment, the material to be etched is Al-Cu
-Si, mask material is photoresist, base material is CVD
Although the case of the oxide film has been described, similar effects can be obtained with other materials to be etched, other mask materials, and other base materials.

【0015】[0015]

【発明の効果】本発明によれば、エッチングの高選択性
と低残さ性が同時に達成される。特に、変調される高周
波電圧の周波数を2MHz以上にすることで、選択比4
以上の高選択性が維持される。また、変調の1サイクル
の周期を10ms以下にすることで高速加工性が達成さ
れる。
According to the present invention, high selectivity and low residual etching can be achieved at the same time. In particular, by setting the frequency of the modulated high-frequency voltage to 2 MHz or more, the selection ratio 4
The above high selectivity is maintained. In addition, high-speed workability is achieved by setting the cycle of one modulation cycle to 10 ms or less.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例において試料に印加するバイ
アス電圧の波形図。
FIG. 1 is a waveform diagram of a bias voltage applied to a sample in one embodiment of the present invention.

【図2】従来例のRFバイアスを用いたプラズマエッチ
ング装置の縦断面図。
FIG. 2 is a longitudinal sectional view of a conventional plasma etching apparatus using an RF bias.

【図3】従来例のRFバイアスのウエーハバイアス波形
図。
FIG. 3 is a wafer bias waveform diagram of a conventional RF bias.

【図4】被加工物となる試料構造を示す断面図。FIG. 4 is a cross-sectional view showing a sample structure to be processed.

【図5】本発明の方法を実施するためのS−ECR装置
の一例を示す縦断面図。
FIG. 5 is a longitudinal sectional view showing an example of an S-ECR apparatus for performing the method of the present invention.

【図6】本発明を実施してエッチングした試料表面の電
子顕微鏡写真の模写図。
FIG. 6 is a simulated view of an electron micrograph of a sample surface etched according to the present invention.

【図7】従来の高周波バイアスを印加してエッチングし
た試料表面の電子顕微鏡写真の模写図。
FIG. 7 is a simulated view of an electron micrograph of a sample surface etched by applying a conventional high-frequency bias.

【図8】Al−Cu−Siのエッチング速度とレジスト
エッチング速度の関係の測定図。
FIG. 8 is a measurement diagram of a relationship between an etching rate of Al—Cu—Si and a resist etching rate.

【図9】変調の1サイクルの周期とAl−Cu−Siエ
ッチング速度の関係の測定図。
FIG. 9 is a measurement diagram showing the relationship between the cycle of one cycle of modulation and the etching rate of Al—Cu—Si.

【符号の説明】[Explanation of symbols]

1…被処理物、2…静電チャック、3…高周波整合回
路、4…高周波電源、5…プラズマ、6…下地材料、7
…被エッチング材料、8…マスク、9…UHF電源、1
0…同軸線路、11…UHF用整合器、12…アンテ
ナ、13…処理室、14…コイル、15…発振器、16
…信号発生器。
DESCRIPTION OF SYMBOLS 1 ... Workpiece, 2 ... Electrostatic chuck, 3 ... High frequency matching circuit, 4 ... High frequency power supply, 5 ... Plasma, 6 ... Base material, 7
... material to be etched, 8 ... mask, 9 ... UHF power supply, 1
0: Coaxial line, 11: Matching device for UHF, 12: Antenna, 13: Processing room, 14: Coil, 15: Oscillator, 16
... signal generator.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 田地 新一 東京都国分寺市東恋ケ窪一丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 辻本 和典 東京都国分寺市東恋ケ窪一丁目280番地 株式会社日立製作所中央研究所内 Fターム(参考) 4K057 DA13 DA20 DB04 DB05 DB11 DB15 DD01 DM18 DM19 DM20 DN01 5F004 AA02 BA16 BB11 CA03 CA06 DA04 DB09 DB12  ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Shinichi Taji 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. 4K057 DA13 DA20 DB04 DB05 DB11 DB15 DD01 DM18 DM19 DM20 DN01 5F004 AA02 BA16 BB11 CA03 CA06 DA04 DB09 DB12

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】減圧処理室内に載置した被処理物にプラズ
マを供給し、前記被処理物にバイアス電圧を印加するプ
ラズマエッチング方法において、上記バイアス電圧とし
て高周波電圧を振幅変調した電圧を用いることを特徴と
するドライエッチング方法。
In a plasma etching method for supplying plasma to an object placed in a reduced-pressure processing chamber and applying a bias voltage to the object, a voltage obtained by amplitude-modulating a high-frequency voltage is used as the bias voltage. A dry etching method characterized by the above-mentioned.
【請求項2】請求項1に記載の振幅変調された電圧の振
幅の最小値が50V以上、振幅の最大値が100V以上
であることを特徴とするドライエッチング方法。
2. A dry etching method according to claim 1, wherein the amplitude-modulated voltage has a minimum amplitude of 50 V or more and a maximum amplitude of 100 V or more.
【請求項3】請求項1に記載の変調される高周波バイア
ス電圧が周波数2MHz以上の正弦波状のバイアス電圧
か、もしくは、パルス状の電圧を用いることを特徴とす
るドライエッチング方法。
3. The dry etching method according to claim 1, wherein the high frequency bias voltage to be modulated is a sinusoidal bias voltage having a frequency of 2 MHz or more or a pulsed voltage.
【請求項4】請求項1に記載の振幅変調の1サイクルの
周期が10ms以下であることを特徴とするドライエッ
チング方法。
4. A dry etching method according to claim 1, wherein a cycle of one cycle of the amplitude modulation is 10 ms or less.
【請求項5】請求項1に記載の被処理物が下地材料,1
種類以上の材質からなる被エッチング材料,マスク材料
の積層構造であり、かつ前記被エッチング材料にアルミ
ニウムもしくは銅が含まれることを特徴とするドライエ
ッチング方法。
5. An object according to claim 1, wherein the object to be treated is a base material,
A dry etching method having a laminated structure of a material to be etched and a mask material made of more than two kinds of materials, wherein the material to be etched contains aluminum or copper.
【請求項6】請求項5に記載のマスク材料がホトレジス
トであることを特徴とするドライエッチング方法。
6. A dry etching method, wherein the mask material according to claim 5 is a photoresist.
JP10176924A 1998-06-24 1998-06-24 Dry etching Pending JP2000012524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10176924A JP2000012524A (en) 1998-06-24 1998-06-24 Dry etching

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10176924A JP2000012524A (en) 1998-06-24 1998-06-24 Dry etching

Publications (1)

Publication Number Publication Date
JP2000012524A true JP2000012524A (en) 2000-01-14

Family

ID=16022146

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2000012524A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1336984A2 (en) * 2002-02-13 2003-08-20 Applied Materials, Inc. Method and apparatus for providing modulated bias power to a plasma etch reactor
US7112533B2 (en) 2000-08-31 2006-09-26 Micron Technology, Inc. Plasma etching system and method
WO2008044633A1 (en) * 2006-10-06 2008-04-17 Tokyo Electron Limited Plasma etching device and plasma etching method
KR100827805B1 (en) * 2007-10-31 2008-05-07 주식회사 상진미크론 Position controller for fine blanking press

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7112533B2 (en) 2000-08-31 2006-09-26 Micron Technology, Inc. Plasma etching system and method
US7507672B1 (en) 2000-08-31 2009-03-24 Micron Technology, Inc. Plasma etching system and method
EP1336984A2 (en) * 2002-02-13 2003-08-20 Applied Materials, Inc. Method and apparatus for providing modulated bias power to a plasma etch reactor
EP1336984A3 (en) * 2002-02-13 2004-09-15 Applied Materials, Inc. Method and apparatus for providing modulated bias power to a plasma etch reactor
WO2008044633A1 (en) * 2006-10-06 2008-04-17 Tokyo Electron Limited Plasma etching device and plasma etching method
US8852385B2 (en) 2006-10-06 2014-10-07 Tokyo Electron Limited Plasma etching apparatus and method
US10229815B2 (en) 2006-10-06 2019-03-12 Tokyo Electron Limited Plasma etching apparatus and method
US10861678B2 (en) 2006-10-06 2020-12-08 Tokyo Electron Limited Plasma etching apparatus and method
KR100827805B1 (en) * 2007-10-31 2008-05-07 주식회사 상진미크론 Position controller for fine blanking press

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