JP2000011699A - Semiconductor memory apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To greatly shorten a test time of a reliability test by setting an X decoder and a Y decoder having a function of carrying out a predetermined multiple selection, and a control circuit for independently generating a word line multiple selection signal or a bit line multiple selection signal according to an external control signal. SOLUTION: A multiple selection function and an impression voltage switch function of an X decoder 2 or a Y decoder 3 are driven by a decode circuit control signal 4a, 4b, 4c, 4d generated at each independently set mode of a control circuit 4 upon receipt of various control signals CONT from the outside. In consequence of this, a voltage can be impressed only to gates of a plurality of memory cells or only to drains of the plurality of memory cells, and the impression voltage can be switched. A voltage acceleration coefficient can be evaluated easily at a reliability test for evaluating a charge retention characteristic of a floating gate at the application of a gate stress or a charge retention characteristic of the floating gate at the application of a drain stress.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of writing and erasing data.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory device in which data can be written and erased, a high voltage detecting function for enabling multiple selection of memory cells is added to an X, Y address input circuit, so that the semiconductor memory device can be programmed. Techniques for alleviating the increase in the read / write function test time accompanying the increase in capacity are widely used.

FIG. 6 shows a semiconductor in which a high voltage detection function for enabling multiple selection of memory cells is added to an X, Y address input circuit in order to alleviate an increase in a conventional read / write function test time. 2 shows a configuration of a storage device.

A double gate transistor having a floating gate for storing electric charge and a control gate,
A memory cell array 1 in which a plurality of writable and erasable nonvolatile memory cells are arranged in a matrix, and an X decoder 2 for selecting a word line of the memory cell array 1
And a Y decoder 3 for selecting a bit line of the memory cell array 1, and a high voltage detection for enabling multiple selection of memory cells when the external X address input signal 8 and Y address input signal 9 are high voltage signals. X with circuit 5
It is composed of an address input circuit 6 and a Y address input circuit 7, and by simultaneously recognizing a high-voltage address signal from the outside, it has been possible to simultaneously read / write to a plurality of memory cells.

[0005]

However, the conventional configuration for enabling multiple selection has the following problems. Since the high voltage detection circuit 5 is provided, the circuit scale increases. Further, since the address input circuits 6 and 7 have a function of only detecting whether or not the external address signal is at a high voltage, the gate and drain of the memory cell such as read / write operation are provided. In a mode in which a voltage is applied to both, a plurality of memory cells can be simultaneously selected, but a voltage cannot be simultaneously applied to only a gate or a drain only to a plurality of memory cells.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems by using a writable and erasable non-volatile memory as a storage medium, suppressing an increase in circuit scale, and providing a multiple selection function of an X decoder and a Y decoder. It is an object of the present invention to provide a semiconductor memory device which can be independently controlled, whereby a voltage can be applied not only to a read / write operation but also to only a gate of a plurality of memory cells or only a drain of a plurality of memory cells. Therefore, the test time can be greatly reduced in the reliability test for evaluating the charge retention characteristics of the floating gate due to the application of gate stress or the charge retention characteristics of the floating gate due to the application of drain stress. The ability of the floating gate to retain the charge by applying gate stress, or the floating by applying drain stress It is possible to greatly shorten the screening test time due to charge retention ability of over bets.

Further, in addition to the function of applying only a gate or a drain voltage to the plurality of memory cells, a mode is provided in which a plurality of applied voltages are switched and controlled when a voltage is applied. It is possible to easily evaluate the voltage acceleration coefficient in the reliability test for evaluating the charge retention characteristic of the floating gate due to the application of the drain stress or the charge retention characteristic of the floating gate.

[0008]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a double gate transistor having a floating gate for storing electric charges and a control gate, and performs writing and erasing. A memory cell array in which a plurality of possible nonvolatile memory cells are arranged in a matrix, an X decoder having a function of selecting a word line of the memory cell array in accordance with a normal address, and also having a function of performing multiple selection; In addition to the function of selecting a bit line of the memory cell array in accordance with a normal address, a Y decoder having a function of performing multiple selection, and a word line multiple selection signal or a bit line multiple selection signal that are independently controlled by an external control signal. And a control circuit for generating the data.

With this configuration, the increase in circuit scale is suppressed,
In addition, it is possible to independently control the multiple selection function of the X decoder and the Y decoder, and to apply a voltage to only the gates of a plurality of memory cells or only the drains of the plurality of memory cells as well as the read / write operation. Therefore, the test time can be greatly reduced in the reliability test for evaluating the charge retention characteristics of the floating gate due to the application of gate stress, or the charge retention characteristics of the floating gate due to the application of drain stress. In addition, it is possible to drastically shorten the screening test time due to the ability to retain the charge of the floating gate by applying the gate stress or the ability to retain the charge of the floating gate due to the application of the drain stress.

Further, the semiconductor memory device of the present invention comprises a double gate transistor having a floating gate and a control gate for storing electric charges, and a plurality of writable and erasable nonvolatile memory cells are arranged in a matrix. A memory cell array having a function of selecting a word line of the memory cell array in accordance with a normal address, an X decoder having a function of switching an applied voltage to select multiple word lines, and a memory cell array of the memory cell array. In addition to the function of selecting a bit line in accordance with a normal address, a Y decoder having a function of switching an applied voltage to multiple select a bit line, and a word line multiple selection signal or a bit line multiple selection by an external control signal And a control circuit for independently generating signals.

With this configuration, in addition to the function of applying only the gate or drain voltage to the plurality of memory cells, it is possible to switch and control a plurality of applied voltages when applying a voltage. This makes it easy to evaluate the voltage acceleration coefficient in the reliability test for evaluating the charge retention characteristics or the charge retention characteristics of the floating gate due to the application of drain stress.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a circuit configuration of a semiconductor memory device according to an embodiment of the present invention. A memory cell array 1 comprising a plurality of non-volatile memory cells which are composed of a double gate transistor having a floating gate and a control gate for accumulating electric charges and which can be written and erased, and a word of the memory cell array 1 In addition to a function of selecting a line according to a normal address, an X decoder 2 having a function of switching an applied voltage to multiple select a word line and a bit line of the memory cell array 1 are selected according to a normal address. In addition to the function, a Y decoder 3 having a function of switching the applied voltage to multiple select a bit line, and a control circuit for independently generating a word line multiple select signal or a bit line multiple select signal by an external control signal And 4.

Upon receiving various control signals CONT from outside,
The control circuit 4 drives the multiple selection function and the applied voltage switching function of the X decoder 2 or the Y decoder 3 by the decode circuit control signals 4a, 4b, 4c, 4d generated at the time of the mode independently set, so that the plurality of memories can be controlled. A voltage can be applied only to the gate of the cell or only to the drain of a plurality of memory cells, and the applied voltage can be switched.

In the following configuration, a voltage is applied only to the gates of all the memory cells or only the drains of all the memory cells, and the switching of the applied voltage is limited to the switching of two types of voltages. According to the present invention, two or more types of applied voltages are switched when multiple selection is performed on memory cells of a limited block according to the purpose, or when multiple selection is performed on a gate of a memory cell or a drain of a memory cell. It is also effective in some cases.

FIG. 2 is a truth table of modes and internal control signals of the semiconductor memory device according to the present embodiment. In addition to the various rewrite and read modes set by the conventional control signals CONT0-CONT, a new control signal TST
When "H", four new modes are set by new control signals Ta and Tb, and independent decode circuit control signals 4a, 4b, 4c and 4d are generated in each mode.

At the time of TST = “H”, first, Ta =
When “L” and Tb = “L”, the word line batch selection mode (voltage A) is set, and the control circuit decode signal control signal 4a = “H”, 4b = “L”, 4c =
“L”, 4d = “L” is generated. Ta = “H”, T
b = “L”, word line batch selection mode (voltage B)
Are set in the control circuit, and the decode circuit control signals 4a = “L”, 4b = “H”, 4c = “L”, 4d in the control circuit
= “L” is generated. Also, Ta = “L”, Tb =
In the case of "H", the bit line batch selection mode (voltage C) is set, and the decoding circuit control signals 4a = "L", 4b = "L", 4c = "H", 4d =
“L” is generated. When Ta = “H” and Tb = “H”, the bit line collective selection mode (voltage D) is set, and the decoding circuit control signal 4a =
"L", 4b = "L", 4c = "L", 4d = "H" are generated.

As described above, a new mode is set by further increasing the number of new control signals, and by increasing the number of decoding circuit control signals to be generated, multiplexing is performed on memory cells of a limited block according to the purpose. It is also possible to carry out selection or to set two or more types of applied voltage switching when multiple selection of the gate of the memory cell or the drain of the memory cell.

FIG. 3 is a control circuit diagram of the semiconductor memory device according to the present embodiment. On the basis of the mode and the internal control signal truth table, the control circuit according to the present invention converts the new control signals TST, Ta, Tb from the decode circuit control signals 4a, 4b.
b, 4c and 4d are generated.

FIG. 4 is an X decoder circuit diagram of the semiconductor memory device according to the present embodiment. Decode circuit control signal 4a generated in the control circuit = “H” or 4
By receiving b = "H", the gates of all memory cells can be collectively selected unconditionally regardless of the address decode signal. Further, when 4a = "H" and 4b = "L", all the memory cells are selected. The voltage A can be supplied to the gates of the cells, and the voltage B can be supplied to the gates of all the memory cells when 4a = "L" and 4b = "H".

Further, by further increasing the number of decoding circuit control signals, multiple selection is performed on memory cells of a limited block according to the purpose, and switching of applied voltage when multiple selection of gates of memory cells is performed. It is also possible to set two or more types.

FIG. 5 is a Y decoder circuit diagram of the semiconductor memory device according to the present embodiment. Decode circuit control signal 4c generated in the control circuit = “H” or 4
By receiving d = “H”, drains of all memory cells can be unconditionally selected collectively regardless of the address decode signal. Further, when 4c = “H” and 4d = “L”, all the memory cells are drained. The voltage C can be supplied to the drains of the cells, and the voltage D can be supplied to the drains of all the memory cells when 4c = "L" and 4d = "H".

Further, by further increasing the number of decoding circuit control signals, multiple selection can be performed on memory cells of a limited block according to the purpose, and switching of the applied voltage at the time of multiple selection of the drain of the memory cell can be performed. It is also possible to set two or more types.

[0024]

As described above, a plurality of writable and erasable non-volatile memory cells are formed in a matrix and are constituted by a double gate transistor having a floating gate and a control gate for storing electric charges. A memory cell array, an X decoder having a function of selecting a word line of the memory cell array according to a normal address, and also having a function of multiple selection, and selecting a bit line of the memory cell array according to a normal address. A Y-decoder having a function of performing multiple selection in addition to a function of performing multiple selection, and a control circuit which independently generates a word line multiple selection signal or a bit line multiple signal according to an external control signal. X-decoder and Y
It is also possible to independently control the multiple selection function of the decoder, and it is possible to apply a voltage not only to the read / write operation but also to only the gates of a plurality of memory cells or only the drains of the plurality of memory cells. In a reliability test for evaluating the charge retention characteristics of a floating gate due to stress application or the charge retention characteristics of a floating gate due to application of drain stress, the test time can be significantly reduced. It is possible to greatly reduce the screening test time based on the charge retention ability of the floating gate or the charge retention ability of the floating gate due to the application of drain stress.

A memory cell array comprising a plurality of non-volatile memory cells which are composed of a double gate transistor having a floating gate and a control gate for storing electric charges and which can be written and erased, and which are arranged in a matrix;
In addition to the function of selecting a word line of the memory cell array according to a normal address, an X decoder having a function of switching an applied voltage to multiple select word lines, and a method of setting a bit line of the memory cell array to a normal address. In addition to the function of selecting, a Y decoder having a function of switching the applied voltage to multiple select a bit line, and independently generating a word line multiple select signal or a bit line multiple select signal by an external control signal In addition to the function of applying a voltage only to the gate or the drain to the plurality of memory cells, it is possible to switch and control a plurality of applied voltages at the time of applying a voltage, and to apply a gate stress to the plurality of memory cells. Charge retention characteristics of the floating gate due to Facilitated the voltage acceleration factor assessment in reliability test for evaluating the.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor memory device according to an embodiment of the present invention;

FIG. 2 is a truth table of modes and internal control signals of the semiconductor memory device according to one embodiment of the present invention;

FIG. 3 is a control circuit diagram of the semiconductor memory device according to one embodiment of the present invention;

FIG. 4 is an X decoder circuit diagram of the semiconductor memory device according to one embodiment of the present invention;

FIG. 5 is a Y decoder circuit diagram of the semiconductor memory device according to one embodiment of the present invention;

FIG. 6 is a circuit configuration diagram of a conventional semiconductor memory device for the purpose of multiple selection of memory cells at the time of writing and reading;

[Explanation of symbols]

 Reference Signs List 1 memory cell array 2 X decoder 3 Y decoder 4 control circuit 4a X decoder control signal (for supplying voltage A) 4b X decoder control signal (for supplying voltage B) 4c Y decoder control signal (for supplying voltage C) 4d Y decoder control signal (For supplying voltage D) CONT Control signal from outside EW Internal control signal for rewriting / reading TST Control signal from new outside Ta Control signal from outside Tb New control signal from outside

Claims (7)

[Claims] 1. A semiconductor memory device comprising a memory cell as a storage medium and a control circuit for independently generating a word line multiplex selection signal or a bit line multiplex signal by an external control signal. 2. A memory cell array in which a plurality of memory cells are arranged in a matrix using a memory cell as a storage medium, and a function of selecting a word line of the memory cell array according to a normal address and a function of performing multiple selection. 2. The semiconductor device according to claim 1, further comprising an X decoder, and a Y decoder having a function of selecting multiple bits in addition to a function of selecting a bit line of the memory cell array according to a normal address. Storage device. 3. The memory cell according to claim 2, wherein said memory cell comprises a double gate transistor having a floating gate and a control gate for storing electric charges, and comprises a writable and erasable nonvolatile memory. Semiconductor storage device. 4. The memory cell according to claim 1, wherein said memory cell comprises a double gate transistor having a floating gate and a control gate for storing electric charges, and comprises a flash memory which can be electrically written and erased. 3. The semiconductor memory device according to 2. 5. A memory cell array in which a plurality of memory cells are arranged in a matrix using a memory cell as a storage medium, and a function of selecting a word line of the memory cell array in accordance with a normal address, and switching an applied voltage to change a word. An X decoder having a function of multi-selecting a line, and a Y decoder having a function of multi-selecting a bit line by switching an applied voltage, in addition to a function of selecting a bit line of the memory cell array according to a normal address. And a control circuit that independently generates a word line multiple selection signal or a bit line multiple selection signal by an external control signal. 6. The memory cell according to claim 5, wherein said memory cell comprises a double gate transistor having a floating gate and a control gate for storing electric charges, and comprises a writable and erasable nonvolatile memory. Semiconductor storage device. 7. The memory cell according to claim 1, wherein said memory cell comprises a double gate transistor having a floating gate for storing electric charge and a control gate, and comprises a flash memory which can be electrically written and erased. 6. The semiconductor memory device according to 5.