JP2000011635A - Fifo memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a FIFO memory of a large capacity capable of a high speed operation for an FIFO(first in first out) memory. SOLUTION: A two-port RAM register 1, register circuit 6 and output selector circuit 7 are provided, the register circuit 6 stores data of address 0 and the two-port RAM 1 stores other data in advance. The output selector circuit 7 is controlled so that the register circuit 6 outputs data when reading at address 0 and the two-port RAM1 outputs data in other case. This reduces the access time of FIFO to attain a high speed operation allowing the working frequency to be raised.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FIFO (first-in first-out) memory, and more particularly to a circuit configuration method thereof.

[0002]

2. Description of the Related Art A FIFO memory can be constituted by adding a counter circuit for sequentially generating addresses and a control circuit for writing and reading to a two-port RAM. By using one port of the two-port RAM exclusively for writing data and the other port exclusively for reading data, writing and reading can be performed asynchronously and at high speed. Japanese Patent Application Laid-Open No. 3-156788 discloses a FIFO memory circuit using a two-port RAM. According to this method, a large-capacity FIFO can be easily realized by using a large-capacity two-port RAM.

FIG. 9 shows a conventional FIF having such a configuration.
2 shows a circuit diagram of O. FIG. 1 is a two-port RAM.
Writing to 1 is controlled by a memory write signal 12 from the write control circuit 2 and a write address signal 13 from the write address counter circuit 3. Data given to the data input 10 is sequentially written by increasing the write address signal 13 in each write cycle. For reading from 1, the data is output from the data output 17 in the same order as the writing was performed by the memory read signal 14 from the read control circuit 4 and the read address signal 15 from the read address counter circuit 5. The two signals on the write side, the write enable signal XWE and the write reset signal XWRS, are fetched in synchronization with the write clock WCK. That is, the write cycle is WCK with XWE being "L".
Starts at the rising edge of the write address counter circuit 3
Is reset when WCK rises with XWRS at "L". Similarly, the read enable signal XRE and the read reset signal XRRS are taken in at the rise of the read clock RCK. When the reset is performed, the value of each counter becomes 0, and the physical address 0 of the 2-port RAM is selected. After reaching the maximum address, the counter remains at 0.
It returns to and changes in a loop.

FIG. 10 is a timing chart showing a read operation of the FIFO shown in FIG. The access time tAC is from the rise of RCK to the data output. The access time is the largest factor that determines the operation speed of the FIFO. To reduce this, the read counter circuit counts up at the falling edge of RCK delayed by a half cycle. That is, since the address to be accessed is determined before the rise of the RCK, the memory read signal can be immediately applied to the two-port RAM to start the access. In principle, most of the access time is occupied by the access time tACM of the 2-port RAM. However, there is a special timing at reset,
This in effect limits access time. Specifically, this is the operation in cycle 0 in FIG.
The data at address 0 is read at the same time as resetting by setting both RS and XRE to "L". Then R
After the rise of CK, the read counter circuit is reset, and the address changes to 0. If an asynchronous type is used for the two-port RAM, correct data appears after the address is changed and determined, and only the access time in cycle 0 needs to be delayed. However, if a synchronous type is used, before the memory read signal is given. The address must be fixed in the address. In FIG. 10, a delay is applied to the rise of the memory read signal, and the memory read signal rises at t0 after the address changes to 0.

[0005]

When the reset and the read operation overlap as described above, the read address changes after the rise of RCK, and the address 0 after the change is read.
Data must be read. 2-port RAM
The method of handling differs depending on whether the synchronous type or the asynchronous type is used, but in any case, the operation clock of the FIFO can only be adjusted to cycle 0, and this has actually determined the maximum operation frequency.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and has as its object to provide a large capacity F which can operate at high speed.
It is to provide an IFO memory.

[0007]

According to a first aspect of the present invention, there is provided a FIFO memory for storing data of a plurality of addresses.
A port RAM, a register circuit for storing data of a single address, and an output selector circuit for selecting one of the outputs of the two and outputting the data to the outside, and writing the data at address 0 to the register circuit; The address data is written to the 2-port RAM. When reading address 0 after read reset, control the output selector circuit to output data of the register circuit, and to read data of another address, to output data of the 2-port RAM. Features.

A FIFO memory according to a second aspect of the present invention is a two-port RAM for storing data of a plurality of addresses.
And a register circuit for storing data of a single address;
An output selector circuit for selecting one of the two outputs and outputting data to the outside is provided. Data of all addresses is written to the 2-port RAM, and data of address 0 is written to the register circuit in parallel. The output selector circuit is controlled so as to output the data of the 2-port RAM in the case of the read without the read reset operation, and to output the data of the register circuit in the case of performing the read reset operation and the read simultaneously. And

[0009]

The data of the address 0 is always held in the register circuit. 2-port RAM for addresses other than 0
The data is read from the register circuit when the data is read simultaneously with the reset, that is, when the address is 0. Since the access time of the register circuit is faster than that of a two-port RAM, data can be read at a high speed even when a reset operation is added.

[0010]

FIG. 1 is a block diagram of a FIFO memory showing a first embodiment according to the present invention. Write data is sent from the data input 10 to the register circuit 6 and the 2-port R
AM 1, and these output data are read from the data output 17 through the output selector circuit 7. The write address counter circuit 3 counts up each time a write operation is performed, and the write address signal 13 is sent to 1. When the write address signal 13 is the address 0, the register control signal 30 is issued from the write control circuit 2 and writing to 6 is performed. Similarly, from 2 the memory write signal 12 is sent to 1 each time data is written, and data of all addresses including address 0 is written to the 2-port RAM 1. On the other hand, also on the read side, the read address signal 15 from the read address counter circuit 5 and the memory read signal 14 from the read control circuit 4 are 2
Data is read out in the same order as written by being sent to the port RAM1. When the read address signal 15 is the address 0, the register read signal 31 is issued from 4 and the output selector circuit 7 is controlled. As a result, 6 data is read from the data output 17 when the address is 0, and 1 data is read when the address is not 0. By taking the above configuration,
The data holding means is changed in such a manner that the data of the address 0 is the register circuit 6 and the others are the two-port RAM 1.

FIG. 3 shows a register read signal 3 according to the present invention.
1 is a circuit for generating the “1”. That is, a part of the read control circuit 4 included in FIG. 1 is shown. The read enable signal XRE is latched by the D flip-flop 401 at the rise of the read clock RCK, and the signal XRE becomes "
If LCK is “H”, the output of the AND circuit 402 becomes “H” while the RCK is “H”.
Indicates that read address signals RA0 to RAn are all "L".
The output becomes "H" at the time of. Therefore, the register read signal 31 becomes "H" only when address 0 is read.
On the other hand, the memory read signal 15 becomes "H" for reading all addresses and accesses the 2-port RAM.

FIG. 6 is a timing chart showing the operation of the circuits of FIGS. In cycle 0, both the read reset signal XRRS and the read enable signal XRE are “L”.
And reset and read simultaneously. Hereafter, XR
RS is kept at “H” and XRE is kept at “L”, and the read clock RCK is applied to sequentially read data. In cycle 0, the read counter circuit is reset after the rise of RCK, and the read address signal changes to 0.
Then, the register read signal also changes to H, and data of the register circuit is output from the data output. At the falling edge of RCK, the register read signal and memory read signal are "L".
, And the read address is counted up to 1. After cycle 1, the register read becomes "L", only the memory read becomes "H", and the data output is the read data from the 2-port RAM. Conventional FI
In FIG. 10 showing the FO, a delay is given from RCK to the rise of the memory read signal. However, in the present invention, when reset and reading are performed simultaneously, the data in the register is read, so that such a delay is not given. The data at address 0 can be read out normally. Therefore, the time t1 or t2 from when RCK rises to the time when the memory read signal rises can be significantly reduced as compared with the conventional case. The access time tAC of the FIFO when reading data from the two-port RAM is a time obtained by adding the access time tACM of the two-port RAM to t1 or t2. On the other hand, the access time in cycle 0 is the sum of t0 from the rise of RCK to the rise of the register read signal and the register read time tACR. Since the register read signal detects that the read address is 0, t
1, t2, but the register circuit has only one address data storage circuit, and its read time tA
CR is much faster than the two-port RAM access time tACM. Therefore, F in cycle 0
Access time tAC as IFO is 2-port RAM
From the first cycle in which data is read from the first cycle. In cycle 0, a memory read signal is issued at the same time as the register read signal,
Access to is made. In a two-port RAM, the read address changes to 0 after a memory read signal is issued, so that when the synchronous type is used, normal reading cannot be performed. However, since what is output to the outside is the data of the address 0 stored in the register circuit, it is possible to perform normal and high-speed reading as a FIFO.

FIG. 5 shows a register write signal 3 according to the present invention.
This is a circuit that generates 0. That is, a part of the write control circuit 2 included in FIG. 1 is shown. The write enable signal XWE is latched by the D flip-flop 501 at the rise of the write clock signal WCK, and XWE
Is "L", and NOR during WCK is "L"
The output of the circuit 502 becomes “H”. Also, the NOR circuit 5
04 is all write address signals WA0 to WAn "
The output becomes "H" at the time of "L", so that the register write signal 30 becomes "H" only when writing the address 0. On the other hand, the memory write signal 12 becomes "H" for writing of all addresses. And accesses the 2-port RAM.

FIG. 8 is a timing chart showing the operation of the circuits of FIGS. In cycle 0, both the write reset signal XWRS and the write enable signal XWE are "L".
And reset and write simultaneously. Hereafter, XW
RS is kept at “H” and XWE is kept at “L”, and the write clock WCK is applied to sequentially perform writing. In each cycle, the write counter circuit counts up in synchronization with the rise of WCK. The reset of the write counter circuit is also synchronized with the rise of WCK. On the other hand, the memory write signal changes to “H” after the fall of WCK, and writing is performed during the “L” period of WCK. As the data to be written, the state of the data input at the time of the falling edge of the memory write signal at which the writing ends is captured. As is apparent from this figure, the write address is determined before the start of the write operation, and there is no need to give a special delay to the memory write signal regardless of the presence or absence of the reset signal. Although the register write signal is generated during the "L" period of the WCK in cycle 0, the signal generation is not delayed since the write address has already been set to "0".
In cycle 0, a memory write signal and a register write signal are issued, and writing is performed on the 2-port RAM and the register circuit. As shown in FIG. 6, in the read operation, when the address is 0, the data of the register circuit is always output. Therefore, it is not necessary to write to the address 0 of the two-port RAM. Originally, the configuration of FIG. 1 does not require the memory cell itself equivalent to the address 0 of the two-port RAM,
Since the circuit scale is small and there is no influence on the characteristics, there is no need to delete the access or prohibit the access.

FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a block diagram of an IFO memory. The difference from FIG. 1 is that the read control circuit 4
This is that the read reset signal XRRS is used to generate 1 instead of determining that the read address is 0. Therefore, the read address 15 is not input to 4.

FIG. 4 shows the register read signal 31 shown in FIG.
FIG. 3 is a diagram illustrating a specific example of a circuit that generates the data. That is, a part of the read control circuit 4 of FIG. 2 is shown. The output of the AND circuit 402 is RCK when XRE is "L".
Becomes "H" during the period of "H". Also, an AND circuit 405
Is output when RCK is "L" when XRRS is "L".
It becomes "H" during the period of "H." Therefore, the register read signal 31 is issued only when the reset and the read are performed at the same time.Figure 7 is a timing chart showing the operation of the circuits of FIGS. XRRS and XRE at 0
Are both "L", a register read signal is generated after the rise of RCK. Since the period t0 does not have to wait for the read address to change to 0 as shown in FIG. 5, it is greatly shortened, and can be made equivalent to the memory read signals t1 and t2. As a result, the access time tAC of the FIFO in cycle 0 is much faster than in cycle 1 and thereafter. When the register is read by the reset signal as described above, it is necessary to write data to the two-port RAM at the address 0. The reason is that when the read reaches the final address and the read address signal becomes 0 again, the data is not read from the register but is read from the two-port RAM. Despite such restrictions, tAC in cycle 0 in FIG. 7 is faster than in FIG.

[0017]

As described above, according to the present invention, when read reset and read are simultaneously performed, data can be read at high speed because a register circuit is used.
In addition, when reading from the two-port RAM, there is no need to consider the timing of the reset operation, and there is no need to delay access. Therefore, the access time of the FIFO can be shortened and the operating frequency can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram of a FIFO memory according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a FIFO memory according to a second embodiment of the present invention;

FIG. 3 is a circuit for generating a register read signal according to the first embodiment of the present invention;

FIG. 4 is a circuit for generating a register read signal according to a second embodiment of the present invention.

FIG. 5 is a circuit for generating a register write signal according to the present invention.

FIG. 6 is a timing chart showing a read operation of the first embodiment according to the present invention.

FIG. 7 is a timing chart showing a read operation of the second embodiment according to the present invention.

FIG. 8 is a timing chart showing a write operation of the embodiment according to the present invention.

FIG. 9 is a block diagram of a conventional FIFO memory.

FIG. 10 is a timing chart showing a read operation of a conventional FIFO memory.

[Explanation of symbols]

 1 2-port RAM 2 write control circuit 3 write address counter circuit 4 read control circuit 5 read address counter circuit 6 register circuit 7 output selector circuit WCK write clock signal XWE write enable signal XWRS write reset signal RCK read clock signal XRE read enable signal XRRS Read reset signal

Claims (2)

[Claims] 1. A two-port RAM for storing data of a plurality of addresses, a register circuit for storing data of a single address, and an output selector circuit for selecting one of the outputs of the two and outputting the data to the outside, Data at address 0 is written to the register circuit, and data at another address is written to the 2-port RAM. The output selector circuit is controlled so as to output data of the register circuit when reading address 0 after read reset and to output data of the 2-port RAM when reading another address. FIFO memory. 2. A semiconductor device comprising a two-port RAM for storing data of a plurality of addresses, a register circuit for storing data of a single address, and an output selector circuit for selecting one of the outputs of the two and outputting the data to the outside. Data of all addresses is written to the 2-port RAM, and addresses 0
Is written into the register circuit. In the case of reading without read reset operation, the 2-port RAM
Wherein the output selector circuit is controlled to output the data of the register circuit when the read reset operation and the read operation are performed simultaneously.