JP2000010861A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up the operation of an information processor while suppressing increase in the capacity of a DRAM by functioning as a secondary cache for a specific area. SOLUTION: In the figure, 101 is a CPU and has a primary cache inside. When necessary data are not present in the primary cache or when the CPU 101 makes a request to access a part distinctively other than the primary cache, it is shown as an external access request of the CPU 101 on a CPU bus 106. A BUS control circuit 103 receives the external access request from the CPU 101, an internally generated refresh request, etc., and controls the DRAM 102, a ROM 104, and an I/O device 105. The DRAM 102 is constituted on the CPU bus and a control signal to the DRAM 102 is outputted by the BUS control circuit 103, but write data themselves from the CPU 101 can be received directly by the DRAM 102 and read data outputted from the DRAM 102 can be received directly by the CPU 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly, to an information processing apparatus which functions as a secondary cache for a specific area and achieves high speed while suppressing an increase in DRAM capacity.

[0002]

2. Description of the Related Art Recently, processing performance has been improved due to an increase in the internal operating frequency of a CPU. On the other hand, however, the delay in external access by the CPU occupies a large weight as a factor hindering the improvement in processing performance. It is becoming like.

As a method of improving this, there is a method of having a large-capacity high-speed memory corresponding to the internal operating frequency of the CPU inside the CPU. However, the size of the built-in memory is limited. , Compared to main memory
They have only a few sizes. However, this still has an effect due to the locality of program execution, but improvement is desired. As a method of further increasing the speed, a secondary cache composed of an SRAM is provided outside the CPU, which is slower than a built-in primary cache, but can be accessed at a higher speed than a main memory composed of a DRAM. . However, the secondary cache is a high-speed SRAM
Therefore, there were various problems.

As a method for solving this problem, Japanese Patent Laid-Open No. 7-2
No. 00404, there is a method described in SR
This is a secondary cache composed of AM, which aims to address the problems of mounting area, power consumption, and cost.
By constructing a memory and integrating it with the control logic and the tag memory on the same chip, the problems of mounting area, power consumption and cost are improved.

[0005]

According to the above prior art, there is a problem that it is necessary to adopt a special configuration in which the components are integrated on the same chip. In addition, conventional DRAM
Instead, a synchronous DRAM (hereinafter, sometimes referred to as an SDRAM) that performs external interface of the DRAM in clock synchronization has been used. This is not so different from the conventional DRAM in terms of the internal structure of the DRAM.
Although there is little difference in performance from the RAM, there is a feature that continuous data can be transferred every clock.

A normal CPU has a primary cache internally and most of external accesses are transferred by a plurality of words. Therefore, by using an SDRAM, it is possible to achieve almost the same performance as a secondary cache constituted by an SRAM. . However, a problem here is that not all data and instructions are stored on the SDRAM, and a low-speed device such as a ROM must be accessed. Ideally, first transfer to SDRAM once,
It is only necessary to be able to access DRAM only, but SDRAM
Such a space is required in that space, which causes an increase in cost. Therefore, such a configuration cannot be adopted in many cases. In this case, there is a problem that the processing performance is greatly reduced by low-speed device access. In the present invention,
An object of the present invention is to provide an information processing device that solves this problem.

[0007]

According to the present invention, in response to a read request from a CPU for a specific area,
A means for managing whether or not a copy of the read request data exists in the DRAM; if a copy of the read request data exists in the DRAM, the read data is supplied from the DRAM instead of the original target device, and If it does not exist, the read access is performed from the original target device, the read data is supplied to the CPU, and a copy of the read data is also stored in the DRAM, thereby functioning as a secondary cache for a specific area. , D
Higher speed is achieved while suppressing an increase in RAM capacity.

According to the second aspect of the present invention, a start address and a size of a space for storing a copy of data in a specific area according to the first aspect of the present invention can be set, so that the configuration is optimally adapted to the system.

According to the third aspect of the present invention, it is possible to set so that when a CPU issues a write request to a space for storing a copy of data in a specific area according to the first aspect of the present invention, the execution is not performed. To prevent software from being accidentally rewritten.

According to a fourth aspect of the present invention, when the CPU issues a write request to a space for storing a copy of the data in the specific area according to the first aspect of the present invention, the CPU has means for notifying the CPU of an unauthorized access. Recognize software errors.

[0011]

FIG. 1 is a block diagram for explaining an embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a CPU, which internally has a primary cache. CPU 101 is 1
If there is no necessary data in the next cache or C
If the PU explicitly requests access outside the primary cache, it is indicated on the CPU bus 106 as an external access request of the CPU 101. BUS control circuit 103
Receives an external access request from the CPU 101, an internally generated refresh request, etc.
04, controlling the I / O device 105; In this embodiment, the DRAM 102 is configured on a CPU bus,
The BUS control circuit 103 outputs a control signal to the M102, but the write data itself from the CPU 101 can be directly received by the DRAM 102 (without receiving the BUS control circuit 103 once).
The read data output from the DRAM 102 is CP
U101 can receive it directly. 1
A local bus 07 is separated from the CPU bus 106.

In the present embodiment, the ROM of 104 is 8 MB,
The DRAM 102 has a capacity of 16 MB, and the address space of the DRAM 102 used as a secondary cache is as follows.
CPU1 as start address and end address
01 (however, in this embodiment, the end address is set so that the capacity from the start address is 1, 2, 4, 8,... (Word)). Whether or not to enable the secondary cache is also determined by the CPU 101 as a cache enable register.
It can be set from. With such a configuration, an optimal configuration can be selected for the data capacity of the secondary cache configured on the DRAM 102 according to the system.

In this embodiment, the secondary cache is constructed by the direct mapping method. For example, all RO
1MB, which is 1/8 of M capacity,
In the case of allocating as the data RAM of the secondary cache, in the present embodiment, the secondary cache is configured by the direct mapping method,
Since the cache area of the AM is determined, the information required as a TAG includes address information for 3 bits,
One bit of data indicating valid / invalid is required.

This part will be described in detail.
Since the end address of the data area as the secondary cache configured on the AM 102 is set so that the space from the start address is 1, 2, 4, 8,... (Word), the secondary cache When the data exists in the DRAM, the lower address (for 1 MB in this description) in the ROM space can be the same address in the DRAM space. Then, only the upper address is different. Therefore, from the lower address of the DRAM, RO
The lower address (1 MB) of the M address can be determined. After that, the upper address (for 3 bits) for each secondary cache data and the 1-bit data indicating whether there is valid data in the TAG RAM are stored in the TAG RAM. It will be good to keep it.

FIG. 2 is a diagram showing a configuration of a secondary cache control circuit formed in the BUS control circuit 103. In FIG.
210 is a control circuit for controlling the secondary cache, 201 is a request address register for temporarily storing the address of the access request, and 202 is a TAG RAM for storing management information of the secondary cache. Here, the above-mentioned management information of data configured on the DRAM as a data area of the secondary cache is held. 20
3,204 is D as RAM for secondary cache data
A start address register and an end address register for holding start / end points of addresses formed on the RAM. In this embodiment, as described above, the end address is 1, 2, 4, 8,.
d) is set. Reference numeral 205 denotes a cache enable register for setting valid / invalid of the secondary cache function. The control registers of these 203, 204 and 205 are set by the CPU 101.

Reference numeral 206 denotes a comparator (Comp), which outputs an output result of the request address register 201 and a TAG.
It functions to compare information in the RAM 202. The comparator 206 also manages status information (TAG RAM information is valid / invalid) output from the TAG RAM 202 and information of the cache enable register 205 (whether the secondary cache is valid). Then, the request address is in the secondary cache target area, the data cached on the DRAM matches the request address, and it is also determined whether the data should be used.

Reference numeral 207 denotes a RAM controller, which is controlled by the control circuit 210. The RAM controller 207 receives the output results of the start address register 203, the end address register 204, and the cache enable register 205, and uses the information when accessing the DRAM as secondary cache data. The address of the DRAM. Conversely, when the cache enable register 205 is valid, the CPU accesses the start address register 203 and the end address register 20 as CPU accesses.
When the access request of the address space in No. 4 is received,
The DRAM access is not performed and the control circuit 210 is notified that the access is unauthorized, and the control circuit 210
01 is notified of unauthorized access. 208 is R
An OM controller, which controls ROM access.

FIG. 3 shows that the secondary cache hits (DRA
FIG. 3 is a diagram showing a sequence when valid data is present on M and this data is used instead of ROM data. In FIG. 3, the request address is held in the request address register at the timing of (1). You. The request address here is a ROM address, and since cache data exists on the DRAM, Comp output is Hi.
gh. GNT from arbiter not shown at timing (2)
Sampling the signal to confirm that access has been granted,
The DRAM access as the secondary cache access is started based on the information of Comp = High. From the timing of (3), the DRAM read data becomes C
Since output starts on the PU bus (CPU_D), DVa
By setting lid_ to Low, it indicates that read request data is returned to the CPU. At the timing of (4), the specified data amount (here, 4 words) was passed to the CPU, so that DValid_ was set to Hig.
h and prepare for the next access.

FIG. 4 is a diagram showing a sequence of a secondary cache miss (when valid data does not exist on the DRAM even though the cache enable bit is valid). At the timing of (1), Request Address is held in the request address register. The request address here is a ROM address, but since there is no cache data on the DRAM, the Comp output is low. GNT from arbiter not shown at timing (2)
Sampling the signal to confirm that access has been granted,
ROM read is started from the information of Comp = Low,
TAG RAM for the next level 2 cache access
Stores data relating to the ROM data accessed this time. TAG RAM control is performed by TAG RA at the timing of (3).
Switch to M-read so that extra data is not written to the TAG RAM. In the present embodiment, the timing of (4) is three clocks before the ROM determines the fourth data on the local bus (ROM_D), so that write control is requested to the DRAM and read from the ROM. 3
The data for the number is output to the CPU bus and DValid_ is set to L
Set to ow to indicate that data for the read request is on the CPU bus. Since the specified data amount has been passed to the CPU at the timing of (5), DValid_ is set to High to prepare for the next access.

[0020]

According to the first aspect of the present invention, the CPU:
In response to a read request for a specific area from the device, a means for managing whether or not a copy of the read request data exists in the DRAM is provided. If a copy of the data of the read request exists in the DRAM, the copy is performed instead of the original target device. DRA
The read data is supplied from the M, and when the data does not exist in the DRAM, the read access is performed from the original target device, the read data is supplied to the CPU, and the copy is stored in the DRAM. Function as a secondary cache for a specific area,
Higher speed can be achieved while suppressing an increase in RAM capacity.

The effect corresponding to the second aspect of the present invention: the first aspect
Since the start address and size of the space for storing the copy of the data in the specific area can be set in the invention of the first aspect, an optimum configuration can be adopted according to the system.

Advantageous Effects Corresponding to the Invention of Claim 3: Claim 1
When the CPU issues a write request to a space for storing a copy of data in a specific area according to the invention of the present invention, it is possible to set so as not to execute the write request, so that it is possible to prevent software from being erroneously rewritten. .

Advantageous effect corresponding to the invention of claim 4: Claim 1
When the CPU issues a write request to a space for storing a copy of data in a specific area according to the invention of the present invention, the CPU has means for notifying the CPU of unauthorized access, so that a software error can be recognized.

[Brief description of the drawings]

FIG. 1 is a main block diagram for explaining an embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a secondary cache control circuit configured in a BUS control circuit 103;

FIG. 3 is a diagram showing a sequence of a hit of a secondary cache (when valid data exists on a DRAM and this data is used instead of ROM data).

FIG. 4 shows a secondary cache miss (DRAM despite cache enable bit being enabled)
FIG. 7 is a diagram showing a sequence when valid data does not exist on the upper part).

[Explanation of symbols]

101: CPU, 102: DRAM, 103: BUS control circuit, 104: ROM, 105: I / O device, 1
06 ... CPU bus, 107 ... Local bus, 201 ...
Request address register, 202 ... TAGR
AM, 203... Start address register, 204
... End address register, 205 ... Cache
Enable register, 206, comparator (Comp),
207 RAM controller, 208 ROM controller, 210 control circuit.

Claims (4)

[Claims] In response to a read request from a CPU for a specific area, a means for managing whether or not a copy of read request data exists in a DRAM is provided. Supply read data from DRAM instead of target device of
An information processing apparatus for performing read access from an original target device when not present in a DRAM, supplying read data to a CPU, and storing a copy of the read data also in the DRAM. 2. The information processing apparatus according to claim 1, wherein a start address and a size of a space for storing a copy of data in a specific area can be set. 3. The method according to claim 1, wherein when the CPU issues a write request to a space for storing a copy of the data in the specific area, the write request can be set not to be executed. Information processing device. 4. The information processing apparatus according to claim 1, further comprising means for notifying the CPU of unauthorized access when the CPU issues a write request to a space for storing a copy of data in a specific area. apparatus.