JP2000004130A - Thin film transistor circuit and semiconductor display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To offset the difference of TFT characteristics and to obtain an image which does not have image uneveness and has high definition and high resolution by making a buffer consist of a differential circuit and a current mirror circuit where a gate potential of respective input and output sides includes the specified number of common thin film transistor TFTs. SOLUTION: A differential circuit is formed by making guide electrodes which are connected to each of (x) pieces of input and output ports 102 and 103 of an input side and an output side of a differential circuit A common and making a source or a drain common potential and TFTs of the input side and the output side are respectively divided into (x) pieces and they are parallelly connected. Also, a current mirror circuit B makes potential of gate electrodes of (y) pieces of TFTs which are connected to sources or drains of (x) pieces of TFTs of the input and output sides of the circuit A common and also connects it to the sources and drains, the current mirror circuit is divided into (y) pieces and they are parallelly connected. Here, the differential circuit and the current mirror circuit uses TFTs whose polarity is opposite with each other and also secures current capacity as TFTs whose sizes are small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a driving circuit for a semiconductor display device using a thin film transistor. In particular, the present invention relates to a differential amplifier circuit used in a drive circuit of an active matrix type semiconductor display device and a buffer using the same. Further, the present invention relates to a semiconductor display device using the driving circuit.

[0003]

[Prior art]

Recently, a technique for manufacturing a thin film transistor (TFT) using a semiconductor thin film formed on an inexpensive glass substrate has been rapidly developed. The reason is that the demand for active matrix type liquid crystal display devices and EL display devices has increased.

An active matrix type liquid crystal display device is
TFTs are arranged in several tens to millions of pixel regions arranged in a matrix, and electric charges entering and exiting each pixel electrode are controlled by a switching function of the TFTs.

FIG. 10 shows a configuration of a conventional active matrix type liquid crystal display device. The shift register and the buffer circuit are generally referred to as a drive circuit, and recently formed integrally with the active matrix circuit on the same substrate. 10
01 is a source signal line side driving circuit, and 1002 is a gate signal line side driving circuit.

Reference numeral 1003 denotes an active matrix circuit in which pixel TFTs 1004 are arranged in a matrix. A pixel electrode is connected to a drain electrode of each pixel TFT 1004. Liquid crystal is sandwiched and sealed between the pixel electrode and the counter electrode. In addition, each pixel TFT
Reference numeral 1004 denotes an auxiliary capacitor 1006 for holding a charge.
Are formed.

There is also known a configuration in which quartz is used as a substrate and a thin film transistor is manufactured using a polycrystalline silicon film.

There is also known a technique for manufacturing a thin film transistor using a crystalline silicon film on a glass substrate by utilizing a technique such as laser annealing. Using this technology, an active matrix circuit and a driver circuit can be integrated on a glass substrate.

In the configuration shown in FIG. 10, an image signal supplied to an image signal line is selected by a timing signal from a shift register circuit of a source signal line side driving circuit. Then, a predetermined image signal is supplied to the corresponding source signal line. Further, a timing signal from the gate signal line side driving circuit is supplied to a corresponding gate signal line (scanning line). The image signal supplied to the source signal line is written to the pixel electrode of the thin film transistor of the pixel selected by the timing signal from the gate signal line.

By repeating the above operation sequentially with appropriate timing, information is sequentially written to each pixel arranged in a matrix.

After writing the image information for one screen (one frame), the image information for the next screen is written. In this way, images are displayed one after another. Usually, the writing of the information for one screen is performed 30 times or 60 times per second.

[0013]

[Problems to be solved by the invention]

Here, FIG. 11 shows an example of the source signal line side driving circuit. 1100 is a clock input terminal, 1101
Is a clock line, 1102 is a start pulse input terminal, 1
103-1105 are shift registers, 1106-111
1 is an inverter type buffer, 1112 is a video signal input terminal, 1113 is a video signal line, 1114 to 1116 and 1120 to 1122 are switches, 1117 to 111
Reference numerals 9 and 1125 to 1127 denote storage capacitors; 1123, a transfer signal input terminal; 1124, a transfer signal line; 1128 to 1130, an analog buffer;
Numerals 1133 are source signal line connection terminals.

In the case of analog gray scale, a video signal that is temporally continuous is used as a gray scale signal input to the source signal line side driving circuit. In the case of the normally white mode (display mode in which white display is performed when no voltage is applied to the liquid crystal), the display is set so as to approach black display as the absolute value of the voltage of the gradation signal increases. Shift registers 1103 to 110
In 5, a start pulse synchronized with the video signal is input to a start pulse input terminal 1102, and is sequentially shifted by a clock pulse input from a clock pulse line. The outputs of the shift registers 1103 to 1105 are input to the sampling circuits via the inverter type buffers 1106 to 1111.

The sampling circuit comprises switches 1114 to
1116 and storage capacitors 1117 to 1119. Switches 1114 to 1116 are sometimes referred to as transmission gates. Switch 1114
1116 are their O.S.
N or OFF is controlled, and in the ON state, the video signal line and the storage capacitors 1117 to 1119 are short-circuited,
Electric charges are stored in the storage capacitors 1117 to 1119. When a start pulse is input and the pulse passes through the shift register, the output of the buffer circuit is inverted and the switch 1
114 to 1116 are OFF.

When the switches 1114 to 1116 are turned off, the charges stored in the holding capacitors 1117 to 1119 are held, and then the switches 1114 to 1116 are turned on.
The potential is maintained until. A transfer signal is input from a transfer signal input terminal between the time when the sampling of one line of video data is completed and the time when the sampling of the next line is started, and the transfer signal is supplied from the transfer signal line. You. The switch 1120
1122 is turned ON, charges are stored in the storage capacitors 1125 to 1127, and the potentials of the storage capacitors 1117 to 1119 are transmitted to the storage capacitors 1125 to 1127. Switch 1
When 120 to 1122 are turned off, the storage capacity 1125
To 1127 are held.

Analog buffers 1128 to 1130 are connected to the holding capacitors 1125 to 1127, and source signal lines 1131 to 1133 are driven via the analog buffers 1128 to 1130. These analog buffers 1128 to 1130 are circuits necessary for driving the source signal line without affecting the potential of the storage capacitor.

Here, the analog buffers 1128 to 11
FIG. 12 shows an example of a circuit 30 conventionally used. Reference numeral 1201 denotes a terminal to which a storage capacitor is connected, which is a signal input terminal. Reference numeral 1202 denotes a terminal to which a source signal line is connected, which is a signal output terminal. 12
03 is a constant current source, 1204 is a constant voltage source, 1205 and 1206 are P-channel TFTs, 1207 and 120
Reference numeral 8 denotes an N-channel TFT. In the analog buffer of FIG. 12, the differential circuit A is configured by a P-channel TFT, and the current mirror circuit B is configured by an N-channel TFT.

The operation of the analog buffer shown in FIG. 12 will be described. Input terminal 12 of the differential circuit connected to the storage capacitor
When the potential of 01 rises, the input current of the current mirror circuit 1210 connected to the negative-phase output of the input terminal 1201 decreases, and the output current of the current mirror circuit 1210 decreases accordingly. On the other hand, the in-phase current at the input terminal increases, whereby the potential at the output terminal 1202 rises and reaches the same potential as the input terminal of the differential circuit. Therefore, the output terminal 1202
Becomes the same potential as the potential of the input terminal.

In recent years, with the rapid increase in the amount of information to be handled, the display capacity has been increased and the display resolution has been increased. Here, examples of display resolutions of commonly used computers are shown below by the number of pixels and the standard name.

Number of pixels (width × length): Standard name 640 × 400: EGA 640 × 480: VGA 800 × 600: SVGA 1024 × 768: XGA 1280 × 1024: SXGA

Recently, in the field of personal computers, software for displaying a plurality of images having different characteristics on a display has become widespread.
XGA and SX with higher display resolution than GA standard
The display device has been shifted to a display device conforming to the GA standard. Active matrix type liquid crystal display devices are also very often used in the field of personal computers. Recently, not only notebook type personal computers but also desktop type personal computers are increasingly used. Was.

Further, the active matrix type liquid crystal display device having a high display resolution is used for displaying a television signal in addition to displaying a data signal in a personal computer.

It is meaningless for such a buffer to have a small current capacity, and a buffer having a somewhat large current capacity is required. When a buffer having a large current capacity is constituted by TFTs, a TFT having a sufficiently large current capacity, that is, a TFT having a large channel width is required. If the size (channel width) of the TFT is simply increased in order to realize a buffer having a sufficiently large current capacity, only the central portion of the TFT functions as a channel, and the end does not function as a channel, and the deterioration of the TFT is accelerated. Sometimes.

Further, when the size of the TFT is large, TF
The self-heating of T becomes large, which may lead to a change or deterioration of the threshold value.

In a TFT having a large channel width, a variation in crystallinity occurs in the device.
The threshold voltage varies for each FT. Therefore, it is inevitable that the characteristics of the buffer constituted by a plurality of TFTs also vary. Therefore,
There is a buffer having a variation in characteristics for each source signal line, and these variations in characteristics directly lead to variations in voltage applied to the pixel matrix circuit.

When driving the liquid crystal with an applied voltage of 5 V,
When performing eight gradation display, the voltage width per gradation is 5
V / 8 gradation = 625 mV / gradation.
313 mV for gradation display, 156 mV for 32 gradation display, 7 for 64 gradation display.
When performing 8 mV, 128 gradation display, 39 mV, 25
When performing 6-gradation display, the voltage is 20 mV.

When an active matrix type liquid crystal display device is applied to a three-plate type projector, it is necessary to display 256 gradations in order to realize full color display. Therefore, as described above, if the applied voltage varies for each source signal line, display unevenness of the entire display device appears, and good display cannot be performed.

Also in the gate signal line side driving circuit, a scanning signal is sequentially supplied to the gate signal line (scanning line) based on a timing signal from the shift register. The gate signal line side driving circuit must drive all pixel TFTs for one line connected to one scanning line, and the load capacitance connected to one scanning line is large.
Therefore, in the gate signal line side driving circuit, it may be necessary to eliminate the "dullness" by passing the timing signal from the shift register through a buffer circuit or the like. Also in this case, a buffer having a large current capacity is required, and the above-described problem occurs. In particular,
The buffer of the gate signal line must drive the TFTs of all connected pixel matrix circuits for one line, and the variation in the characteristics significantly causes image unevenness. This is one of the biggest problems when a display device with high definition and high resolution is desired.

[0031]

[Means for Solving the Problems]

Therefore, the present invention has been made to solve the above-described problem, and provides a buffer capable of canceling the difference between the characteristics of individual TFTs even when there is a difference between the characteristics. Is what you do. Further, the present invention provides a driving circuit of an active matrix type semiconductor display device using a buffer having a small variation. It is still another object of the present invention to provide a semiconductor display device using the driving circuit of the present invention, which can obtain a good image with high definition and high resolution without image unevenness.

The structure of the present invention is as described below.

According to one embodiment of the present invention, the gate electrode potential to which a signal is output is common to x input thin film transistors (x is a natural number of 2 or more) to which a signal is input. And a differential circuit including x output-side thin film transistors and a gate electrode potential common to y
A plurality of thin film transistors on the input side (y is a natural number of 2 or more) and y thin film transistors on the output side;
There is provided a thin film transistor circuit having at least a gate electrode of each of the input-side thin film transistors and a current mirror circuit to which a source or a drain of each of the y input-side thin film transistors is connected. This achieves the above object.

Further, according to an embodiment of the present invention, x (where x is a natural number of 2 or more) input-side thin-film transistors having a common gate electrode potential to which a signal is input, and a gate electrode potential to which a signal is output are provided. Are common (n × x) (n is 2
A differential circuit including the above-described natural number thin film transistors on the output side, and y (y is a natural number of 2 or more) input side thin film transistors having the same gate electrode potential and (n ×
a thin-film transistor comprising: y) output-side thin film transistors, at least having a current mirror circuit in which a gate electrode of the y input-side thin film transistors and a source or drain of the y input-side thin film transistors are connected. A circuit is provided. This achieves the above object.

Further, according to an embodiment of the present invention, a pixel matrix circuit, x input thin film transistors (x is a natural number of 2 or more) having a common gate electrode potential to which a signal is input, and a signal output terminal are provided. A differential circuit including x output thin-film transistors having a common gate electrode potential, and y input thin-film transistors (y is a natural number of 2 or more) having a common gate electrode potential, and y outputs And a current mirror circuit including at least a gate electrode of the y input-side thin film transistors and a source or a drain of the y input side thin film transistors. A driving circuit, wherein the pixel matrix circuit and the driving circuit are provided on the same substrate. The semiconductor display device have been made is provided. This achieves the above object.

Further, according to an embodiment of the present invention, a pixel matrix circuit, x input thin film transistors (x is a natural number of 2 or more) having a common gate electrode potential for inputting a signal, and a signal output signal And a differential circuit including (n × x) output thin film transistors having common gate electrode potentials (n is a natural number of 2 or more) and y (y is 2 or more) common gate electrode potentials. A (natural number) input-side thin film transistor and (n × y) output-side thin film transistors, wherein a gate electrode of the y input-side thin film transistors is connected to a source or a drain of the y input-side thin film transistors. Current mirror circuit,
And a driving circuit having at least a thin film transistor circuit using at least a semiconductor display device,
A semiconductor display device is provided in which the pixel matrix circuit and the drive circuit are formed on the same substrate. This achieves the above object.

Here, the present invention will be described with reference to FIG.
FIG. 1 is a diagram showing a circuit configuration of a thin film transistor circuit according to the present invention. A portion A surrounded by a dotted line constitutes a differential circuit, and a portion B surrounded by a dotted line constitutes a current mirror circuit. The differential circuit is connected to a constant current source 100, and the current mirror circuit is connected to a constant voltage source 101.

The differential circuit includes x input-side thin film transistors connected to the input terminal 102 and having a common gate electrode potential, and x output thin film transistors connected to the output terminal 103 and having a common gate electrode potential. (X is a natural number of 2 or more). The sources or drains of the x input-side thin film transistors connected to the input terminal 102 and having the same gate electrode potential are connected to be at a common potential. The sources or drains of the x output-side thin film transistors connected to the output terminal 103 and having the same gate electrode potential are connected to have a common potential. The gate electrodes of the x output thin film transistors are connected to their sources or drains. That is, in other words, the differential circuit of the present invention is configured by dividing each of the output side and input side thin film transistors constituting the conventional differential circuit into x thin film transistors and connecting them in parallel. .

On the other hand, the current mirror circuit comprises y input-side thin film transistors connected to the source or drain of x thin film transistors on the input side of the differential circuit and having a common gate electrode potential, and the output side of the differential circuit. Have a common gate electrode potential connected to the source or drain of the x thin film transistors, and have y common output thin film transistors (y is a natural number of 2 or more). The gate electrodes of the y input-side thin film transistors and the y output thin film transistors have the same potential. These gate electrodes are connected to the sources or drains of the y input side thin film transistors. In other words, the current mirror circuit of the present invention is also configured by dividing the thin film transistors constituting the conventional current mirror circuit into y or z thin film transistors and connecting them in parallel.

The polarities of the thin film transistors used for the differential circuit and the current mirror circuit are opposite to each other. In FIG. 1, a P-channel thin film transistor is used in the differential circuit, and an N-channel thin film transistor is used in the current mirror circuit. This P
The polarity of the type and the N type may be reversed. However, it does not operate with the same polarity.

In the thin film transistor circuit of the present invention shown in FIG. 1, a TFT having a large size (channel width) is used.
Instead, a plurality of small-sized TFTs are connected in parallel and used. By doing so, it is possible to reduce variations in the characteristics of the thin film transistor while securing a sufficient current capacity.

[0043]

【Example】

(Example 1)

FIG. 2 shows an embodiment of the present invention. FIG. 2 shows a case where the configuration of the present invention is used for an analog buffer of a source signal line side driving circuit of an active matrix semiconductor display device. Note that the analog buffer of this embodiment is a case where x = y = 3.

The analog buffer shown in FIG. 2 includes a differential amplifier of a circuit A surrounded by a dotted line and a circuit B surrounded by a dotted line.
And a current mirror circuit. Note that the channel width of the six P-channel TFTs constituting the differential amplifier was 30 μm. The channel width of the N-channel TFT forming the current mirror circuit was 30 μm.

In the present embodiment, the number of TFTs forming the differential circuit is the same as the number of TFTs forming the current mirror circuit, but it is not always necessary to make the same number. The channel width of each TFT is 30 μm, but may be 100 μm or less (preferably 90 μm or less).

Hereinafter, an example of a method of manufacturing an active matrix type liquid crystal display device as an active matrix type semiconductor display device having the analog buffer of the present embodiment in a drive circuit will be described. Note that the manufacturing method described below is merely one method for realizing the present invention, and an active matrix liquid crystal display device including the thin film transistor circuit of the present invention can be realized by another manufacturing method.

Here, an example in which a plurality of TFTs are formed on a substrate having an insulating surface and a pixel matrix circuit, a driving circuit, a logic circuit, and the like are monolithically constructed is shown in FIG.
6 to FIG. In this embodiment, one pixel of the pixel matrix circuit and a CMOS circuit which is a basic circuit of another circuit (a driving circuit having an analog buffer of the present invention, a logic circuit, or the like) are simultaneously formed on the same substrate. It shows how it works. In this embodiment, the P-channel TFT and the N
The manufacturing process will be described for the case where each of the channel type TFTs has one gate electrode. A CMOS circuit using a TFT having a plurality of gate electrodes, such as a double gate type or a triple gate type, is similarly described. Can be made.

Referring to FIG. First, a quartz substrate 301 is prepared as a substrate having an insulating surface. A silicon substrate on which a thermal oxide film is formed can be used instead of the quartz substrate. Also, once an amorphous silicon film is formed on a quartz substrate,
A method of completely thermally oxidizing it to form an insulating film may be used. Further, a quartz substrate or a ceramic substrate on which a silicon nitride film is formed as an insulating film may be used.

An amorphous silicon film 302 is formed on a substrate 301 by a low pressure CVD method, a plasma CVD method, or a sputtering method. The amorphous silicon film 302 is adjusted so that the final film thickness (thickness in consideration of film reduction after thermal oxidation) is 10 to 100 nm (preferably 30 to 60 nm). In addition,
It is important to thoroughly control the impurity concentration in the film when forming the film.

Although the amorphous silicon film 302 is formed on the substrate 301 in this embodiment, another semiconductor thin film may be used instead of the amorphous silicon film. For example, Si _x Ge
It is also possible to use a compound of silicon and germanium represented by _1-x (0 <X <1).

In this embodiment, in the amorphous silicon film 302, C (carbon) and N, which are impurities that inhibit crystallization, are used.
The concentration of (nitrogen) was 5 × 10 ¹⁸ atoms / cm
Less than ³ (typically 5 × 10 ¹⁷ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less);
O (oxygen) is controlled to be less than 1.5 × 10 ¹⁹ atoms / cm ³ (typically 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 5 × 10 ¹⁷ atoms / cm ³ or less). This is because, if each impurity is present at a higher concentration, it will have an adverse effect on the subsequent crystallization and cause a deterioration in the film quality after the crystallization. In this specification, the above-mentioned impurity element concentration in a film is defined by a minimum value in a measurement result of SIMS (Secondary Mass Ion Analysis).

In order to obtain the above configuration, it is desirable that the reduced pressure thermal CVD furnace used in this embodiment is periodically dry-cleaned to clean the film forming chamber. Dry cleaning is performed in a furnace heated to about 200 to 400 ° C.
A film formation chamber may be cleaned by flowing ClF ₃ (chlorine fluoride) gas at a flow rate of 00 to 300 sccm and using fluorine generated by thermal decomposition.

According to the knowledge of the present applicant, the furnace temperature 3
00 ° C. and the flow rate of ClF ₃ (chlorine fluoride) gas is 30
When the thickness is set to 0 sccm, it is possible to completely remove the attached matter (mainly composed mainly of silicon) having a thickness of about 2 μm in 4 hours.

The hydrogen concentration in the amorphous silicon film 302 is also a very important parameter, and a film having a good crystallinity can be obtained by keeping the hydrogen content low. for that reason,
The formation of the amorphous silicon film 302 is preferably performed by a low pressure thermal CVD method. Note that the plasma CVD method can be used by optimizing the film formation conditions.

When the amorphous silicon film 302 is formed, TF
It is effective to add an impurity element (a Group 13 element, typically boron, or a Group 15 element, typically phosphorus) for controlling the threshold voltage (Vth) of T. The amount of addition is V when no Vth controlling impurity is added.
It is necessary to determine in consideration of th.

Next, a crystallization step of the amorphous silicon film 302 is performed. As a means for crystallization, a technique described in JP-A-7-130652 is used. Although any of the means of Embodiment 1 and Embodiment 2 of the publication may be used, in this embodiment, the technical contents described in Embodiment 2 of the publication (Japanese Patent Laid-Open No. 8-78329) will be described.
It is preferable to use the method described in Japanese Unexamined Patent Publication (Kokai) No. H11-26095.

The technique described in Japanese Patent Application Laid-Open No. H8-78329 discloses a mask insulating film 3 for selecting a region to which a catalyst element is added.
03 is formed. The mask insulating film 303 has a plurality of openings for adding a catalyst element. The position of the crystal region can be determined by the position of the opening.

Then, a solution containing nickel (Ni) as a catalyst element for promoting crystallization of the amorphous silicon film is applied by spin coating to form a Ni-containing layer 304. In addition, as a catalyst element, in addition to nickel, cobalt (Co), iron (Fe), palladium (Pd), germanium (Ge), platinum (Pt), copper (Cu), and gold (A
u) etc. can be used (FIG. 3A).

In the step of adding the catalyst element, an ion implantation method using a resist mask or a plasma doping method can be used. In this case, the reduction of the occupied area of the addition region and the control of the growth distance of the lateral growth region are facilitated, so that this is an effective technique when configuring a miniaturized circuit.

Next, when the step of adding the catalyst element is completed,
After dehydration for about 2 hours at 500 ° C, an inert atmosphere,
500 to 700 in a hydrogen atmosphere or an oxygen atmosphere
° C (typically 550-650 ° C, preferably 570
(° C.) and heat treatment for 4 to 24 hours to crystallize the amorphous silicon film 302. In this embodiment, heat treatment is performed at 570 ° C. for 14 hours in a nitrogen atmosphere.

At this time, the crystallization of the amorphous silicon film 302 proceeds preferentially from the nuclei generated in the nickel-added regions 305 and 306, and grows substantially parallel to the substrate surface of the substrate 301. Regions 307 and 308 are formed. These crystal regions 307 and 308 are called lateral growth regions. Since individual crystals are aggregated in the lateral growth region in a relatively uniform state, there is an advantage that the overall crystallinity is excellent (FIG. 3B).

When the technique described in the first embodiment of Japanese Patent Application Laid-Open No. Hei 7-130652 is used, a region which can be microscopically called a lateral growth region is formed. However, since nucleation occurs unevenly in the plane, there is a difficulty in controllability of crystal grain boundaries.

When the heat treatment for crystallization is completed, the mask insulating film 903 is removed and patterning is performed to form island-like semiconductor layers (active layers) 309, 310, and 311 composed of the lateral growth regions 307 and 308. (Figure 3
(C)).

Here, reference numeral 309 denotes N constituting a CMOS circuit.
An active layer of a channel type TFT, 310 is an active layer of a P channel type TFT constituting a CMOS circuit, and 311 is an N channel type TFT (pixel TF) constituting a pixel matrix circuit.
T) is an active layer.

After forming the active layers 309, 310 and 311, a gate insulating film 312 made of an insulating film containing silicon is formed thereon (FIG. 3C).

Then, as shown in FIG. 3D, a heat treatment (a catalytic element gettering process) for removing or reducing the catalytic element (nickel) is performed. In this heat treatment, a halogen element is contained in the treatment atmosphere, and the gettering effect of the metal element by the halogen element is used.

In order to sufficiently obtain the gettering effect by the halogen element, it is preferable to perform the above heat treatment at a temperature exceeding 700 ° C. Below this temperature, the decomposition of the halogen compound in the processing atmosphere becomes difficult, and the gettering effect may not be obtained.

Therefore, in this embodiment, this heat treatment is performed
It is carried out at a temperature exceeding 0 ° C., preferably 800 to 1000
° C (typically 950 ° C) and the treatment time is 0.1 to 6
hr, typically 0.5 to 1 hr.

In the present embodiment, in an atmosphere containing hydrogen chloride (HCl) at a concentration of 0.5 to 10% by volume (3% by volume in this embodiment) with respect to an oxygen atmosphere, 9%
An example in which heat treatment is performed at 50 ° C. for 30 minutes will be described. If the HCl concentration is higher than the above concentration, the surface of the active layers 309, 310 and 311 will have irregularities of about the film thickness, which is not preferable.

The compound containing a halogen element is HC
Although the example using 1 gas was shown, as other gas,
Typically, HF, NF ₃ , HBr, Cl ₂ , ClF ₃ ,
One or more compounds selected from compounds containing halogen such as BCl ₂ , F ₂ , and Br ₂ can be used.

In this step, the active layers 309, 31
It is considered that nickel in 0 and 311 is gettered by the action of chlorine, becomes volatile nickel chloride, escapes to the atmosphere and is removed. By this step, the concentration of nickel in the active layers 309, 310, and 311 is reduced to 5 × 10 ¹⁷ atoms / cm ³ or less.

The value of 5 × 10 ¹⁷ atoms / cm ³ is the lower detection limit of SIMS (Mass Secondary Ion Analysis). As a result of analyzing a TFT manufactured by the present applicant, 1 × 1
0 ¹⁸ atoms / cm ³ or less (preferably 5 × 10 ¹⁷ a
(toms / cm ³ or less), the effect of nickel on the TFT characteristics was not confirmed. However, the impurity concentration in this specification is defined by the minimum value of the measurement result of the SIMS analysis.

Further, the active layer 309,
A thermal oxidation reaction proceeds at the interface between the gate insulating film 312 and the gate insulating film 312, and the thickness of the gate insulating film 312 increases by the amount of the thermal oxide film. When the thermal oxide film is formed in this manner, a semiconductor / insulating film interface having very few interface states can be obtained. Further, there is also an effect of preventing formation failure (edge thinning) of a thermal oxide film at an end of the active layer.

It is also effective to perform the catalytic element gettering process after removing the mask insulating film 303 and before patterning the active layer. Further, the gettering process of the catalytic element may be performed after patterning the active layer. Further, any gettering process may be performed in combination.

Note that the catalyst element gettering process can also be performed by using P (phosphorus). The phosphorus gettering process may be combined with the above-described gettering process. Alternatively, only the gettering process using phosphorus may be used.

It is also effective to improve the film quality of the gate insulating film 312 by performing a heat treatment in a nitrogen atmosphere at 950 ° C. for about 1 hour after the heat treatment in the halogen atmosphere.

The active layer 309,
In 310 and 311, the halogen element used for the gettering treatment was 1 × 10 ¹⁵ atoms / cm ³ to 1
It has also been confirmed that it remains at a concentration of × 10 ²⁰ atoms / cm ³ . At this time, the active layers 309, 310,
And 311 and the thermal oxide film formed by the heat treatment indicate that the halogen element is distributed at a high concentration.
Confirmed by IMS analysis.

As a result of SIMS analysis of other elements, C (carbon), N (nitrogen), O (oxygen) and S (sulfur), which are typical impurities, are all 5 × 10 ¹⁸ a
less than toms / cm ³ (typically 1 × 10 ¹⁸ atoms
s / cm ³ or less).

The lateral growth region of the active layer thus obtained has a unique crystal structure composed of a rod-like or flat rod-like aggregate. The features of this unique crystal structure will be described later.

Next, reference is made to FIG. First, a metal film (not shown) containing aluminum as a main component is formed, and the gate electrode prototypes 313, 314, and 315 are formed by patterning. In this embodiment, an aluminum film containing 2 wt% scandium is used (FIG. 4).
(A)).

Note that a polycrystalline silicon film may be used as a gate electrode instead of the aluminum film containing 2 wt% scandium.

Next, the porous anodic oxide films 316, 317, and 318, the nonporous anodic oxide films 319, 320, and 321 and the gate electrodes 322 and 323 are formed by the technique described in Japanese Patent Application Laid-Open No. 7-135318. And 324 (FIG. 4B).

When the state shown in FIG. 4B is obtained,
Next, gate insulating film 312 is etched using gate electrodes 322, 323, and 324 and porous anodic oxide films 316, 317, and 318 as masks. Then, the porous anodic oxide films 316, 317, and 318 are removed to obtain the state shown in FIG. Note that in FIG. 4C, reference numerals 325, 326, and 327 denote the gate insulating films after processing.

Next, a step of adding an impurity element imparting one conductivity is performed. As an impurity element, P (phosphorus) or As (arsenic) may be used for an N-channel type, and B (boron) or Ga (gallium) may be used for a P-type.

In this embodiment, the addition of impurities for forming N-channel and P-channel TFTs is performed in two separate steps.

First, an impurity is added for forming an N-channel type TFT. First, the first impurity addition (in this embodiment, P (phosphorus) is used) is performed at a high accelerating voltage 80.
This is performed at about keV to form an n ^- region. This n ⁻ region has a P ion concentration of 1 × 10 ¹⁸ atoms / cm ³ to 1
Adjust so as to be × 10 ¹⁹ atoms / cm ³ .

Further, the second impurity addition is performed at a low acceleration voltage of about 10 keV to form an n ⁺ region. At this time, since the acceleration voltage is low, the gate insulating film functions as a mask. The n ⁺ region has a sheet resistance of 500
It is adjusted so as to be Ω or less (preferably 300 Ω or less).

Through the above steps, a source region 328, a drain region 329, a low-concentration impurity region 330, and a channel formation region 331 of an N-channel TFT constituting a CMOS circuit are formed. Further, the source region 332 and the drain region 33 of the N-channel TFT constituting the pixel TFT
3, low concentration impurity region 334, channel formation region 335
Is determined (FIG. 4D).

In the state shown in FIG.
The active layer of the P-channel TFT forming the circuit has the same configuration as the active layer of the N-channel TFT.

Next, as shown in FIG. 5A, a resist mask 336 is provided so as to cover the N-channel TFT, and an impurity ion imparting P-type (boron is used in this embodiment) is added.

This step is also performed twice as in the case of the above-described impurity doping step. However, since it is necessary to invert the N-channel type to the P-channel type, the concentration is about several times the above-mentioned P ion addition concentration. B (boron) ion is added.

Thus, the source region 337, the drain region 338 of the P-channel type TFT constituting the CMOS circuit,
A low-concentration impurity region 339 and a channel formation region 340 are formed (FIG. 5A).

When the active layer is completed as described above, activation of impurity ions is performed by a combination of furnace annealing, laser annealing, lamp annealing and the like. At the same time, the damage of the active layer in the addition step is also repaired.

Next, a stacked film of a silicon oxide film and a silicon nitride film is formed as an interlayer insulating film 341, and a contact hole is formed. Then, source electrodes 342, 343, and 34 are formed.
4. Form drain electrodes 345 and 346 to form FIG.
The state shown in is obtained. Note that an organic resin film can also be used as the interlayer insulating film 341.

When the state shown in FIG. 5B is obtained, the first interlayer insulating film 347 made of an organic resin film is
It is formed to a thickness of μm. As the organic resin film, polyimide, acrylic, polyimide amide or the like is used. The advantages of the organic resin film are that the film formation method is simple, the film thickness can be easily increased, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. .
Note that an organic resin film other than those described above can be used.

Next, a black matrix 348 made of a light-shielding film is formed on the first interlayer insulating film 347 for 100 nm.
m. Although a titanium film is used as the black matrix 348 in this embodiment, a resin film or the like containing a black pigment may be used.

Note that. In the case of using a titanium film for the black matrix 348, part of a wiring in a driver circuit and other peripheral circuit portions can be formed using titanium. This titanium wiring is used when the black matrix 348 is formed.
Can be formed simultaneously.

After forming the black matrix 348,
As the second interlayer insulating film 349, any one of a silicon oxide film, a silicon nitride film, and an organic resin film or a stacked film thereof is formed to a thickness of 0.1 to 0.3 μm. Then, contact holes are formed in the interlayer insulating film 347 and the interlayer insulating film 349, and the pixel electrode 350 is formed to a thickness of 120 nm. According to the configuration of the present embodiment, the black matrix 34
A storage capacitor is formed in a region where the pixel electrode 8 and the pixel electrode 350 overlap (FIG. 5C). Note that since this embodiment is an example of a transmission type active matrix liquid crystal display device, a transparent conductive film such as ITO is used as a conductive film forming the pixel electrode 350.

Next, the entire substrate is heated in a hydrogen atmosphere at 350 ° C. for 1 to 2 hours, and hydrogenation of the entire device is performed, whereby dangling bonds (unpaired bonds) in the film (especially in the active layer) are formed.
To compensate. Through the above steps, a CMOS circuit and a pixel matrix circuit can be manufactured over the same substrate.

Next, a process of manufacturing an active matrix type liquid crystal display device based on the active matrix substrate manufactured by the above process will be described with reference to FIG.

An orientation film 351 is formed on the active matrix substrate in the state shown in FIG. In this embodiment, polyimide is used for the alignment film 351. Next, a counter substrate is prepared. The opposing substrate is a glass substrate 352, a transparent conductive film 3
53 and an alignment film 354.

In this embodiment, a polyimide film in which liquid crystal molecules are aligned parallel to the substrate is used as the alignment film. After the alignment film was formed, a rubbing treatment was performed so that the liquid crystal molecules were aligned in parallel with a certain pretilt angle.

Next, the active matrix substrate and the counter substrate having undergone the above-described steps are subjected to a well-known cell assembling step.
It is bonded via a sealing material or a spacer (both not shown). Thereafter, a liquid crystal material 355 is injected between the two substrates, and completely sealed with a sealing agent (not shown). Thus, a transmission type active matrix liquid crystal display device as shown in FIG. 6 is completed.

FIG. 7 is a perspective view of a completed active matrix type liquid crystal display device. 701 is an active matrix substrate, 702 is a pixel matrix circuit,
703 is a source signal line side driving circuit, 704 is a gate signal line side driving circuit, 705 is another peripheral circuit, and 706 is a counter substrate. As shown in FIG. 7, in the active matrix type liquid crystal display device of the present embodiment, only the end face on which the FPC is mounted is exposed to the outside, and the remaining three end faces are aligned.

In this embodiment, the liquid crystal display device is TN
Display is performed in (twisted nematic) mode. Therefore, a pair of polarizing plates (not shown) are arranged so as to sandwich the liquid crystal panel in a crossed Nicols state (a state in which the pair of polarizing plates makes their polarization axes orthogonal to each other).

Therefore, in this embodiment, it is understood that display is performed in a so-called normally white mode, in which white display is performed when no voltage is applied to the liquid crystal display device.

According to the manufacturing method described above, in the active matrix liquid crystal display device of this embodiment, it is understood that the driving circuit, other peripheral devices, and the pixels can be integrally formed on an insulating substrate such as a quartz substrate or a glass substrate. Is done.

(Example 2)

FIG. 8 shows another embodiment of the present invention. FIG.
Shows a case where the configuration of the present invention is used for an analog buffer of a source signal line side driving circuit of an active matrix semiconductor display device. In the present embodiment, the number of thin film transistors on the output side of the differential circuit and the current mirror circuit is increased to three times that of the first embodiment. In other words,
The circuit on the output side of the differential circuit and the current mirror circuit is tripled. By doing so, the current capability of the analog buffer configured is increased.

In the present embodiment, the channel width of the six P-channel TFTs constituting the differential amplifier was 30 μm. Also, an N-channel type TF constituting a current mirror circuit
The channel width of T was 30 μm. In this embodiment, the channel width of each TFT is 30 μm, but may be 100 μm or less (preferably 90 μm or less).

The operation of the analog buffer of this embodiment will be described. When the potential at the input terminal decreases, most of the current of the constant current source flows to the P-channel TFT on the input side of the differential circuit, and further flows to the input of the current mirror circuit. Since the number of TFTs on the output side of the current mirror circuit is three times as large as that on the input side, three times the current of the constant current source can be drawn from the output terminal and connected to the output terminal. The source signal line can be driven at high speed. When the potentials at the input terminal and the output terminal become substantially equal, the current of the constant current source is divided between the output TFT and the input TFT. In this case, the ratio of the number of TFTs of the differential circuit is 1: 3 on the output side and the input side, and the TFT of the current mirror circuit is
Is 1: 3 between the output side and the input side, the potential of the input terminal and the potential of the output terminal are not affected by the number of TFTs.

In this embodiment, the number of TFTs in the differential circuit and the current mirror circuit is three times that in the first embodiment. However, the present invention is not limited to this. That is, the number of output-side thin film transistors in the differential circuit is n times (that is, (n × x)), and the number of output side thin film transistors in the current mirror circuit is n times (that is, (n × y)). To).

(Example 3)

The active matrix type liquid crystal display device of the present invention described in Embodiments 1 and 2 can sufficiently cope with a high definition and high resolution active matrix type liquid crystal display device.
The number of pixels is determined by the future ATV (Advanced T
V) is enormous enough to support. Therefore, the present invention can be applied to an active matrix type liquid crystal display device having a resolution of XGA or more, for example, 1920 × 1280 resolution.

(Example 4)

The active matrix type liquid crystal display device described in the first to third embodiments can be used for both a transmission type active matrix type liquid crystal display device and a reflection type active matrix type liquid crystal display device. Alternatively, an antiferroelectric liquid crystal having no threshold can be used as a liquid crystal material. Further, it is possible to cope with a case where a ferroelectric liquid crystal is used as a liquid crystal material and a memory effect of the ferroelectric liquid crystal is erased by a special alignment film or the like.

For example, in 1998, SID, "Characteristics an
d Driving Scheme of Polymer-Stabilized Monostable
FLCD Exhibiting Fast Response Time and High Contra
st Ratio with Gray-Scale Capability "by H. Furue e
t al., 1997, SID DIGEST, 841, "A Full-Color Thres
holdless Antiferroelectric LCD Exhibiting WideView
ing Angle with Fast Response Time "by T. Yoshida e
or the liquid crystal materials disclosed in US Pat. No. 5,594,569.

In particular, a thresholdless antiferroelectric liquid crystal material,
Among the thresholdless antiferroelectric mixed liquid crystal which is a mixed liquid crystal material of a ferroelectric liquid crystal material and an antiferroelectric liquid crystal material, a drive voltage of about ± 2.5 V has been found. . When such a low-voltage driven thresholdless antiferroelectric mixed liquid crystal is used, the power supply voltage of the image signal sampling circuit can be suppressed to about 5 V to 8 V, and the LDD region (low density TFT with small width of impurity region)
(For example, 0 nm to 500 nm or 0 nm to 200 n
This is also effective when using m).

FIG. 13 is a graph showing the characteristics of the light transmittance with respect to the applied voltage of the thresholdless antiferroelectric mixed liquid crystal.
Shown in Note that the transmission axis of the polarizing plate on the incident side of the liquid crystal display device is set substantially parallel to the normal direction of the smectic layer of the thresholdless antiferroelectric mixed liquid crystal that substantially matches the rubbing direction of the liquid crystal display device. . Further, the transmission axis of the exit-side polarizing plate is set substantially at right angles (crossed Nicols) to the transmission axis of the incidence-side polarizing plate. As described above, it can be seen that when the thresholdless antiferroelectric mixed liquid crystal is used, it is possible to perform a gradation display showing an applied voltage-transmittance characteristic as shown in FIG.

In general, a thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitance is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization. In addition, by making the driving method of the liquid crystal display device line-sequential driving, a period (pixel feed period) of writing a gray scale voltage to a pixel can be lengthened, and even if the storage capacity is small, it can be compensated.

Since low-voltage driving is realized by using a thresholdless antiferroelectric liquid crystal, low power consumption of the liquid crystal display device is realized.

In the first to third embodiments, the case where liquid crystal is used as a display medium has been described. However, a semiconductor display device having any other display medium whose optical characteristics can be modulated in response to an applied voltage. May be used. For example, an electroluminescent element or an electrochromic element may be used as a display medium.

The TF used in Examples 1 to 3 was used.
T may be a top gate type or an inverted stagger type.

(Example 5)

The semiconductor display devices of Embodiments 1 to 4 have various uses. EXAMPLE 1 In this example, a semiconductor device incorporating an active matrix semiconductor display device using the thin film transistor circuit of the present invention will be described.

Examples of such a semiconductor device include a video camera, a still camera, a projector, a head-mounted display, a car navigation, a personal computer, and a portable information terminal (mobile computer, mobile phone, etc.). One example is shown in FIG.

FIG. 9A shows a portable telephone, and a main body 90.
1, an audio output unit 902, an audio input unit 903, a semiconductor display device 904, an operation switch 905, and an antenna 906.

FIG. 9B shows a video camera,
07, a semiconductor display device 908, an audio input unit 909, an operation switch 910, a battery 911, and an image receiving unit 912.

FIG. 9C shows a mobile computer, which comprises a main body 913, a camera section 914, an image receiving section 915, operation switches 916, and a semiconductor display device 917.

FIG. 9D shows a head-mounted display, which comprises a main body 918, a semiconductor display device 919, and a band section 920.

FIG. 9E shows a rear type projector.
921 is a main body, 922 is a light source, 923 is a semiconductor display device, 924 is a polarizing beam splitter, 925 and 92
6 is a reflector, and 927 is a screen. In addition,
It is preferable that the rear type projector can change the angle of the screen while keeping the main body fixed, depending on the viewing position of the viewer. Note that by using three semiconductor display devices 923 (corresponding to R, G, and B light, respectively), a rear projector with higher resolution and higher definition can be realized.

FIG. 9F shows a front type projector, which includes a main body 928, a light source 929, a semiconductor display device 930,
It comprises an optical system 931 and a screen 932. In addition,
By using three semiconductor display devices 930 (corresponding to R, G, and B lights, respectively), it is possible to realize a front-type projector with higher resolution and higher definition.

[0135]

【The invention's effect】

According to the present invention, it is possible to minimize the variation in the characteristics of the analog buffer, which is one of the major causes of image unevenness in an active matrix type semiconductor display device, and to provide a high image quality active matrix type semiconductor display device. Is realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing a thin film transistor circuit of the present invention.

FIG. 2 is a diagram showing one embodiment of a thin film transistor circuit of the present invention.

FIG. 3 is a diagram illustrating an example of a manufacturing process of an active matrix liquid crystal display device having a thin film transistor circuit of the present invention.

FIG. 4 is a diagram illustrating an example of a manufacturing process of an active matrix liquid crystal display device having a thin film transistor circuit of the present invention.

FIG. 5 is a diagram illustrating an example of a manufacturing process of an active matrix liquid crystal display device having a thin film transistor circuit of the present invention.

FIG. 6 is a diagram illustrating an example of a manufacturing process of an active matrix liquid crystal display device having a thin film transistor circuit of the present invention.

FIG. 7 is a perspective view of an active matrix type liquid crystal display device having the thin film transistor circuit of the present invention.

FIG. 8 is a diagram showing one embodiment of a thin film transistor circuit of the present invention.

FIG. 9 is a diagram showing an example of a semiconductor device having a semiconductor display device having a thin film transistor circuit of the present invention.

FIG. 10 is a schematic configuration diagram of an active matrix liquid crystal display device.

FIG. 11 is a diagram illustrating an example of a source signal line side driving circuit of an active matrix liquid crystal display device.

FIG. 12 is a circuit diagram of a conventional analog buffer.

FIG. 13 is a graph showing an applied voltage-transmittance characteristic of a thresholdless antiferroelectric mixed liquid crystal.

[Explanation of symbols]

 Reference Signs List 100 constant current source 101 constant voltage source 102 input terminal 103 output terminal A differential circuit B current mirror circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 614

Claims (4)

[Claims] An x-side (x is a natural number of 2 or more) input-side thin film transistors having a common gate electrode potential for inputting a signal and an x-side output thin-film transistor having a common gate electrode potential for outputting a signal. Y (y is a natural number of 2 or more) having the same gate electrode potential as the differential circuit including the thin film transistor
A current mirror circuit including a thin film transistor on the input side and a thin film transistor on the y output side, wherein a gate electrode of the thin film transistor on the y input side is connected to a source or a drain of the thin film transistor on the y input side; And a thin film transistor circuit comprising at least: 2. An x-side (x is a natural number of 2 or more) input side thin film transistors having a common gate electrode potential to which a signal is input, and a common gate electrode potential (n × n) having a signal output potential.
a differential circuit including x) (n is a natural number of 2 or more) output-side thin film transistors, and y (y is a natural number of 2 or more) having a common gate electrode potential
, And (n × y) output-side thin film transistors, wherein the gate electrodes of the y input-side thin film transistors are connected to the source or drain of the y input-side thin film transistors. And a current mirror circuit. 3. A pixel matrix circuit and x gate electrode potentials to which signals are input (x is 2
A differential circuit including the input-side thin film transistors of the above (natural numbers) and x output-side thin film transistors with a common gate electrode potential for outputting a signal, and y (y is 2) common gate electrode potentials The above-mentioned (natural number) input-side thin film transistors and y output-side thin film transistors are included, and the gate electrodes of the y input-side thin film transistors are connected to the sources or drains of the y input-side thin film transistors. A semiconductor display device comprising: a current mirror circuit; and a drive circuit having at least a thin film transistor circuit using the same, wherein the pixel matrix circuit and the drive circuit are formed over the same substrate. 4. A pixel matrix circuit and x gate electrode potentials to which signals are input (x is 2
A differential circuit including (n is a natural number) an input-side thin film transistor, and (n × x) (n is a natural number of 2 or more) output-side thin film transistors having a common gate electrode potential for outputting a signal; Y (y is a natural number of 2 or more) input-side thin film transistors having a common electrode potential and (n ×
a) a current mirror circuit including at least y) output side thin film transistors, wherein a gate electrode of the y number of input side thin film transistors and a source or drain of the y number of input side thin film transistors are connected; A semiconductor display device comprising: a driving circuit having at least a thin film transistor circuit, wherein the pixel matrix circuit and the driving circuit are formed over the same substrate.