JP2000003162A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device which suppresses display defects, such as crosstalks and writing deficiency. SOLUTION: A timing controller 12 outputs a start pulse and clock signal and scanning lines are successively selected in a scanning drive circuit section 4. This timing controller 12 outputs the start pulse and the clock signal of an anti-phase, successively shifts shift registers and outputs a gate signal to an analog switch section. The analog switch section writes data in data lines in accordance with the gate signal outputted from the shift register section and the data of a digital/analog converter 13. If the output pulse is bold, the phase of the clock signal of the anti-phase with respect to the clock signal is shifted forward and the pulse width is fine, by which the crosstalks are prevented. When the output pulse is fine, the clock signal is shifted backward and the pulse width is increased, by which the display defect by the writing inconsistency is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display having a liquid crystal matrix.

[0002]

2. Description of the Related Art Conventionally, as this type of liquid crystal display device,
For example, a drive circuit integrated type liquid crystal display device in which a drive circuit is formed integrally with a liquid crystal panel is known.

[0003] The liquid crystal panel has a plurality of scanning lines,
A plurality of data lines are made orthogonal to each other, and a thin film transistor as a switching element is disposed at an intersection of the scanning line and the data line, and a pixel is controlled by the thin film transistor.

The driving circuit is constituted by a CMOS circuit having an n-type thin film transistor and a p-type thin film transistor. The CMOS circuit drives a shift register to output an output pulse from the shift register. The line is supplied to control the thin film transistor.

However, the characteristics of the n-type thin film transistor and the p-type thin film transistor of the driving circuit vary, and the circuit threshold varies depending on the panel. If the circuit threshold varies, the output pulse width of the shift register becomes wider than the design value. It becomes thin or thin.

[0006] When the output pulse of the shift register becomes thicker, the output pulse overlaps with the output pulse output at the preceding and following timings, and this overlapping timing is generated. The timing data is also written to the data lines. This causes a so-called crosstalk in which the display of the pixel connected to the data line becomes a display in which the preceding and succeeding data are partially written.

On the other hand, when the output pulse of the shift register becomes narrower, the time for writing data to the data line becomes shorter, and the display of the pixel connected to the data line becomes a display in which data cannot be written to a desired potential. Will happen.

[0008]

As described above, in the conventional liquid crystal display device, the characteristics of the n-type thin film transistor and the p-type thin film transistor of the driving circuit vary.
There is a problem that the output pulse width of the shift register becomes thicker or thinner than the designed value, which causes display defects such as crosstalk and insufficient writing.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a liquid crystal display device that suppresses display defects such as crosstalk and insufficient writing.

[0010]

According to the present invention, there are provided a plurality of scanning lines, a plurality of data lines intersecting the scanning lines, and a switching element provided at an intersection of the scanning lines and the data lines. A liquid crystal display device comprising: a liquid crystal matrix having: a scanning line driving circuit for sequentially selecting the scanning lines; a data line driving circuit for writing data to the data lines; and a timing controller for outputting a clock signal. The line drive circuit has a shift register that sequentially transfers shift pulses in synchronization with the clock signal and outputs the shift pulses in parallel. The clock signals are signals having opposite phases, and the phases of the signals having opposite phases are relatively shifted. And the pulse width of the output pulse of the shift register is controlled.

[0011] The output pulse width of the shift register is controlled by relatively shifting the phases of the pair of clock signals that are opposite in phase to each other. On the other hand, display defects due to insufficient writing due to thinning are suppressed.

The data line driving circuit is a CMOS circuit.

Furthermore, the signal of the opposite phase shifts the phase in accordance with the phase difference of the wiring delay, and makes the output pulse width of the shift register a desired width.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the liquid crystal display device of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the liquid crystal display device 1 includes a liquid crystal panel 2, and the liquid crystal panel 2 has a liquid crystal display matrix 3 as a liquid crystal matrix. The liquid crystal display matrix 3 is controlled by a plurality of scanning lines (not shown), data lines orthogonal to the scanning lines, thin film transistors as switching elements located at intersections of these scanning lines and data lines, and the thin film transistors. Pixels arranged in a matrix of 800 × 600 × RGB. Further, the liquid crystal panel 2 is formed with a scan line drive circuit section 4 and a data line drive circuit 5 as a CMOS scan line drive circuit having an n-channel thin film transistor and a p-channel thin film transistor. Has a shift register section 6 and an analog switch section 7, the scanning line drive circuit section 4 is connected to the scanning lines of the liquid crystal display matrix 3, and the analog switch section 7 is connected to the data lines of the liquid crystal display matrix 3, respectively. I have.

Reference numeral 11 denotes a personal computer (P
In C), the personal computer 11 outputs a PC signal and is connected to the timing controller 12. The timing controller 12 outputs clock signals (CLK, / CLK) and start pulses (ST
H), and is connected to the shift register unit 6, outputs a clock signal (YCLK) and a start pulse (STV), is connected to the scanning line driving circuit unit 4, and outputs a 6-bit RGB data signal (DATA). The output is connected to a digital / analog (D / A) converter 13, which is connected to the analog switch 7.

As shown in FIG. 2, the shift register section 6 has a number of shift registers 21 corresponding to the number of data lines, and these shift registers 21 are constituted by clocked inverters 22 to 27. The output pulses a and b are output from the latch circuit, and the output pulse b is output from the shift register 21.

Next, the operation of the liquid crystal display device of the above embodiment will be described.

First, from the personal computer 11 to the PC
When the signal is output, the timing controller 12 outputs the start pulse (STV) and the clock signal (YCL).
K), and the scanning line driving circuit unit 4 sequentially shifts and selects scanning lines based on the start pulse (STV) and the clock signal (YCLK).

The timing controller 12 outputs a start pulse (STH) and a clock signal (CLK, /
CLK), and sequentially shifts the shift register 21 of the shift register section 6 in synchronization with the start pulse (STH) and clock signals (CLK, / CLK), and outputs a gate signal to the analog switch section 7.

On the other hand, the digital data (DATA) output from the timing controller 12 is converted into analog data (DATA) by the digital / analog converter 13 and output to the analog switch unit 7.

Then, the analog switch section 7 receives the gate signal output from the shift register section 6 and the digital /
Data is written to a data line based on the data (DATA) of the analog converter 13.

Here, the clock signals (CLK, / CL)
The output timing of K) will be described with reference to FIGS.

First, the scanning line driving circuit unit 4 having a CMOS configuration
When clock signals (CLK, / CLK) are simply input in opposite phases due to variations in the characteristics of the n-channel thin film transistor and the p-channel thin film transistor of the data line driving circuit 5, as in the comparative example shown in FIG. The output pulse b of 21 becomes thicker or thinner.

Therefore, when the output pulse b is thicker than the set value, as shown in FIG. 3, a clock signal (/ CLK) having a phase opposite to a clock signal (CLK) having a certain phase.
Is shifted before Xns. As a result, the output pulse b of the shift register 21 is about Xns
By narrowing the pulse width and narrowing the output pulse b to a desired pulse width, it was possible to avoid display failure of crosstalk.

When the output pulse b is thinner than the set value, as shown in FIG.
LK), the phase of the clock signal (/ CLK) having the opposite phase is shifted by Xns. This allows the shift register
The output pulse b of No. 21 has a pulse width of about Xns wider than that before shifting, and by making the output pulse b wider to a desired pulse width, display defects due to indeterminate writing can be avoided.

In any case, the time for shifting the phase of the clock signal (CLK) and the phase of the clock signal (/ CLK) is shifted based on, for example, the phase difference of the wiring delay in the liquid crystal panel 2. The width of the output pulse of the shift register 21 may be adjusted to an optimum value.

[0028]

According to the present invention, the output pulse width of the shift register is controlled by relatively shifting the phases of the paired signals of opposite phases of the clock signal, and the output pulse width of the shift register is increased. It is possible to suppress the occurrence of crosstalk and display defects due to insufficient writing due to the narrowing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a liquid document display device of the present invention.

FIG. 2 is a block diagram showing a shift register unit according to the first embodiment;

FIG. 3 is a timing chart showing a clock signal when the output pulse is made thinner;

FIG. 4 is a timing chart showing a clock signal when the output pulse is widened;

FIG. 5 is a timing chart showing clock signals of the same simple phase as those in the first embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 3 Liquid crystal display matrix as a liquid crystal matrix 4 Scanning line drive circuit part as a scan line drive circuit 5 Data line drive circuit 12 Timing controller 21 Shift register

Claims (3)

[Claims] A liquid crystal matrix having a plurality of scanning lines, a plurality of data lines provided to intersect the scanning lines, a switching element provided at an intersection of the scanning lines and the data lines, and A scanning line driving circuit for sequentially selecting lines, a data line driving circuit for writing data to the data lines,
A liquid crystal display device including a timing controller that outputs a clock signal, wherein the data line drive circuit includes a shift register that sequentially transfers shift pulses in synchronization with the clock signal and outputs the shift pulses in parallel. A liquid crystal display device comprising: signals having phases opposite to each other, wherein a phase of the signals having phases opposite to each other is relatively shifted to control a pulse width of an output pulse of the shift register. 2. The liquid crystal display device according to claim 1, wherein the data line drive circuit is a CMOS circuit. 3. The liquid crystal display device according to claim 1, wherein the phase of the signal having the opposite phase is shifted in accordance with the phase difference of the wiring delay.