ITTO930428A1 - Sistema a multiprocessore - Google Patents

Sistema a multiprocessore

Info

Publication number
ITTO930428A1
ITTO930428A1 IT000428A ITTO930428A ITTO930428A1 IT TO930428 A1 ITTO930428 A1 IT TO930428A1 IT 000428 A IT000428 A IT 000428A IT TO930428 A ITTO930428 A IT TO930428A IT TO930428 A1 ITTO930428 A1 IT TO930428A1
Authority
IT
Italy
Prior art keywords
multiprocessor system
multiprocessor
Prior art date
Application number
IT000428A
Other languages
English (en)
Inventor
Bruno Conterno
Mauro Gismondi
Vildo Luperini
Fernando Pesce
Original Assignee
Finmeccanica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Finmeccanica Spa filed Critical Finmeccanica Spa
Priority to ITTO930428A priority Critical patent/IT1260848B/it
Publication of ITTO930428A0 publication Critical patent/ITTO930428A0/it
Priority to DE69424221T priority patent/DE69424221D1/de
Priority to EP94108884A priority patent/EP0628917B1/en
Priority to US08/258,759 priority patent/US5586258A/en
Publication of ITTO930428A1 publication Critical patent/ITTO930428A1/it
Application granted granted Critical
Publication of IT1260848B publication Critical patent/IT1260848B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Multi Processors (AREA)
ITTO930428A 1993-06-11 1993-06-11 Sistema a multiprocessore IT1260848B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
ITTO930428A IT1260848B (it) 1993-06-11 1993-06-11 Sistema a multiprocessore
DE69424221T DE69424221D1 (de) 1993-06-11 1994-06-09 Mehrrechnersystem
EP94108884A EP0628917B1 (en) 1993-06-11 1994-06-09 Multiprocessor system
US08/258,759 US5586258A (en) 1993-06-11 1994-06-13 Multilevel hierarchical multiprocessor computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITTO930428A IT1260848B (it) 1993-06-11 1993-06-11 Sistema a multiprocessore

Publications (3)

Publication Number Publication Date
ITTO930428A0 ITTO930428A0 (it) 1993-06-11
ITTO930428A1 true ITTO930428A1 (it) 1994-12-11
IT1260848B IT1260848B (it) 1996-04-23

Family

ID=11411555

Family Applications (1)

Application Number Title Priority Date Filing Date
ITTO930428A IT1260848B (it) 1993-06-11 1993-06-11 Sistema a multiprocessore

Country Status (4)

Country Link
US (1) US5586258A (it)
EP (1) EP0628917B1 (it)
DE (1) DE69424221D1 (it)
IT (1) IT1260848B (it)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
WO2002071248A2 (de) * 2001-03-05 2002-09-12 Pact Informationstechnologie Gmbh Verfahren und vorrichtungen zur datenbe- und/oder verarbeitung
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19654593A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh Umkonfigurierungs-Verfahren für programmierbare Bausteine zur Laufzeit
ATE243390T1 (de) 1996-12-27 2003-07-15 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen umladen von datenflussprozessoren (dfps) sowie bausteinen mit zwei- oder mehrdimensionalen programmierbaren zellstrukturen (fpgas, dpgas, o.dgl.)
DE19654846A1 (de) 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704728A1 (de) 1997-02-08 1998-08-13 Pact Inf Tech Gmbh Verfahren zur Selbstsynchronisation von konfigurierbaren Elementen eines programmierbaren Bausteines
DE19704742A1 (de) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
US6212606B1 (en) * 1998-10-13 2001-04-03 Compaq Computer Corporation Computer system and method for establishing a standardized shared level for each storage unit
CN1378665A (zh) 1999-06-10 2002-11-06 Pact信息技术有限公司 编程概念
US6973559B1 (en) * 1999-09-29 2005-12-06 Silicon Graphics, Inc. Scalable hypercube multiprocessor network for massive parallel processing
JP2004506261A (ja) 2000-06-13 2004-02-26 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト パイプラインｃｔプロトコルおよびｃｔ通信
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
AU2002220600A1 (en) 2000-10-06 2002-04-15 Pact Informationstechnologie Gmbh Cell system with segmented intermediate cell structure
US6990555B2 (en) 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
JP4783527B2 (ja) * 2001-01-31 2011-09-28 株式会社ガイア・システム・ソリューション データ処理システム、データ処理装置およびその制御方法
WO2005045692A2 (en) 2003-08-28 2005-05-19 Pact Xpp Technologies Ag Data processing device and method
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7210129B2 (en) 2001-08-16 2007-04-24 Pact Xpp Technologies Ag Method for translating programs for reconfigurable architectures
US7581076B2 (en) 2001-03-05 2009-08-25 Pact Xpp Technologies Ag Methods and devices for treating and/or processing data
WO2002103532A2 (de) 2001-06-20 2002-12-27 Pact Xpp Technologies Ag Verfahren zur bearbeitung von daten
JP4865960B2 (ja) 2001-06-25 2012-02-01 株式会社ガイア・システム・ソリューション データ処理装置およびその制御方法
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US7577822B2 (en) 2001-12-14 2009-08-18 Pact Xpp Technologies Ag Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization
US6993674B2 (en) 2001-12-27 2006-01-31 Pacific Design, Inc. System LSI architecture and method for controlling the clock of a data processing system through the use of instructions
DE10392560D2 (de) 2002-01-19 2005-05-12 Pact Xpp Technologies Ag Reconfigurierbarer Prozessor
WO2003071432A2 (de) 2002-02-18 2003-08-28 Pact Xpp Technologies Ag Bussysteme und rekonfigurationsverfahren
US7085866B1 (en) * 2002-02-19 2006-08-01 Hobson Richard F Hierarchical bus structure and memory access protocol for multiprocessor systems
US6959372B1 (en) * 2002-02-19 2005-10-25 Cogent Chipware Inc. Processor cluster architecture and associated parallel processing methods
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
WO2004038599A1 (de) 2002-09-06 2004-05-06 Pact Xpp Technologies Ag Rekonfigurierbare sequenzerstruktur
EP1974265A1 (de) 2006-01-18 2008-10-01 PACT XPP Technologies AG Hardwaredefinitionsverfahren
RU2397538C1 (ru) * 2008-12-25 2010-08-20 ООО Научно-исследовательский центр супер-ЭВМ и нейрокомпьютеров Многопроцессорный модуль
RU2402807C1 (ru) * 2009-05-04 2010-10-27 Федеральное Государственное Унитарное Предприятие "Государственный Рязанский Приборный Завод" Устройство цифровой обработки сигналов
US20120096292A1 (en) * 2010-10-15 2012-04-19 Mosaid Technologies Incorporated Method, system and apparatus for multi-level processing
RU2623806C1 (ru) * 2016-06-07 2017-06-29 Акционерное общество Научно-производственный центр "Электронные вычислительно-информационные системы" (АО НПЦ "ЭЛВИС") Способ и устройство обработки стереоизображений

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4130865A (en) * 1974-06-05 1978-12-19 Bolt Beranek And Newman Inc. Multiprocessor computer apparatus employing distributed communications paths and a passive task register
WO1983001135A1 (en) * 1981-09-18 1983-03-31 Rovsing As Christian Multiprocessor computer system
US4485438A (en) * 1982-06-28 1984-11-27 Myrmo Erik R High transfer rate between multi-processor units
IT1184015B (it) * 1985-12-13 1987-10-22 Elsag Sistema multiprocessore a piu livelli gerarchici
US4734865A (en) * 1986-01-28 1988-03-29 Bell & Howell Company Insertion machine with audit trail and command protocol
US4942575A (en) * 1988-06-17 1990-07-17 Modular Computer Systems, Inc. Error connection device for parity protected memory systems
US4912633A (en) * 1988-10-24 1990-03-27 Ncr Corporation Hierarchical multiple bus computer architecture
DE69231451T2 (de) * 1991-03-11 2001-05-10 Mips Technologies,Inc. Rückwärts kompatible Rechnerarchitektur mit erweiterten Wortbreiten und Adressraum

Also Published As

Publication number Publication date
EP0628917B1 (en) 2000-05-03
EP0628917A3 (en) 1995-08-09
ITTO930428A0 (it) 1993-06-11
EP0628917A2 (en) 1994-12-14
IT1260848B (it) 1996-04-23
US5586258A (en) 1996-12-17
DE69424221D1 (de) 2000-06-08

Similar Documents

Publication Publication Date Title
ITTO930428A1 (it) Sistema a multiprocessore
DE69230093D1 (de) Multiprozessorsystem
DE69326530D1 (de) Mehrrechnersystem
NO954685D0 (no) Defibrillator-elektrodesystem
FI954479A0 (fi) Hälytysjärjestelmä
DE59405047D1 (de) Sensorsystem
NO942613L (no) Robot-skjæresystem
DE69409386D1 (de) Sensorsystem
BR9404412A (pt) Sistema de monitoramento
DE69318447D1 (de) Erkennungssystem
DE69332058D1 (de) Mehrprozessorsystem
DE69416438D1 (de) Alarmanlage
DE69426585D1 (de) Sensorsystem
DE69410362D1 (de) Flüssigentwicklungssystem
DE59205860D1 (de) Rohrsystem
DE69433489D1 (de) Keratorefraktives system
AT399801B (de) Fütterungsanlage
BR9401762A (pt) Sistema de telealarme
BR9401853A (pt) Sistema de ligaçoes
BR9501308A (pt) Sistema de multiprocessador
DE69227272D1 (de) Multiprozessorssystem
BR9301761A (pt) Sistema flumeneletrógeno
BR9304948A (pt) Sistema TAMBOSI
GT199300083A (es) Sistema de construccion madray
DE69310510D1 (de) Standortbestimmungssystem

Legal Events

Date Code Title Description
0001 Granted