ITTO20060931A1 - Sistemi e metodi per ridurre l'interferenza fra celle di memoria - Google Patents
Sistemi e metodi per ridurre l'interferenza fra celle di memoriaInfo
- Publication number
- ITTO20060931A1 ITTO20060931A1 IT000931A ITTO20060931A ITTO20060931A1 IT TO20060931 A1 ITTO20060931 A1 IT TO20060931A1 IT 000931 A IT000931 A IT 000931A IT TO20060931 A ITTO20060931 A IT TO20060931A IT TO20060931 A1 ITTO20060931 A1 IT TO20060931A1
- Authority
- IT
- Italy
- Prior art keywords
- interference
- systems
- methods
- reduce
- memory cells
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT000931A ITTO20060931A1 (it) | 2006-12-29 | 2006-12-29 | Sistemi e metodi per ridurre l'interferenza fra celle di memoria |
| US12/005,994 US7706191B2 (en) | 2006-12-29 | 2007-12-28 | Systems and methods to reduce interference between memory cells |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT000931A ITTO20060931A1 (it) | 2006-12-29 | 2006-12-29 | Sistemi e metodi per ridurre l'interferenza fra celle di memoria |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ITTO20060931A1 true ITTO20060931A1 (it) | 2008-06-30 |
Family
ID=39715711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT000931A ITTO20060931A1 (it) | 2006-12-29 | 2006-12-29 | Sistemi e metodi per ridurre l'interferenza fra celle di memoria |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7706191B2 (it) |
| IT (1) | ITTO20060931A1 (it) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI436363B (zh) | 2010-05-11 | 2014-05-01 | Silicon Motion Inc | 資料儲存裝置以及快閃記憶體之資料寫入方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4170952B2 (ja) * | 2004-01-30 | 2008-10-22 | 株式会社東芝 | 半導体記憶装置 |
| JP4410188B2 (ja) * | 2004-11-12 | 2010-02-03 | 株式会社東芝 | 半導体記憶装置のデータ書き込み方法 |
| US7539052B2 (en) * | 2006-12-28 | 2009-05-26 | Micron Technology, Inc. | Non-volatile multilevel memory cell programming |
| US7508711B2 (en) * | 2007-04-30 | 2009-03-24 | Intel Corporation | Arrangements for operating a memory circuit |
-
2006
- 2006-12-29 IT IT000931A patent/ITTO20060931A1/it unknown
-
2007
- 2007-12-28 US US12/005,994 patent/US7706191B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US7706191B2 (en) | 2010-04-27 |
| US20080205155A1 (en) | 2008-08-28 |
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