ITMI921460A1 - SEMICONDUCTOR MEMORY DEVICE WITH POWER AND GROUND LINES OF THE INPUT TERMINAL ISOLATED FROM THOSE OF THE OUTPUT TERMINAL - Google Patents

SEMICONDUCTOR MEMORY DEVICE WITH POWER AND GROUND LINES OF THE INPUT TERMINAL ISOLATED FROM THOSE OF THE OUTPUT TERMINAL

Info

Publication number
ITMI921460A1
ITMI921460A1 IT001460A ITMI921460A ITMI921460A1 IT MI921460 A1 ITMI921460 A1 IT MI921460A1 IT 001460 A IT001460 A IT 001460A IT MI921460 A ITMI921460 A IT MI921460A IT MI921460 A1 ITMI921460 A1 IT MI921460A1
Authority
IT
Italy
Prior art keywords
those
power
memory device
semiconductor memory
ground lines
Prior art date
Application number
IT001460A
Other languages
Italian (it)
Inventor
Young-Ho Seo
Hyoung-Kyu Yim
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI921460A0 publication Critical patent/ITMI921460A0/en
Publication of ITMI921460A1 publication Critical patent/ITMI921460A1/en
Application granted granted Critical
Publication of IT1258990B publication Critical patent/IT1258990B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0218—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of field effect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
ITMI921460A 1991-06-19 1992-06-12 SEMICONDUCTOR MEMORY DEVICE WITH POWER AND GROUND LINES OF THE INPUT TERMINAL ISOLATED FROM THOSE OF THE OUTPUT TERMINAL IT1258990B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910010194A KR930001392A (en) 1991-06-19 1991-06-19 Power Ground Wire Wiring Method for Semiconductor Memory Device

Publications (3)

Publication Number Publication Date
ITMI921460A0 ITMI921460A0 (en) 1992-06-12
ITMI921460A1 true ITMI921460A1 (en) 1993-12-12
IT1258990B IT1258990B (en) 1996-03-11

Family

ID=19316015

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI921460A IT1258990B (en) 1991-06-19 1992-06-12 SEMICONDUCTOR MEMORY DEVICE WITH POWER AND GROUND LINES OF THE INPUT TERMINAL ISOLATED FROM THOSE OF THE OUTPUT TERMINAL

Country Status (7)

Country Link
JP (1) JPH0719851B2 (en)
KR (1) KR930001392A (en)
DE (1) DE4219927A1 (en)
FR (1) FR2678109B1 (en)
GB (1) GB2256968A (en)
IT (1) IT1258990B (en)
TW (1) TW245835B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100249166B1 (en) * 1997-03-07 2000-03-15 김영환 Esd protection circuit and manufacturing method thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5780828A (en) * 1980-11-07 1982-05-20 Hitachi Ltd Semiconductor integrated circuit device
JPS5922357A (en) * 1982-07-28 1984-02-04 Toshiba Corp Cmos type semiconductor integrated circuit
JPH0693497B2 (en) * 1986-07-30 1994-11-16 日本電気株式会社 Complementary MIS integrated circuit
GB2199695B (en) * 1987-01-06 1990-07-25 Samsung Semiconductor Inc Dynamic random access memory with selective well biasing
US5023689A (en) * 1987-03-18 1991-06-11 Nec Corporation Complementary integrated circuit device equipped with latch-up preventing means

Also Published As

Publication number Publication date
TW245835B (en) 1995-04-21
JPH06112435A (en) 1994-04-22
IT1258990B (en) 1996-03-11
JPH0719851B2 (en) 1995-03-06
FR2678109A1 (en) 1992-12-24
KR930001392A (en) 1993-01-16
DE4219927A1 (en) 1992-12-24
ITMI921460A0 (en) 1992-06-12
FR2678109B1 (en) 1994-01-21
GB9212830D0 (en) 1992-07-29
GB2256968A (en) 1992-12-23

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Legal Events

Date Code Title Description
0001 Granted