ITMI20032444A1 - Metodo per ridurre la difettosita' dopo un attacco metallico in dispositivi semic0nduttori. - Google Patents

Metodo per ridurre la difettosita' dopo un attacco metallico in dispositivi semic0nduttori.

Info

Publication number
ITMI20032444A1
ITMI20032444A1 IT002444A ITMI20032444A ITMI20032444A1 IT MI20032444 A1 ITMI20032444 A1 IT MI20032444A1 IT 002444 A IT002444 A IT 002444A IT MI20032444 A ITMI20032444 A IT MI20032444A IT MI20032444 A1 ITMI20032444 A1 IT MI20032444A1
Authority
IT
Italy
Prior art keywords
semiconductor devices
metallic attachment
reduce defectivity
defectivity
reduce
Prior art date
Application number
IT002444A
Other languages
English (en)
Inventor
Simone Alba
Alessandro Spandre
Barbara Zanderighi
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT002444A priority Critical patent/ITMI20032444A1/it
Priority to US11/009,687 priority patent/US7288427B2/en
Publication of ITMI20032444A1 publication Critical patent/ITMI20032444A1/it
Priority to US11/855,229 priority patent/US20080001295A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
IT002444A 2003-12-12 2003-12-12 Metodo per ridurre la difettosita' dopo un attacco metallico in dispositivi semic0nduttori. ITMI20032444A1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT002444A ITMI20032444A1 (it) 2003-12-12 2003-12-12 Metodo per ridurre la difettosita' dopo un attacco metallico in dispositivi semic0nduttori.
US11/009,687 US7288427B2 (en) 2003-12-12 2004-12-10 Method for reducing defects after a metal etching in semiconductor devices
US11/855,229 US20080001295A1 (en) 2003-12-12 2007-09-14 Method for reducing defects after a metal etching in semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT002444A ITMI20032444A1 (it) 2003-12-12 2003-12-12 Metodo per ridurre la difettosita' dopo un attacco metallico in dispositivi semic0nduttori.

Publications (1)

Publication Number Publication Date
ITMI20032444A1 true ITMI20032444A1 (it) 2005-06-13

Family

ID=34856904

Family Applications (1)

Application Number Title Priority Date Filing Date
IT002444A ITMI20032444A1 (it) 2003-12-12 2003-12-12 Metodo per ridurre la difettosita' dopo un attacco metallico in dispositivi semic0nduttori.

Country Status (2)

Country Link
US (2) US7288427B2 (it)
IT (1) ITMI20032444A1 (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006046364A1 (de) * 2006-09-29 2008-04-03 Advanced Micro Devices, Inc., Sunnyvale ARC-Schicht mit geringerer Neigung zum Ablösen und Verfahren zur Herstellung derselben
US8748323B2 (en) * 2008-07-07 2014-06-10 Macronix International Co., Ltd. Patterning method
CN104576514B (zh) * 2013-10-29 2017-11-24 中芯国际集成电路制造(上海)有限公司 半导体器件的制备方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093973A (en) * 1998-09-30 2000-07-25 Advanced Micro Devices, Inc. Hard mask for metal patterning
US6153504A (en) * 1999-08-16 2000-11-28 Advanced Micro Devices, Inc. Method of using a silicon oxynitride ARC for final metal layer
US6345399B1 (en) * 2000-09-27 2002-02-12 International Business Machines Corporation Hard mask process to prevent surface roughness for selective dielectric etching
DE10062660B4 (de) * 2000-12-15 2010-05-06 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Siliciumoxynitrid-ARC-Schicht über einer Halbleiterstruktur
DE10218955B4 (de) * 2002-04-27 2004-09-09 Infineon Technologies Ag Verfahren zur Herstellung einer strukturierten Schicht auf einem Halbleitersubstrat

Also Published As

Publication number Publication date
US20080001295A1 (en) 2008-01-03
US20050186780A1 (en) 2005-08-25
US7288427B2 (en) 2007-10-30

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