IT970954B - Metodo di diffusione planare di zone di un circuito integrato monolitico - Google Patents
Metodo di diffusione planare di zone di un circuito integrato monoliticoInfo
- Publication number
- IT970954B IT970954B IT31759/72A IT3175972A IT970954B IT 970954 B IT970954 B IT 970954B IT 31759/72 A IT31759/72 A IT 31759/72A IT 3175972 A IT3175972 A IT 3175972A IT 970954 B IT970954 B IT 970954B
- Authority
- IT
- Italy
- Prior art keywords
- zones
- integrated circuit
- monolithic integrated
- planar diffusion
- diffusion
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/051—Etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/151—Simultaneous diffusion
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2157633A DE2157633C3 (de) | 1971-11-20 | 1971-11-20 | Verfahren zum Herstellen von Zonen einer monolithisch integrierten Festkörperschaltung |
Publications (1)
Publication Number | Publication Date |
---|---|
IT970954B true IT970954B (it) | 1974-04-20 |
Family
ID=5825659
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT31759/72A IT970954B (it) | 1971-11-20 | 1972-11-17 | Metodo di diffusione planare di zone di un circuito integrato monolitico |
Country Status (4)
Country | Link |
---|---|
US (1) | US3837936A (it) |
DE (1) | DE2157633C3 (it) |
FR (1) | FR2160667B1 (it) |
IT (1) | IT970954B (it) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2282162A1 (fr) * | 1974-08-12 | 1976-03-12 | Radiotechnique Compelec | Procede de realisation de dispositifs semiconducteurs |
US4153487A (en) * | 1974-12-27 | 1979-05-08 | Tokyo Shibaura Electric Co., Ltd. | Method of manufacturing intergrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques |
US4151019A (en) * | 1974-12-27 | 1979-04-24 | Tokyo Shibaura Electric Co., Ltd. | Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques |
USRE30282E (en) * | 1976-06-28 | 1980-05-27 | Motorola, Inc. | Double master mask process for integrated circuit manufacture |
US4149906A (en) * | 1977-04-29 | 1979-04-17 | International Business Machines Corporation | Process for fabrication of merged transistor logic (MTL) cells |
US4135954A (en) * | 1977-07-12 | 1979-01-23 | International Business Machines Corporation | Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers |
US4110126A (en) * | 1977-08-31 | 1978-08-29 | International Business Machines Corporation | NPN/PNP Fabrication process with improved alignment |
US4243435A (en) * | 1979-06-22 | 1981-01-06 | International Business Machines Corporation | Bipolar transistor fabrication process with an ion implanted emitter |
DE3136731A1 (de) * | 1981-09-16 | 1983-03-31 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Verfahren zum herstellen einer halbleiteranordnung |
US4648909A (en) * | 1984-11-28 | 1987-03-10 | Fairchild Semiconductor Corporation | Fabrication process employing special masks for the manufacture of high speed bipolar analog integrated circuits |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1187611A (en) * | 1966-03-23 | 1970-04-08 | Matsushita Electronics Corp | Method of manufacturing Semiconductors Device |
US3497407A (en) * | 1966-12-28 | 1970-02-24 | Ibm | Etching of semiconductor coatings of sio2 |
DE1614691B2 (de) * | 1967-12-21 | 1975-12-04 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zum Herstellen von Halbleiterbauelementen |
US3542551A (en) * | 1968-07-01 | 1970-11-24 | Trw Semiconductors Inc | Method of etching patterns into solid state devices |
US3560278A (en) * | 1968-11-29 | 1971-02-02 | Motorola Inc | Alignment process for fabricating semiconductor devices |
-
1971
- 1971-11-20 DE DE2157633A patent/DE2157633C3/de not_active Expired
-
1972
- 1972-10-18 US US00298724A patent/US3837936A/en not_active Expired - Lifetime
- 1972-11-17 IT IT31759/72A patent/IT970954B/it active
- 1972-11-20 FR FR7241105A patent/FR2160667B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
FR2160667B1 (it) | 1976-04-23 |
FR2160667A1 (it) | 1973-06-29 |
DE2157633A1 (de) | 1973-06-07 |
US3837936A (en) | 1974-09-24 |
DE2157633C3 (de) | 1980-01-24 |
DE2157633B2 (de) | 1979-05-10 |
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