IT960350B - Perfezionamento nei sistemi calco latori comprendenti un elaboratore centrale combinato con una memoria esterna - Google Patents

Perfezionamento nei sistemi calco latori comprendenti un elaboratore centrale combinato con una memoria esterna

Info

Publication number
IT960350B
IT960350B IT5248072A IT5248072A IT960350B IT 960350 B IT960350 B IT 960350B IT 5248072 A IT5248072 A IT 5248072A IT 5248072 A IT5248072 A IT 5248072A IT 960350 B IT960350 B IT 960350B
Authority
IT
Italy
Prior art keywords
latori
calco
improvement
external memory
central computer
Prior art date
Application number
IT5248072A
Other languages
English (en)
Italian (it)
Inventor
J Vandierendonck
E Caudel
G Boone
B Wayne
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/176,669 external-priority patent/US3962684A/en
Priority claimed from US05/176,664 external-priority patent/US4037094A/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of IT960350B publication Critical patent/IT960350B/it

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50Adding; Subtracting
    • G06F7/501Half or full adders, i.e. basic adder cells for one denomination
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18Handling requests for interconnection or transfer for access to memory bus based on priority control
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/386Special constructional features
    • G06F2207/3872Precharge of output to prevent leakage

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Multi Processors (AREA)
  • Microcomputers (AREA)
  • Logic Circuits (AREA)
  • Advance Control (AREA)
IT5248072A 1971-08-31 1972-08-31 Perfezionamento nei sistemi calco latori comprendenti un elaboratore centrale combinato con una memoria esterna IT960350B (it)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US17666671A 1971-08-31 1971-08-31
US17666571A 1971-08-31 1971-08-31
US17666871A 1971-08-31 1971-08-31
US17666771A 1971-08-31 1971-08-31
US17667071A 1971-08-31 1971-08-31
US05/176,669 US3962684A (en) 1971-08-31 1971-08-31 Computing system interface using common parallel bus and segmented addressing
US05/176,664 US4037094A (en) 1971-08-31 1971-08-31 Multi-functional arithmetic and logical unit

Publications (1)

Publication Number Publication Date
IT960350B true IT960350B (it) 1973-11-20

Family

ID=27569152

Family Applications (1)

Application Number Title Priority Date Filing Date
IT5248072A IT960350B (it) 1971-08-31 1972-08-31 Perfezionamento nei sistemi calco latori comprendenti un elaboratore centrale combinato con una memoria esterna

Country Status (5)

Country Link
JP (1) JPS5537031B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE2242912A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB1410081A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IT (1) IT960350B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
NL (1) NL7211814A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5821299B2 (ja) * 1974-02-25 1983-04-28 株式会社東芝 メモリ
JPS5821300B2 (ja) * 1974-03-20 1983-04-28 株式会社東芝 デンシケイサンキ ノ メモリアドレスシテイホウシキ
JPS5264846A (en) * 1975-11-25 1977-05-28 Hitachi Ltd Unit selection system
JPS54134934A (en) * 1978-04-12 1979-10-19 Toshiba Corp Semiconductor memory device
GB2175109A (en) * 1985-05-10 1986-11-19 Philips Electronic Associated Digital code detector circuits

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1933873U (de) 1964-03-18 1966-03-03 Karl Moertl Pumpenanordnung an tankwagen fuer fluessigmist.
US3551892A (en) * 1969-01-15 1970-12-29 Ibm Interaction in a multi-processing system utilizing central timers

Also Published As

Publication number Publication date
NL7211814A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1973-03-02
DE2242912A1 (de) 1973-04-12
JPS4835736A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1973-05-26
JPS5537031B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1980-09-25
GB1410081A (en) 1975-10-15

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