IT956632B - INPUT CIRCUIT AND PARITY BIT GENERATOR FOR DATA PROCESSING COMPLEXES - Google Patents

INPUT CIRCUIT AND PARITY BIT GENERATOR FOR DATA PROCESSING COMPLEXES

Info

Publication number
IT956632B
IT956632B IT2575972A IT2575972A IT956632B IT 956632 B IT956632 B IT 956632B IT 2575972 A IT2575972 A IT 2575972A IT 2575972 A IT2575972 A IT 2575972A IT 956632 B IT956632 B IT 956632B
Authority
IT
Italy
Prior art keywords
data processing
input circuit
parity bit
bit generator
processing complexes
Prior art date
Application number
IT2575972A
Other languages
Italian (it)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT956632B publication Critical patent/IT956632B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/321—Program or instruction counter, e.g. incrementing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)
IT2575972A 1971-07-16 1972-06-16 INPUT CIRCUIT AND PARITY BIT GENERATOR FOR DATA PROCESSING COMPLEXES IT956632B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19712135607 DE2135607C2 (en) 1971-07-16 1971-07-16 Circuit arrangement for incrementing or decrementing

Publications (1)

Publication Number Publication Date
IT956632B true IT956632B (en) 1973-10-10

Family

ID=5813901

Family Applications (1)

Application Number Title Priority Date Filing Date
IT2575972A IT956632B (en) 1971-07-16 1972-06-16 INPUT CIRCUIT AND PARITY BIT GENERATOR FOR DATA PROCESSING COMPLEXES

Country Status (5)

Country Link
JP (1) JPS5230099B1 (en)
DE (1) DE2135607C2 (en)
FR (1) FR2146791A5 (en)
GB (1) GB1402132A (en)
IT (1) IT956632B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4280190A (en) * 1979-08-09 1981-07-21 Motorola, Inc. Incrementer/decrementer circuit
ATE45823T1 (en) * 1985-01-29 1989-09-15 Siemens Ag ORDER TO INCREASE OR DECREASE A BINARY OPERAND BY A PREFERRED VALUE.

Also Published As

Publication number Publication date
FR2146791A5 (en) 1973-03-02
JPS5230099B1 (en) 1977-08-05
DE2135607B2 (en) 1972-12-07
DE2135607C2 (en) 1974-12-12
GB1402132A (en) 1975-08-06
DE2135607A1 (en) 1972-12-07

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