IT9019705A0 - MONOLITHICALLY INTEGRATED CIRCUIT ARRANGEMENT - Google Patents

MONOLITHICALLY INTEGRATED CIRCUIT ARRANGEMENT

Info

Publication number
IT9019705A0
IT9019705A0 IT19705A IT1970590A IT9019705A0 IT 9019705 A0 IT9019705 A0 IT 9019705A0 IT 19705 A IT19705 A IT 19705A IT 1970590 A IT1970590 A IT 1970590A IT 9019705 A0 IT9019705 A0 IT 9019705A0
Authority
IT
Italy
Prior art keywords
integrated circuit
circuit arrangement
monolithically integrated
monolithically
arrangement
Prior art date
Application number
IT19705A
Other languages
Italian (it)
Other versions
IT9019705A1 (en
IT1239451B (en
Inventor
Hartmut Seiler
Original Assignee
Bosch Gmbh Robert
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bosch Gmbh Robert filed Critical Bosch Gmbh Robert
Publication of IT9019705A0 publication Critical patent/IT9019705A0/en
Publication of IT9019705A1 publication Critical patent/IT9019705A1/en
Application granted granted Critical
Publication of IT1239451B publication Critical patent/IT1239451B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
IT19705A 1989-03-17 1990-03-16 MONOLITHICALLY INTEGRATED CIRCUIT PROVISION IT1239451B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE3908794A DE3908794C2 (en) 1989-03-17 1989-03-17 Monolithically integrated circuit arrangement in which parasitic substrate effects are avoided

Publications (3)

Publication Number Publication Date
IT9019705A0 true IT9019705A0 (en) 1990-03-16
IT9019705A1 IT9019705A1 (en) 1991-09-16
IT1239451B IT1239451B (en) 1993-11-02

Family

ID=6376584

Family Applications (1)

Application Number Title Priority Date Filing Date
IT19705A IT1239451B (en) 1989-03-17 1990-03-16 MONOLITHICALLY INTEGRATED CIRCUIT PROVISION

Country Status (2)

Country Link
DE (1) DE3908794C2 (en)
IT (1) IT1239451B (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3507181A1 (en) * 1985-03-01 1986-09-04 IC - Haus GmbH, 6501 Bodenheim Circuit arrangement for avoiding parasitic substrate effects in integrated circuits

Also Published As

Publication number Publication date
IT9019705A1 (en) 1991-09-16
IT1239451B (en) 1993-11-02
DE3908794A1 (en) 1990-09-27
DE3908794C2 (en) 2000-02-03

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960327