IT8023691A0 - Sistema perfezionato perl'esecuzione di funzioni logiche. - Google Patents

Sistema perfezionato perl'esecuzione di funzioni logiche.

Info

Publication number
IT8023691A0
IT8023691A0 IT8023691A IT2369180A IT8023691A0 IT 8023691 A0 IT8023691 A0 IT 8023691A0 IT 8023691 A IT8023691 A IT 8023691A IT 2369180 A IT2369180 A IT 2369180A IT 8023691 A0 IT8023691 A0 IT 8023691A0
Authority
IT
Italy
Prior art keywords
improved system
logical functions
executing logical
executing
functions
Prior art date
Application number
IT8023691A
Other languages
English (en)
Other versions
IT1150035B (it
Inventor
Sumit Das Gupta
Prabhakar Goel
Williams Thomas Walter
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT8023691A0 publication Critical patent/IT8023691A0/it
Application granted granted Critical
Publication of IT1150035B publication Critical patent/IT1150035B/it

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
IT23691/80A 1979-08-13 1980-07-25 Sistema perfezionato per l'esecuzione di funzioni logiche IT1150035B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/066,130 US4293919A (en) 1979-08-13 1979-08-13 Level sensitive scan design (LSSD) system

Publications (2)

Publication Number Publication Date
IT8023691A0 true IT8023691A0 (it) 1980-07-25
IT1150035B IT1150035B (it) 1986-12-10

Family

ID=22067422

Family Applications (1)

Application Number Title Priority Date Filing Date
IT23691/80A IT1150035B (it) 1979-08-13 1980-07-25 Sistema perfezionato per l'esecuzione di funzioni logiche

Country Status (5)

Country Link
US (1) US4293919A (it)
EP (1) EP0023972B1 (it)
JP (1) JPS5629742A (it)
DE (1) DE3069749D1 (it)
IT (1) IT1150035B (it)

Families Citing this family (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045511B2 (ja) * 1979-05-14 1985-10-09 株式会社日立製作所 ラッチ付きシフトレジスタ
US4441075A (en) * 1981-07-02 1984-04-03 International Business Machines Corporation Circuit arrangement which permits the testing of each individual chip and interchip connection in a high density packaging structure having a plurality of interconnected chips, without any physical disconnection
US4503386A (en) * 1982-04-20 1985-03-05 International Business Machines Corporation Chip partitioning aid (CPA)-A structure for test pattern generation for large logic networks
US4477902A (en) * 1982-06-18 1984-10-16 Ibm Corporation Testing method for assuring AC performance of high performance random logic designs using low speed tester
US4493077A (en) * 1982-09-09 1985-01-08 At&T Laboratories Scan testable integrated circuit
US4527249A (en) * 1982-10-22 1985-07-02 Control Data Corporation Simulator system for logic design validation
US4488259A (en) * 1982-10-29 1984-12-11 Ibm Corporation On chip monitor
US4495629A (en) * 1983-01-25 1985-01-22 Storage Technology Partners CMOS scannable latch
US4791602A (en) * 1983-04-14 1988-12-13 Control Data Corporation Soft programmable logic array
US4682329A (en) * 1985-03-28 1987-07-21 Kluth Daniel J Test system providing testing sites for logic circuits
US4937770A (en) * 1986-02-07 1990-06-26 Teradyne, Inc. Simulation system
US4749947A (en) * 1986-03-10 1988-06-07 Cross-Check Systems, Inc. Grid-based, "cross-check" test structure for testing integrated circuits
US4672646A (en) * 1986-09-16 1987-06-09 Hewlett-Packard Company Direct-injection FIFO shift register
US5477165A (en) * 1986-09-19 1995-12-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
GB2210171B (en) * 1987-09-28 1991-06-26 Plessey Co Plc Test circuit
US5155432A (en) * 1987-10-07 1992-10-13 Xilinx, Inc. System for scan testing of logic circuit networks
US4855669A (en) * 1987-10-07 1989-08-08 Xilinx, Inc. System for scan testing of logic circuit networks
US5068603A (en) * 1987-10-07 1991-11-26 Xilinx, Inc. Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays
US5047710A (en) * 1987-10-07 1991-09-10 Xilinx, Inc. System for scan testing of logic circuit networks
US5065090A (en) * 1988-07-13 1991-11-12 Cross-Check Technology, Inc. Method for testing integrated circuits having a grid-based, "cross-check" te
US4945536A (en) * 1988-09-09 1990-07-31 Northern Telecom Limited Method and apparatus for testing digital systems
US5039939A (en) * 1988-12-29 1991-08-13 International Business Machines Corporation Calculating AC chip performance using the LSSD scan path
US4982402A (en) * 1989-02-03 1991-01-01 Digital Equipment Corporation Method and apparatus for detecting and correcting errors in a pipelined computer system
US5018144A (en) * 1989-04-28 1991-05-21 International Business Machines Corporation Logic performance verification and transition fault detection
US5023875A (en) * 1989-05-26 1991-06-11 Hughes Aircraft Company Interlaced scan fault detection system
US5079725A (en) * 1989-11-17 1992-01-07 Ibm Corporation Chip identification method for use with scan design systems and scan testing techniques
US5157627A (en) * 1990-07-17 1992-10-20 Crosscheck Technology, Inc. Method and apparatus for setting desired signal level on storage element
US5068881A (en) * 1990-08-10 1991-11-26 Hewlett-Packard Company Scannable register with delay test capability
US5202624A (en) * 1990-08-31 1993-04-13 Cross-Check Technology, Inc. Interface between ic operational circuitry for coupling test signal from internal test matrix
US5179534A (en) * 1990-10-23 1993-01-12 Crosscheck Technology, Inc. Method and apparatus for setting desired logic state at internal point of a select storage element
US5206862A (en) * 1991-03-08 1993-04-27 Crosscheck Technology, Inc. Method and apparatus for locally deriving test signals from previous response signals
US5230001A (en) * 1991-03-08 1993-07-20 Crosscheck Technology, Inc. Method for testing a sequential circuit by splicing test vectors into sequential test pattern
US5648661A (en) * 1992-07-02 1997-07-15 Lsi Logic Corporation Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies
US5389556A (en) * 1992-07-02 1995-02-14 Lsi Logic Corporation Individually powering-up unsingulated dies on a wafer
US5532174A (en) * 1994-04-22 1996-07-02 Lsi Logic Corporation Wafer level integrated circuit testing with a sacrificial metal layer
US6272465B1 (en) 1994-11-02 2001-08-07 Legerity, Inc. Monolithic PC audio circuit
US5859995A (en) * 1994-11-02 1999-01-12 Advanced Micro Devices, Inc. Method and apparatus for coordinating combinatorial logic-clocked state machines
US5821773A (en) * 1995-09-06 1998-10-13 Altera Corporation Look-up table based logic element with complete permutability of the inputs to the secondary signals
US5684808A (en) * 1995-09-19 1997-11-04 Unisys Corporation System and method for satisfying mutually exclusive gating requirements in automatic test pattern generation systems
US5869979A (en) * 1996-04-05 1999-02-09 Altera Corporation Technique for preconditioning I/Os during reconfiguration
US6184707B1 (en) 1998-10-07 2001-02-06 Altera Corporation Look-up table based logic element with complete permutability of the inputs to the secondary signals
DE19929546C1 (de) * 1999-06-23 2000-09-07 Michael Goessel Multi-Mode Speicherelement
US6629277B1 (en) 2000-02-15 2003-09-30 Sun Microsystems, Inc. LSSD interface
US6785855B2 (en) 2001-11-13 2004-08-31 Sun Microsystems, Inc. Implementation of an assertion check in ATPG models
US7039843B2 (en) * 2001-11-13 2006-05-02 Sun Microsystems, Inc. Modeling custom scan flops in level sensitive scan design
US20090009210A1 (en) * 2004-08-03 2009-01-08 Koninklijke Philips Electronics, N.V. Scan-Testable Logic Circuit
US8010856B2 (en) * 2007-10-31 2011-08-30 Verigy (Singapore) Pte. Ltd. Methods for analyzing scan chains, and for determining numbers or locations of hold time faults in scan chains
US7853846B2 (en) * 2007-10-31 2010-12-14 Verigy (Singapore) Pte. Ltd. Locating hold time violations in scan chains by generating patterns on ATE
WO2012027458A1 (en) 2010-08-26 2012-03-01 Semprius, Inc. Structures and methods for testing printable integrated circuits
US9222973B2 (en) 2011-01-20 2015-12-29 International Business Machines Corporation Protecting chip settings using secured scan chains
US8656235B2 (en) 2011-11-28 2014-02-18 International Business Machines Corporation Verifying and detecting boundary scan cells to input/output mapping
US11131706B2 (en) * 2015-12-08 2021-09-28 International Business Machines Corporation Degradation monitoring of semiconductor chips

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761695A (en) * 1972-10-16 1973-09-25 Ibm Method of level sensitive testing a functional logic system
US3784907A (en) * 1972-10-16 1974-01-08 Ibm Method of propagation delay testing a functional logic system
US3806891A (en) * 1972-12-26 1974-04-23 Ibm Logic circuit for scan-in/scan-out
US3783254A (en) * 1972-10-16 1974-01-01 Ibm Level sensitive logic system
US4051352A (en) * 1976-06-30 1977-09-27 International Business Machines Corporation Level sensitive embedded array logic system

Also Published As

Publication number Publication date
EP0023972B1 (en) 1984-12-05
IT1150035B (it) 1986-12-10
EP0023972A3 (en) 1981-08-26
DE3069749D1 (en) 1985-01-17
JPS6211735B2 (it) 1987-03-14
JPS5629742A (en) 1981-03-25
US4293919A (en) 1981-10-06
EP0023972A2 (en) 1981-02-18

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960729