IT201700051944A1 - Rete di propagazione della credenza a dimensione minima per codificatori e decodificatori iterativi fec e relativo metodo di instradamento - Google Patents

Rete di propagazione della credenza a dimensione minima per codificatori e decodificatori iterativi fec e relativo metodo di instradamento

Info

Publication number
IT201700051944A1
IT201700051944A1 IT102017000051944A IT201700051944A IT201700051944A1 IT 201700051944 A1 IT201700051944 A1 IT 201700051944A1 IT 102017000051944 A IT102017000051944 A IT 102017000051944A IT 201700051944 A IT201700051944 A IT 201700051944A IT 201700051944 A1 IT201700051944 A1 IT 201700051944A1
Authority
IT
Italy
Prior art keywords
codificators
credence
fec
minimum size
routing method
Prior art date
Application number
IT102017000051944A
Other languages
English (en)
Inventor
Domenico Giancristofaro
Massimo Fonte
Original Assignee
Thales Alenia Space Italia Spa Con Unico Socio
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales Alenia Space Italia Spa Con Unico Socio filed Critical Thales Alenia Space Italia Spa Con Unico Socio
Priority to IT102017000051944A priority Critical patent/IT201700051944A1/it
Priority to PCT/EP2018/062266 priority patent/WO2018206803A1/en
Priority to US16/612,959 priority patent/US11526396B2/en
Priority to EP18722570.1A priority patent/EP3622642B1/en
Publication of IT201700051944A1 publication Critical patent/IT201700051944A1/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2771—Internal interleaver for turbo codes
    • H03M13/2775—Contention or collision free turbo code internal interleaver
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6566—Implementations concerning memory access contentions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13076—Distributing frame, MDF, cross-connect switch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Error Detection And Correction (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
IT102017000051944A 2017-05-12 2017-05-12 Rete di propagazione della credenza a dimensione minima per codificatori e decodificatori iterativi fec e relativo metodo di instradamento IT201700051944A1 (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT102017000051944A IT201700051944A1 (it) 2017-05-12 2017-05-12 Rete di propagazione della credenza a dimensione minima per codificatori e decodificatori iterativi fec e relativo metodo di instradamento
PCT/EP2018/062266 WO2018206803A1 (en) 2017-05-12 2018-05-11 Minimum-size belief propagation network for fec iterative encoders and decoders and related routing method
US16/612,959 US11526396B2 (en) 2017-05-12 2018-05-11 Minimum-size belief propagation network for FEC iterative encoders and decoders and related routing method
EP18722570.1A EP3622642B1 (en) 2017-05-12 2018-05-11 Minimum-size belief propagation network for fec iterative encoders and decoders and related routing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT102017000051944A IT201700051944A1 (it) 2017-05-12 2017-05-12 Rete di propagazione della credenza a dimensione minima per codificatori e decodificatori iterativi fec e relativo metodo di instradamento

Publications (1)

Publication Number Publication Date
IT201700051944A1 true IT201700051944A1 (it) 2018-11-12

Family

ID=59812039

Family Applications (1)

Application Number Title Priority Date Filing Date
IT102017000051944A IT201700051944A1 (it) 2017-05-12 2017-05-12 Rete di propagazione della credenza a dimensione minima per codificatori e decodificatori iterativi fec e relativo metodo di instradamento

Country Status (4)

Country Link
US (1) US11526396B2 (it)
EP (1) EP3622642B1 (it)
IT (1) IT201700051944A1 (it)
WO (1) WO2018206803A1 (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11329754B2 (en) * 2020-03-03 2022-05-10 Rockwell Collins, Inc. Variable data rate broadcast method for channels requiring equalization
US11804859B2 (en) * 2022-01-20 2023-10-31 Hewlett Packard Enterprise Development Lp Analog error detection and correction in analog in-memory crossbars
CN115379318B (zh) * 2022-08-03 2024-04-05 无锡芯光互连技术研究院有限公司 一种benes网络路由投机求解方法和装置
CN115766190B (zh) * 2022-11-10 2023-07-21 北京海泰方圆科技股份有限公司 一种任意集合元素加密方法、解密方法及电子设备

Citations (2)

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Publication number Priority date Publication date Assignee Title
US4653019A (en) * 1984-04-19 1987-03-24 Concurrent Computer Corporation High speed barrel shifter
US20130156133A1 (en) * 2010-09-08 2013-06-20 Giuseppe Gentile Flexible Channel Decoder

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US4807280A (en) * 1987-09-18 1989-02-21 Pacific Bell Cross-connect switch
US5541914A (en) * 1994-01-19 1996-07-30 Krishnamoorthy; Ashok V. Packet-switched self-routing multistage interconnection network having contention-free fanout, low-loss routing, and fanin buffering to efficiently realize arbitrarily low packet loss
JP3094849B2 (ja) * 1995-06-21 2000-10-03 株式会社日立製作所 並列計算機およびその多段結合網
US6304550B1 (en) * 1996-01-17 2001-10-16 Alcatel Usa, Inc. System and method for broadcast control of a data transmission system
US6456838B1 (en) * 1999-02-17 2002-09-24 Verizon Laboratories Inc. Generic approach to generating permutations for all-to-all personalized exchange for self-routing multistage interconnection networks
US6789218B1 (en) 2000-01-03 2004-09-07 Icoding Technology, Inc. High spread highly randomized generatable interleavers
US6775800B2 (en) 2000-01-03 2004-08-10 Icoding Technology, Inc. System and method for high speed processing of turbo codes
US7260092B2 (en) * 2000-04-11 2007-08-21 Lsi Corporation Time slot interchanger
GB2399722A (en) * 2003-03-21 2004-09-22 Sony Uk Ltd Data communication synchronisation
JP5049652B2 (ja) * 2006-09-07 2012-10-17 キヤノン株式会社 通信システム、データの再生制御方法、コントローラ、コントローラの制御方法、アダプタ、アダプタの制御方法、およびプログラム
US8649370B2 (en) * 2007-05-17 2014-02-11 Ciena Corporation Systems and methods for programming connections through a multi-stage switch fabric with blocking recovery, background rebalancing, and rollback
US9157952B2 (en) * 2011-04-14 2015-10-13 National Instruments Corporation Switch matrix system and method
US10674241B2 (en) * 2018-04-23 2020-06-02 Ciena Corporation Multipath selection in an ethernet fabric in a modular network element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4653019A (en) * 1984-04-19 1987-03-24 Concurrent Computer Corporation High speed barrel shifter
US20130156133A1 (en) * 2010-09-08 2013-06-20 Giuseppe Gentile Flexible Channel Decoder

Also Published As

Publication number Publication date
WO2018206803A8 (en) 2019-03-28
EP3622642A1 (en) 2020-03-18
EP3622642B1 (en) 2021-01-20
WO2018206803A1 (en) 2018-11-15
US20200081766A1 (en) 2020-03-12
US11526396B2 (en) 2022-12-13

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