IT201700021374A1 - ELECTRONIC CIRCUIT, ULTRASONIC EQUIPMENT AND CORRESPONDENT PROCEDURE - Google Patents

Description

"Electronic circuit, ultrasound equipment and corresponding procedure"

TEXT OF THE DESCRIPTION

Technical field

The description refers to electronic circuits. One or more embodiments may refer to electronic circuits usable, for example, in ultrasonic transmission channels.

One or more embodiments can find application, for example, in ultrasound equipment.

Technological background

Ultrasound systems, such as those used in the medical field, can provide for the presence of an ultrasound channel having the task of electrically stimulating a transducer (for example an ultrasound generator of piezoelectric or capacitive material) connected to its output during a phase transmission. Conversely, during a reception phase, the channel receives the echo of the transmitted wave from the transducer, transferring it to the signal receiving and processing circuitry.

Over the years, a rather extensive research and innovation activity has been dedicated to this technological sector, as attested by documents such as, for example. US 9455 693 B2.

Purpose and summary

In the face of this extensive activity, the need is still felt to have improved solutions, for example as regards the reduction of phenomena, such as charge injection phenomena on the connected nodes along the reception path, susceptible, in the case of the application to ultrasound equipment, to generate artifacts in the processing phase of the received images.

One or more embodiments have the purpose of helping to meet this need.

According to one or more embodiments, this object can be achieved thanks to a circuit having the characteristics referred to in the following claims.

One or more embodiments may relate to a corresponding equipment (for example an ultrasound equipment) as well as a corresponding procedure.

The claims form an integral part of the technical teachings administered herein in relation to one or more embodiments.

One or more embodiments may offer one or more of the following advantages:

- extensive reduction, and virtual elimination, of negative effects likely to occur when the various blocks included in an ultrasound channel are switched on / off, these phenomena being likely to be particularly critical when linear drivers are used,

- possibility of avoiding voltage drops, attenuation or distortion of the signal both during the transmission phase and during the reception phase,

- feasibility with low voltage components and with reduced consumption (for example in continuous),

- possibility, in the case of linear drivers, to modulate the glitch related to the output offset of the corresponding operational amplifier by moving its harmonic content to frequencies outside the range used for detection.

Brief description of the various views of the drawings

One or more embodiments will now be described, purely by way of non-limiting example, with reference to the attached figures, in which:

- Figure 1 exemplifies possible general criteria for using an ultrasound transmission system,

- Figure 2 illustrates possible variants that can be introduced in a scheme such as that of Figure 1,

- Figure 3 is an example of one or more embodiments,

- Figures 4 and 5 exemplify different operating conditions of one or more embodiments, e

Figures 6 and 7 are circuit diagrams of greater detail exemplifying possible embodiments.

Detailed description

Various specific details are illustrated in the following description in order to provide an in-depth understanding of various examples of embodiments according to the disclosure. The embodiments can be obtained without one or more of the specific details, or with other processes, components, materials, etc. In other cases, known structures, materials or operations are not illustrated or described in detail so that the various aspects of the embodiments will not be made unclear. A reference to "an embodiment" within the framework of the present disclosure is meant to indicate that a particular configuration, structure or feature described in relation to the embodiment is included in at least one embodiment. Hence, phrases such as "in one embodiment" which may be present at various points of the present disclosure do not necessarily refer to exactly the same embodiment. Furthermore, particular conformations, structures or features can be combined in any suitable way in one or more embodiments.

The references used here are provided for convenience only and therefore do not define the scope of protection or the scope of the forms of implementation.

Figure 1 shows in general terms a possible context of use of an ultrasound channel indicated as a whole with 100.

This context is fully illustrated in Figure 1, it being understood that all the solutions exemplified in Figures 2 to 5 - presented separately for greater clarity and generality - are likely to be applied (also) in this context.

By way of example, such an ultrasound channel can be included in an apparatus such as an ultrasound system that can be used for example in the medical field: the reference to this possible application is not, however, to be understood in a limiting sense of the embodiments, which are likely to be used, for example, also in ultrasonic equipment of different types such as equipment for the analysis / inspection of materials.

Such an apparatus can comprise, for example, a probe P designed to apply an ultrasound signal to the body of a patient subjected to an ultrasound examination and to receive a corresponding echo signal.

The operation of the apparatus can be coordinated by a processing device C (such as for example a CPU which can be controlled for example through an interface such as a keyboard K).

The device C can, for example, control the operation of a transmission driver 10 by determining the emission of an ultrasonic signal through the probe P and the reception, again through the signal 100, of an echo signal capable of being processed, eg. in the same C drive, with a view to possible display on an S screen or graphics unit.

Without prejudice to what has been said in greater detail below, the general operating criteria of an equipment as previously considered are to be considered known per se, which makes it unnecessary to provide a description in greater detail here: in this regard it will be noted once again that the general context of application exemplified in Figure 1 is generally referable to all the possible implementations of the channel 100 exemplified with reference to the other figures.

As far as is of interest here, it will be sufficient to remember that the channel 100 has the task of electrically stimulating an active element 12 connected to a terminal XDCR (this active element is capable of forming part of the probe P discussed above).

Element 12 may comprise a piezoelectric or capacitive transducer (eg CMUT - acronym for Capacitive Micromachined Ultrasonic Transducer, also known as PMUT).

During the transmission phase, the channel 100 can thus apply to the transducer 12 an ultrasound stimulation signal coming from the driver 10 - a signal which can be a (high) voltage signal, e.g. sinao at 200 volts peak-to-peak - while during the reception phase the channel 100 receives, through the transducer 12 coupled to the XDCR terminal, the echo of the transmitted wave carrying it towards a (low voltage) LVOUT terminal to which a chain is connected reception 14.

The chain in question (exemplified here in the form of a single amplifier) can comprise various stages in cascade (low noise input stage, signal amplification / conditioning stages, analog / digital converter filter) which transfer the received signal to the unit. processing C.

In one or more embodiments there may be a clamp block capable of bringing the output of the driver 10 to a reference voltage, for example with the ground GND, at the end of the transmission phase and constrain the continuous (DC) the during the reception phase.

In one or more embodiments, the block in question, exemplified here in the form of a switch S1, such as for example an electronic switch such as a MOSFET, can be integrated in the driver 10, capable of being made according to the criteria illustrated in an application patent for an invention filed on the same date by the same Applicant.

The presence of a further switch block (called TRSW) can then be provided which can include - by way of example - two switches S2, S3 (also in this case it can be electronic switches such as MOSFETs) capable of operating ( for example under the control of unit C) so that:

- during the transmission phase, the switch indicated with S3 (interposed between the XDCR and LVOUT terminals) is open (non-conductive) so as to protect the reception channel connected to the LVOUT terminal with respect to the (high voltage) signal generated by driver 10 and applied on the XDCR terminal, e

- during the reception phase, switch S3 is closed (i.e. conductive, ideally with zero resistance) and connects the XDCR terminal (on which the echo signal is received, in high voltage) with the reception channel connected to the LVOUT terminal.

As schematically represented in the figures, it is also possible to provide a second switch S2 interposed between the LVOUT terminal and the ground and capable (for example always under the control of unit C) to be closed (i.e. conductive) so as to connect the LVOUT terminal to ground during the transmission phase so as to avoid injections on the reception chain and to be open (i.e. non-conductive) during the reception phase in which the switch S3 is closed and connects the XDCR terminal to the LVOUT terminal.

It is then possible to foresee the presence of two diodes in anti-parallel (i.e. connected in parallel with each other with the anode of one diode connected to the cathode of the other and vice versa) 15 placed between the output of the driver 10 (including the circuit clamp S1) and the XDCR terminal in order to decouple the high parasitic capacitances which may occur in the high voltage circuits during the reception phase.

The operation of equipment such as ultrasound systems of the type described here provides - in the terms already mentioned above - the alternation of transmission and reception phases which can have duty cycle values (i.e. the ratio between the duration of the transmission phase and the of the transmission-reception cycle) also quite low, for example less than 1%.

The possible presence of a spurious and unwanted signal on the XDCR terminal can cause an unwanted transmitted wave whose echo could overlap the received useful signal. It has also been observed that the received signal can have a low and time-dependent voltage value: for the more “distant” echoes the received signal is in fact of lower intensity.

In this situation, even a small glitch on the XDCR terminal can generate artifacts in the processing phase of the received signals: it is therefore desirable that these spurious glitches can have a spectral content at a level of (at least) -40 / -60dB with respect to the transmitted signal.

In a scheme such as the one exemplified in Figure 1, the anti-parallel blocking diodes 15 can allow to mask any signal injections by the driver 10 and the clamp circuit S1 (unless they are lower than the threshold voltage of a diode), without however being able to mask the glitch due to the switching on and off of the other switch block (which may include, in the cases exemplified here, two switches S3 and S2) comprising high voltage components (precisely because they are connected to the XDCR terminal).

Finally, it was observed that a scheme as exemplified in Figure 1 can introduce a drop on the output signal with the possible occurrence of a third harmonic distortion, for example in the case in which the driver 10 is a linear driver (such as this can be done in the case of more sophisticated equipment).

This problem can be tackled as schematically represented in Figure 2, that is by eliminating the blocking diodes 15 and assigning the clamp function to ground directly to the switches S3 and S2, e.g. associating to the driver 10 circuits capable of decoupling the parasitic capacitances of the output stage during the reception phase.

Such a solution can lead to a saving in terms of area (linked to the elimination of the antiparallel diodes 15) allowing to reduce and virtually eliminate the phenomena of drop and distortion of the output signal. However, the achievement of this result can be linked to more critical specifications on the glitch, since the output stage of the driver 10 insists directly on the XDCR output terminal, so any spikes due to the switching on / off of the block with switches S3 and S2 they can be injected directly onto the transducer.

One or more embodiments can provide (for example in the context of an ultrasonic channel 100 capable of being used in a general context as exemplified in Figure 1) the use of the scheme exemplified in Figure 3 where, in series with the XDCR output (i.e. with the ability to be crossed by the signal sent to the transducer and by the signal received starting from the transducer 12), a block 16 is inserted.

In one or more embodiments, block 16, hereinafter referred to as an "active diode" block, can be selectively switched (for example according to the methods discussed below) between:

- a first condition or state of operation (usable in the ultrasonic signal transmission and reception phase), in which - as shown in Figure 4 - block 16 essentially behaves as a resistance R16 of reduced value (for example hundreds of milliOhm) with a correspondingly reduced parasitic capacitance (e.g. some pF), e

- a second condition or state of operation (usable in the passage between the transmission phases and the reception phases of the ultrasound signal, which alternate over time), in which - as shown in Figure 5 - block 16 behaves as a pair of diodes D16 coupled with opposite polarity (for example in anti-parallel as schematized in Figure 5 or, possibly, also in series with each other - that is with the cathodes or the anodes mutually coupled).

One or more embodiments allow to mask the phenomena of injection of spurious signals starting from the other stages of the channel (ie to the driver 10, to the switch S1, to the switches S2, S3) with respect to the XDCR terminal connected to the transducer.

One or more embodiments thus make it possible to reduce (and virtually eliminate) the glitch during the passages (in both directions) between the transmission and reception phases.

It has been verified that one or more embodiments introduce a very low level of distortion (less than -50dB), such as not to have negative effects on the quality of the received signal (for example in terms of image resulting from its processing).

An "active diode" block such as block 16 exemplified here can be implemented, in one or more embodiments, in various different ways, for example by generally resorting to switches which in the first condition or operating state (Figure 4 ) interpose in the signal propagation path a resistance R16 and in the second condition or operating state (Figure 5) interpose in the signal path two diodes D16 in complementary configuration (for example in antiparallel).

Figures 6 and 7 exemplify possible circuit implementations of the block 16 according to one or more embodiments capable of realizing the operating criteria described above by means of simple driving circuits.

Figure 6 exemplifies an embodiment in which the use of two transistors 161, 162 (for example field effect transistors such as MOSFET transistors) with complementary polarity, for example NMOS and PMOS arranged in a back-to-back connection ( back-to-back), i.e. with the respective current paths (source-drain, in the case of field effect transistors) arranged in parallel between the terminals 16a, 16b of block 16.

As can be seen in Figures 3 to 5, the terminals 16a, 16b can be connected, respectively, to the driver 10 / switch S1 and to the XDCR terminal, therefore to the transducer 12.

In one or more embodiments as exemplified in Figure 6, with the aforementioned complementary transistors 161, 162 (for example at low voltage) they can be connected with a common source, drain and body and with the respective driving terminals ( gate, in the case of field effect transistors) coupled to driving circuits DC1, DC2, capable of acting, for example, under the control of unit C.

The aforesaid control circuits, indicated with DC1, DC2, can be realized as described in a patent application for industrial invention filed on the same date by the same Applicant.

In one or more embodiments as exemplified in Figure 6, the body or body of the two transistors 161, 162 can be biased through a resistor R connected to the respective current source terminals (source, in the case of field effect transistors) and capable of being selected with a value (much) higher than the resistance value Ron of the two transistors 161, 162, which can be chosen so as to have substantially corresponding resistance values Ron.

In one or more embodiments, during the transmission and reception phase (in which, as exemplified in Figure 4, it is desired that block 16 behaves essentially as a resistor R16) the two transistors 161, 162 are "turned on" by driver circuits DC1, DC2, eg. making sure that

VG_nmos> XDCR + VTH and VG_pmos <XDCR-VTH,

where

- VG_nmos and VG_pmos indicate the voltages applied to the gates of transistors 161, 162,

- XDCR represents the voltage on the homologous terminal, e

- VTH is the threshold voltage.

Under these conditions, block 16 can realize between terminals 16a, 16b a resistive (continuous) signal path R16 with a resistance value given by the parallel of the resistances Ron of the two transistors, namely Ron_nmos and Ron_pmos.

In alternating mode, during the reception phase, the gate-source capacitances of the transistors 161, 162 keep the two transistors on with constant VGS and block 16 does not introduce effects on the received signal.

In alternating mode, during the transmission phase, the topology exemplified in Figure 6 allows to always have at least one of the two transistors that tends to turn on. In particular, in the presence of increasing signals, the PMOS transistor can be turned on, while during the falling edges the NMOS transistor can be turned on.

The insertion of the resistance indicated with R allows to make unfavorable the current path through the well-diodes indicated with 161a, 162a) and to use the body effect of the MOS transistors.

It will be appreciated that, in one or more embodiments (by intervening on the characteristics of the driving circuits DC1, DC2), it is possible to choose to keep both transistors 161, 162 switched on or to use them alternatively.

In one or more embodiments, during the transients from transmission to reception and vice versa, the circuits DC1, DC2 can intervene by switching off, that is, interdicting the two transistors 161, 162 (for example with VG_nmos <XDCR + VTH and VG_pmos> XDCR-VTH , where the aforementioned quantities have the meaning already recalled above) so that between the two terminals 16a, 16b the two diodes 161a, 162a are "seen" in anti-parallel (with a high value resistance in series such as the resistance R).

In this way it is possible to mask glitch phenomena, with the possible exception of those higher than the threshold voltage of the diodes, which can also be traced back to a malfunction of the system.

In one or more embodiments, block 16 can be implemented according to the scheme exemplified in Figure 7, where parts and elements already described in relation to Figure 6 are indicated with the same references that already appear in Figure 6: the relative description will therefore not be repeated here.

One or more embodiments as exemplified in Figure 7 can provide that the transistors 161, 162 (also here, for example, two MOSFET transistors) are of the same type (for example two NMOS transistors) with the advantage of being able to use the same component type.

In one or more embodiments as exemplified in Figure 7, without prejudice to the general parallel connection of the current paths (for example source-drain, in the case of field effect transistors) between the terminals 16a, 16b (therefore with for example source and drain in common), it is possible to provide that the two transistors 161 have their respective bodies and bodies connected by means of a resistance R respectively to the terminal 16a and to the terminal 16b or, in the case of both transistors, to the terminal 16a, 16b which is also connected to the current source terminal (source, in the case of a field effect transistor) of the transistor itself.

This with the respective pocket diodes 161a, 162a capable of being interposed between the body and the current drain terminal (drain, in the case of a field effect transistor) of the respective transistor 161, 162.

Once again, in one or more embodiments as exemplified in Figure 7, during the transmission and reception phase (Figure 4) the two transistors 161, 162 can be turned on (i.e. made conductive) by the circuits DC1, DC2 by making that the block 16 behaves in continuous as a resistive path R16 between the terminals 16a, 16b with a resistance value given by the parallel of the Ron resistances of the two transistors 161 (with the resistances R which once again make it possible to make the path of the current through the pocket diodes 161a, 162a).

During the transients from transmission to reception and vice versa (Figure 5) the two transistors 161, 162 can be turned off and by doing so, between the two terminals 16a, 16b of the block, the diodes 161a, 162a will once again be seen in anti-parallel with in series a "large" resistance value R.

In one or more embodiments, the advantage offered by the solution exemplified in Figure 7 of having a single type of component can be accompanied by the need to provide more articulated driving circuits DC1, DC2. This is mainly to take into account the fact that during the transmission phase unsymmetrical gate-source voltage modulations (VGS) could arise between the falling and rising edges of the signal which can be associated with a certain level of second harmonic distortion.

One or more embodiments may therefore relate to a circuit (e.g. 16) having a first (16a) and a second (16b) terminal and comprising, between the first (16a) and the second (16b) terminal:

- a resistive signal path (see for example R16 in Figure 4),

- a diode signal path (see e.g. D16 in Figure 5) comprising a pair of diodes with opposite polarity (e.g. 161a, 162a in Figures 6 and 7), and

- switch means (see for example transistors 161, 162) coupled with said resistive signal path and said diode signal path, switchable between a first state and a second state, in which:

- i) in the first state, said first and second terminals are coupled to each other through said resistive signal path (R16 - Figure 4), and

- ii) in the second state, said first and second terminals are coupled to each other through said diode signal path (D16 - Figure 5).

In one or more embodiments, said diode signal path can comprise a pair of diodes (e.g.

161a, 162a) in anti-parallel arrangement.

One or more embodiments can comprise a first (e.g. 161) and a second (e.g. 162) transistor arranged with their current paths (e.g. sourcedrain, in the case of FET) in parallel with each other. first and second terminals, in which said resistive signal path comprises the parallel connection of the Ron resistances of the current paths of said transistors.

In one or more embodiments, said switch means can comprise said first and second transistors which can be switched on or off in said first state and in said second state.

In one or more embodiments, said transistors can comprise field effect transistors and said diode signal path comprises the well diodes of said field effect transistors.

In one or more embodiments, said field effect transistors can have opposite polarities (N-MOA, P-MOS) with bodies in common, optionally with a resistor (e.g. R) between the sources and bodies of said field effect transistors.

In one or more embodiments, said field effect transistors can have the same polarity (e.g. NMOS) with separate sources and common drains and bodies, optionally with a resistor (e.g. R) between the sources and bodies of said transistors.

One or more embodiments may relate to an ultrasound equipment with a transducer terminal (e.g. XDCR) which can be coupled to an ultrasonic transducer device (e.g. 12) capable of converting an electrical driving signal into an ultrasonic transmission signal and converting an ultrasonic receiving signal into an electrical receiving signal, wherein the ultrasonic apparatus may comprise:

- a driving device (driver 10, e.g. linear) which can be activated to generate said electrical driving signal during a transmission phase,

- a reception chain (e.g. 14) for receiving said electric reception signal during a reception phase,

- a switching circuit (e.g. S1, S2, S3) for coupling said transducer terminal respectively to said driving device and to said reception chain during alternate transmission and reception phases, and

- a circuit according to one or more embodiments, interposed between said transducer terminal and said switching circuit with said switchable switching means (e.g. DC1, DC2, C) in said first state during said transmission and reception phases and in said second state during the transitions between said alternate transmission and reception phases.

One or more embodiments may comprise a noise blocking stage (e.g. 15) comprising diodes with opposite polarity interposed between said driving device and said circuit.

In one or more embodiments, said switching circuit can comprise at least one of:

- a first switch (e.g. S1) coupled to said driving device and which can be activated to block (clamp) the output of the driving device to a reference level (e.g. GND) during said transmission phases,

- a second switch (e.g. S3) which can be activated to couple said transducer terminal to said reception chain during said reception phases and to decouple said transducer terminal from said reception chain during said transmission phases, and - a third switch (eg S2) which can be activated to block (clamp) the input of said reception chain at a reference level during said transmission phases.

An operating procedure of an ultrasound equipment according to one or more embodiments may include:

- coupling to said transducer terminal an ultrasonic transducer device capable of converting an electrical driving signal into an ultrasonic transmission signal and converting an ultrasonic reception signal into an electric reception signal,

- controlling said driving device, said reception chain and said switching circuit in a sequence of said alternate transmission and reception phases by switching said switch means synchronously with said alternate transmission and reception phases bringing said switch means in said first state during said alternate transmission and reception phases and in said second state during the transitions between said alternate transmission and reception phases.

Without prejudice to the basic principles, the construction details and the embodiments may vary, even significantly, with respect to what is illustrated here purely by way of non-limiting example, without thereby departing from the scope of protection.

This scope of protection is defined by the attached claims.

Claims (11)

CLAIMS 1. Circuit (16) having a first (16a) and a second (16b) terminal and comprising, between the first (16a) and the second (16b) terminal: - a resistive signal path (R16), - a diode signal path (D16) comprising a pair of diodes with opposite polarity (161a, 162a), and - switch means (161, 162) coupled with said resistive signal path and said diode signal path, switchable between a first state and a second state, in which: - i) in the first state, said first (16a) and second (16b) terminals are coupled to each other through said resistive signal path (R16), and - ii) in the second state, said first (16a) and second (16b) terminals are coupled to each other through said diode signal path (D16). A circuit according to claim 1, wherein said diode signal path comprises a pair of diodes (161a, 162a) in an anti-parallel arrangement. 3. Circuit according to claim 1 or claim 2, comprising a first (161) and a second (162) transistor arranged with their current paths in parallel with each other between said first (16a) and second (16b) terminals, in wherein said resistive signal path comprises the parallel connection of the Ron resistances of the current paths of said transistors (161, 4. A circuit according to claim 3, wherein said switch means comprise said first (161) and second (162) transistors capable of being switched on or off in said first state and in said second state. 5. Circuit according to claim 3 or claim 4, wherein said transistors (161, 162) comprise field effect transistors and said diode signal path comprises the well diodes (-161a, 162a) of said transistors field effect. 6. Circuit according to claim 5, wherein said field effect transistors (161, 162) have opposite polarity with bodies in common, preferably with a resistor (R) between the sources and the bodies of said field effect transistors ( 161, 162). 7. Circuit according to claim 5, wherein said field effect transistors (161, 162) have the same polarity with separate sources and common drains and bodies, preferably with a resistor (R) between the sources and bodies of said transistors . 8. Ultrasonic apparatus with a transducer terminal (XDCR) which can be coupled to an ultrasonic transducer device (12) capable of converting an electrical driving signal into an ultrasonic transmission signal and converting an ultrasonic receiving signal into an electrical signal of reception, where the ultrasound equipment includes: - a driving device (10) which can be activated to generate said electrical driving signal during a transmission phase, - a reception chain (14) for receiving said electric reception signal during a reception phase, - a switching circuit (S1, S2, S3) for coupling said transducer terminal (XDCR) respectively to said driving device (10) and to said receiving chain (14) during alternate transmission and reception phases, and - a circuit (16) according to any one of claims 1 to 7, interposed between said transducer terminal (XDCR) and said switching circuit (S1, S2, S3) with said switching means (161, 162) switchable (DC1, DC2, C) in said first state during said alternate transmission and reception phases and in said second state during the transitions between said alternate transmission and reception phases. Ultrasound apparatus according to claim 8, comprising a noise blocking stage (15) comprising diodes with opposite polarity interposed between said driving device (10) and said circuit (16). 10. Ultrasonic apparatus according to claim 8 or claim 9, wherein said switching circuit (S1, S2, S3) comprises at least one of: - a first switch (S1) coupled to said driving device (10) and which can be activated to block (clamp) the output of the driving device (10) at a reference level (GND) during said transmission phases, - a second switch (S3) which can be activated to couple said transducer terminal (XDCR) to said reception chain (14) during said reception phases and to decouple said transducer terminal (XDCR) from said reception chain (14) during said transmission phases , And - a third switch (S2) which can be activated to block (clamp) the input of said reception chain (14) at a reference level (GND) during said transmission phases. 11. Method of operation of an ultrasound equipment according to any one of claims 8 to 10, the method comprising: - coupling to said transducer terminal (XDCR) an ultrasonic transducer device (12) capable of converting an electrical driving signal into an ultrasonic transmission signal and converting an ultrasonic receiving signal into an electrical receiving signal, - controlling (C) said driving device (10), said reception chain (14) and said switching circuit (S1, S2, S3) in a sequence of said alternating transmission and reception phases by switching (DC1, DC2) said switch means (161, 162) synchronously with said alternate transmission and reception phases bringing said switch means (161, 162) into said first state during said transmission and reception phases and in said second state during the transitions between said alternate transmission and reception phases.