IT201600082302A1 - ANTI-FUSE CELL, CIRCUIT, ELECTRONIC DEVICE AND CORRESPONDENT PROCEDURE - Google Patents

Description

"Corresponding anti-fuse cell, circuit, electronic device and procedure"

TEXT OF THE DESCRIPTION

Technical field

The description refers to the anti-fuse (antifuse) circuits.

One or more embodiments can find application in the realization of semiconductor circuits, such as for example integrated circuits (IC).

Technological background

The name anti-fuse (antifuse) is used to indicate an electrical circuit which behaves opposite or complementary to that of a fuse.

A fuse is a component that demonstrates low resistance (thus essentially behaving like a short circuit) and e.g. when the current flowing through it reaches a certain tripping threshold, it "opens" or "burns" and demonstrates a high resistance (thus essentially behaving like an open circuit, interrupting the flow of current).

Conversely, an anti-fuse demonstrates high resistance (thus essentially behaving like an open circuit) and, following an activation event, e.g. when the voltage at its ends reaches a certain breaking threshold, a conductive path (with low resistance) is created in the anti-fuse, so that the anti-fuse changes to behave like a conductive line.

At the base of the activation event can be a phenomenon of dielectric breakage. Such a phenomenon occurs when a dielectric material subjected to a sufficiently high electric field ceases to be insulating. In solids, the dielectric breakdown is due to an electrostatic discharge due to the overcoming of the stiffness of the dielectric.

The antifuse can comprise a thin barrier of a dielectric material between two metal conductors (in practice a capacitor): when a sufficiently high voltage is applied between these conductors, the dielectric layer can transform into a low resistance material, therefore conductive.

A possible field of application of anti-fuses is represented by the (permanent) programming of semiconductor circuits, eg. integrated circuits such as memories. For example, some programmable logic circuits such as ASICs may use antifuse technology to configure logic circuits. A possible field of application of anti-fuses is represented by non-volatile memories (Non-Volatile Memory or NVM) eg. in devices of the type called System-on-Chip (SoC).

Despite the extensive activity of innovation and research in the sector, the need is still felt to have improved anti-fuse solutions in terms of silicon area occupied, reliability, operating temperature range. For example, in application sectors such as the vehicle sector, a factor to be taken into account in the implementations of cell anti-fuses can be given by the fact that, during programming, the cells not intended to be programmed can in any case be subjected to a electric field of a certain importance (for example equal to half of the nominal electric field), being therefore stressed.

This can be a risk from the point of view of reliability: the inhibition times can be longer than the single programming, so the risk of unwanted programming in defective anti-fuse cells can arise.

Purpose and summary

One or more embodiments have the purpose of helping to satisfy the need outlined above.

According to one or more embodiments, this object can be achieved thanks to an anti-fuse cell having the characteristics referred to in the following claims.

One or more embodiments may also relate to a corresponding circuit as well as a corresponding electronic device (for example a semiconductor device incorporating a non-volatile memory, for example for a SoC component) and a corresponding method of use.

The claims form an integral part of the technical teaching given here in relation to the embodiments.

One or more embodiments allow to realize an anti-fuse cell, comprising an anti-fuse capacitor, a pull-up transistor, e.g. pMOS, and a "shoot transistor", eg. nMOS.

One or more embodiments can propose a cell matrix organization, complete with relative programming and reading schemes.

Brief description of the figures

One or more embodiments will now be described, purely by way of non-limiting example, with reference to the attached figures, in which:

- figure 1 is a schematic diagram of an anti-fuse cell,

Figure 2 is a diagram of anti-fuse cells according to one or more embodiments,

- Figures 3 and 4 illustrate possible solutions in which a cell as presented in Figure 2 is comprised in a cell structure presented respectively in programming condition (Figure 3) and in reading condition (Figure 4),

Figure 5 exemplifies a possible circuit implementation of the diagram of Figure 2, and - Figure 6 is an exemplary block diagram of a semiconductor device such as an SoC system.

Detailed description

Various specific details are illustrated in the following description, in order to provide an in-depth understanding of various examples of embodiments according to the description. The embodiments can be obtained without one or more of the specific details, or with other processes, components, materials, etc. In other cases, known structures, materials or operations are not illustrated or described in detail so that the various aspects of the embodiments will not be made unclear.

A reference to "an embodiment" within the framework of the present disclosure is meant to indicate that a particular configuration, structure or feature described in relation to the embodiment is included in at least one embodiment. Thus, phrases such as "in one embodiment" which may be present at various points of the present disclosure do not necessarily refer to exactly the same embodiment. Furthermore, particular conformations, structures or features can be combined in any suitable way in one or more embodiments.

The references used herein are provided merely for convenience and therefore do not define the scope or scope of the embodiments.

Various integrated anti-fuse circuit solutions have been available on the market for some time, for example in CMOS technology or similar.

Such solutions can use, for example, the hard-breakdown principle of a thin gate oxide, with the breaking capable of intervening in the presence of an electric field of sufficient intensity applied for a certain time (so-called programming time) .

The rupture of a gate oxide can be permanent since a conductive filament is formed within that gate oxide. The main block of an anti-fuse circuit can therefore be represented in the initial state by a capacitor with a thin gate oxide, i.e. an open circuit, which in the final state, after programming, has the resistance of a conductive filament, i.e. a closed circuit.

There are various ways to make a single anti-fuse cell and various ways to organize such a cell in a matrix in order to reduce the occupied silicon area.

Various anti-fuse circuit solutions are known from documents such as e.g. US 6667 902 B2 or US 7402 855 B2.

Figure 1 exemplifies an anti-fuse circuit solution implemented at the Applicant company.

This solution may include:

- an antifuse capacitor 10 (for example pMOS) with thin gate oxide (for example 35 A, 35xlO <~ 10> m),

a resistor 12 (for example of polysilicon) connected in parallel to the antifuse capacitor 10, and two transistors 14 and 16 (for example high voltage DRIFT-MOS transistors, available in BCD technologies) respectively with the function of shooting transistor and of reading transistor.

When both transistors 14 and 16 are off (i.e. non-conductive) a null electric field is applied to the ends of the anti-fuse capacitor 10: no current flows in the resistor 12 in parallel, which determines an applied voltage equal to 0 V.

The selection of an anti-fuse cell such as the one shown in Figure 1 for programming purposes (i.e. to replace the capacitor 10 with a path with low ohmic resistance) may involve activating (i.e. turning on, i.e. making conductive ) the shooting transistor 14, e.g.

applying a corresponding voltage Vshootal gate of the transistor 14. In this way, it is possible to bring the terminal of the capacitor 10 facing the transistor 14 to a ground value (0 V) while the opposite terminal remains at a voltage level VPROG. In this way it is possible to induce a strong electric field across the capacitor 10 and cause the gate oxide to "break" in a short time.

The reading operation instead provides that the firing transistor 14 is turned off while the reading transistor 16 is turned on (ie made conductive), optionally lowering the supply voltage so as not to produce unwanted programming.

The data can thus be read by reading the reading current Iread which passes through the selected anti-fuse cell.

A solution as exemplified in Figure 1 may prove to be such as not to facilitate a matrix organization, nor to program two or more bits in parallel.

One or more embodiments as exemplified in Figure 2 can provide for combining a capacitor (for example pMOS) 10 with thin gate oxide (for example 35 A, i.e. 35 x 10 <~ 10> m) a pair of transistors with oxide of thick gate (e.g. 120 A, i.e. 120xl0 <~ 10m>), e.g. a pMOS transistor 21 and an nMOS transistor 22 with the capacitor 10 arranged between the source and the drain of the transistor 21 acting as a pull-up transistor and the transistor 22 acting as a firing transistor arranged with its current path (source-drain ) in cascade to the current path (source-drain) of transistor 21.

A cell as exemplified in Figure 2 can be included in a set of antifuse cells organized in a matrix way (see for example Figures 3 and 4) in which:

- the source terminal of the pull-up transistors 21 (VNW in Figure 2) is coupled to a line of the programming voltage VPROG,

- the gate terminals of the pull-up transistors (e.g. pMOS) 21 are connected to a single terminal Pup (not presented as such in Figures 3 and 4 to avoid overloading the graphical representation), and

- the gate terminals of the transistors 22 (e.g. nMOS) are coupled by columns or words Wnl, Wn2, ..., Wnx, and the source terminals of the same transistors are coupled by rows BL1, BL2, ..., BLx .

Figures 3 and 4 refer for simplicity to a 2x2 matrix comprising four cells CELL (0,0), CELL (0,1), CELL (1,0), CELL (1,1) organized in two columns (words) of two cells each.

This representation is made for simplicity of presentation but is clearly extendable to matrices of (even much) higher rank, it being understood that, in general:

the control electrodes, i.e. the gates, of the firing transistors 22 are coupled with a plurality of first electrical lines (e.g. columns) Wn1, Wn2, ..., Wnx, and

the current paths (for example the sources) of the firing transistors 22 are coupled with a plurality of second electric lines (for example lines) BL1, BL2, ..., BLx.

In this way, each firing transistor 22 is interposed (from the electrical point of view) between one of said first lines Wn1, Wn2, Wnx and one of said second lines BL1, BL2, BLx, with these lines jointly forming a pair of electrical lines such as to uniquely identify this transistor and therefore the cell in which it is included.

It is thus possible to create a matrix type structure in which each cell of the matrix comprises:

- a capacitor 10 (e.g. pMOS) with thin gate oxide connected in parallel to a first (pull-up, e.g. pMOS) transistor 21, and

- a second (firing, for example nMOS) transistor 22 whose source-drain current path is arranged in series with the source-drain current path of the pull-up transistor 21.

All this with the sources and the pull-up transistors 21 connected, respectively, to the voltage VPROG and to the pull-up voltage Pup.

The organization in rows and columns typical of the matrix is therefore mainly carried out at the level of the second transistors 22 (nMOS) each of which has the gate (control electrode) connected to a respective column Wnl, Wn2, ...., Wnx of the matrix and the source (current path) connected to a respective row BL1, BL2, .... BLx of the matrix itself.

If you want to consider - purely by way of example - the programming by writing the cell CELL (0,0) at the top left (it is assumed that the other cells are not programmed), you can think of selecting the first "word" WN1 applying to it, as schematically indicated in Figure 3, a voltage of 8 V (which is applied to the gates of transistors 22) while the other columns, represented in the simplified example proposed here by the other column Wn2, on the right in Figure 3 , are not selected, so that the gates of the relative transistors 22, connected to the column Wn2, remain at a voltage of 0 V.

Desiring to select the upper left cell, (therefore at the intersection between the column Wnl on the left brought to 8 V - and the first row BL1 of the matrix) the first row BL1 can be selected by applying (e.g. to the sources of transistors 22 connected to this line) a voltage equal to 0 V while the other rows (in the present simplified case of a 2x2 matrix, the second row BL2) can be kept floating.

The pull-up transistors 21 can be turned on, e.g. driving them in current, which means that, for example. each transistor 21 can force a current of e.g. 1-10 μΑ, i.e. 1-10 * 10 <~ 6> A.

In this way, the cell CELL (0,0) at the top left (taken as an example of the cell to be selected) will be the only one to have both transistors 21 and 22 on, ie conductive.

With the methods illustrated above, the transistor 22 can be driven in such a way as to have a higher conductivity than the transistor 21, so that the drain terminal (common to the two transistors) will reach a voltage substantially corresponding to the voltage applied to the line BL1 , that is, for example 0 V.

At this point, a voltage (in practice equal to the programming voltage VPROG) is determined at the ends of the capacitor 10 included in the cell in question, capable of giving rise to an electric field which, applied to the thin gate oxide of the capacitor 10, it determines (in a short time) its rupture.

Once the oxide has broken, a current will be able to pass through the capacitor 10 with the drain terminal common to the two transistors 21 and 22 capable of reaching an intermediate value between the voltage VPROG and the voltage applied to the line BL1 ( at 0 V).

In the other cells of the matrix the (other) capacitors 10 will not be stressed by an electric field: in fact, the transistors 22 (except that of the selected cell, top left) are deactivated and each associated pull-up transistor 21 carries the drain interposed between the two transistors at a voltage substantially equal to the voltage VPROG so that the voltage jump across the associated capacitor 10 is practically zero.

In particular, it will be noted that, in the operating modes exemplified here, the transistor 22 in the upper right cell is off (i.e. not conductive) since its gate-source voltage is practically equal to 0 V. The two transistors 22 in the cells at the bottom they are also inactive since the terminal BL to which the respective sources refer is floating.

One or more embodiments as exemplified here allow to program two or more anti-fuse cells of the same word as a function of how the terminal BL1, BL2, ... associated with them is polarized. In this way it is possible to reduce the programming times of an anti-fuse compartment.

The selection of the cell to be read can be done in the same way as the programming described above.

During the reading, the supply voltage of the matrix can be lowered (for example by passing through VPROG equal for example to 8 V to VPROG equal to about 1.8 V) with the pull-up transistors 21 capable of being switched off by acting on the respective Pup terminal.

For example, the data can be read by reading the current that passes through the selected anti-fuse cell (for simplicity, always think of the cell at the top left in figure 4) also exploiting the matrix parallelism.

This is also in consideration of the fact that - in the cell in which, during programming, the voltage that produced the break was applied to the gate oxide of the capacitor 10 - the capacitor 10 acts in practice as a short circuit at the ends (source drain) of the respective pull-up transistor 21.

The diagram of Figure 5 illustrates the possible implementation of an addressing mechanism for the single cell within a matrix scheme of the type exemplified above.

In particular, references 121 and 122 indicate two electronic switches (for example MOSFETs) capable of driving the gates of transistors 21 and 22 bringing them to voltage levels such as (with reference to the values indicated above) values equal to 8 V or 1.8 V.

Reference 123, on the other hand, indicates a further electronic switch (also in this case it can be nMOSFET) which allows to perform the function of selecting the line BL1, BL2, ... bringing the source of transistor 22 to ground level (0 V , selected row) or by keeping it floating.

In the lower part of Figure 5 there is then visible a set of circuits that can be used for reading such as for example a latch 124 (possibly preceded by a logic inverter 125) capable of "feeling" the logic level present on the source of the MOSFET 123 (for example "low" for a virgin cell, in which the oxide of the capacitor 10 has not yet been made conductive, and "high" in the case of a cell in which the oxide of the capacitor 10 has already been perforated).

References 126, 127 and 128 indicate three transistors (CMOS) coupled in a scheme substantially similar to a current mirror intended to selectively couple the source of transistor 126 to a reading current source I_read 129 as a function of the logic level applied on the gate of transistor 128.

The dashed representation in Figure 2 exemplifies the possibility that the capacitor 10 with anti-fuse function can be, so to speak, "split" into two capacitors by optionally coupling them in parallel (i.e. with identical voltage across the ends) an additional capacitor indicated with 10a capable of presenting the same general characteristics of the capacitor 10 and the characteristics exemplified in greater detail below.

One or more embodiments can adopt this solution while retaining the characteristics (e.g. matrix organization) of the embodiments discussed above. In other words, in one or more embodiments, the modifications exemplified with broken lines in Figure 2 can only concern the anti-fuse capacitor 10, 10a included in each single cell (bit-cell), with the transistors 21 (e.g. . pMOS) and 22 (e.g. nMOS) that are not changed.

In one or more embodiments, a first anti-fuse capacitor 10, capable of having a thin gate oxide (e.g. 35 Angstrom; 1 Angstrom = 10 <~ 10> m) can be coupled, as exemplified with broken line in Figure 2, a second anti-fuse capacitor 10a, e.g. connected in parallel, also capable of presenting a thin gate oxide (e.g. 35 Angstrom; 1 Angstrom = 10 <~ 10> m).

In one or more embodiments, the two capacitors 10 and 10a can have a gate poly-silicon with the same type of doping, e.g. type P +.

In one or more embodiments, the two capacitors 10 and 10a can have different doping of the body, with the first capacitor 10 having a doped body e.g. of NW, that is of type N; while the second capacitor 10a has a PW body, therefore of type P.

For example, in one or more embodiments, the two capacitors 10, 10a connected in parallel can have the following gate stack structure: P + poly / 35A / NW and P + poly / 35A / PW, respectively.

In one or more embodiments, the presence of the two capacitors 10, 10a facilitates the improvement of programming and reading performance, without appreciably increasing the area occupied by the single cell on silica in one or more embodiments, during operations. programming and reading (which can be carried out as exemplified above) it is possible to apply to both capacitors 10, 10 at the same voltages, and the same electrical stresses, if the capacitors are connected in parallel as illustrated in dashed line in the Figure 2.

In one or more embodiments, the second capacitor 10a can be more easily programmable than the first capacitor 10 since, at the same applied voltage, a higher electric field can be applied across the gate oxide.

In one or more embodiments, the achievement of this result can be facilitated by the gate stack structure of the second capacitor 10a as exemplified above.

In one or more embodiments, during programming, the first capacitor 10 may be working in an inversion region while the second capacitor 10a may be working in an accumulation region.

For example (of course, the values shown below are purely indicative and not limiting), considering as an example a programming pulse VPR0G of 8V, the ECAPIn electric field in the first capacitor 10 results:

ECAPI = (VPR0G-VTH) / tox = (8V- 0, 6V) / 35A = 21 MV / cm; where VTHe tox indicate respectively the threshold voltage of the MOS capacitor (P + poly / 35A / PW) and the thickness of the gate oxide (e.g. 35A), while the ECAP2 electric field in the second capacitor is:

ECAP 2 <=> VPRGG / tox = 8V / 35A = 23 MV / cm.

The second MOS capacitor can therefore have a zero threshold voltage in the working region of the application considered here.

It has been observed that programming performance can depend exponentially on the electric field applied across the anti-fuse capacitor.

For this reason, an increase such as the one exemplified here, equal to about 10% of the electric field at the same applied voltage, can facilitate the consequent performance improvements, eg. in terms of programming time and oxide "firing" current.

The reading current can also increase for the same reason, whereby one or more embodiments as exemplified in broken lines in Figure 2 can also lead to advantages in terms of a more robust reading, capable of better discriminating a fired anti-fuse. from one inteqro.

In one or more embodiments as exemplified herein, an anti-fuse cell can therefore comprise:

- an anti-fuse capacitor (e.g. 10) which can be activated or "breakable" - with a breakdown voltage to create an electrically conductive path through the capacitor,

- a pull-up transistor (e.g. 21) coupled to the anti-fuse capacitor with the current path (e.g. source-drain, in the case of field effect transistors or FETs) of the pull-up transistor in parallel with the anti-fuse capacitor, e

- a shooting transistor (shootinq transistor), e.g. 22, coupled to the pull-up transistor with the current paths of the pull-up transistor and the firing transistor in cascade (ie in series) with each other, e.g. with the pull-up transistor facing the power supply line (e.g. VNW) and the shootinq transistor placed between the parallel connection of the pull-up transistor and the anti-fuse capacitor and ground,

an additional anti-fuse capacitor (eg.

10a), said an anti-fuse capacitor and said further anti-fuse capacitor being mutually coupled and activated with a breakdown voltage to provide an electrically conductive path through them, in which said anti-fuse capacitor and said further anti-fuse capacitor including bodies with different doping, type N and type P.

In one or more embodiments, the anti-fuse capacitor and said further anti-fuse capacitor may comprise a dielectric layer which can be broken by means of said breakdown voltage.

In one or more embodiments, the anti-fuse capacitor and said further anti-fuse capacitor may comprise a MOS capacitor with said breakable dielectric layer comprising a gate oxide.

In one or more embodiments, said pull-up transistor and said firing transistor can comprise field effect transistors, e.g. MOS.

In one or more embodiments, said pull-up transistor can comprise a pMOS transistor.

In one or more embodiments, said firing transistor can comprise an nMOS transistor.

One or more forms may provide a circuit comprising a plurality of anti-fuse cells as exemplified here, in which:

- the control electrodes of the pull-up transistors of the cells of said plurality of cells are coupled to a common pull-up line (e.g. Pup),

the firing transistors of the cells of said plurality of cells are coupled in matrix form with:

- the control electrodes (e.g. gate, in the case of field effect transistors or FETs) of the firing transistors coupled with a plurality of first electrical lines (e.g. Wnl, Wn2), and

- the current paths (e.g. the current source electrodes, i.e. source if of sections of field effect transistors or FETs) of the firing transistors coupled with a plurality of second electric lines (BL1, BL2),

whereby each firing transistor is interposed between one of said first electric lines and one of said second electric lines, thus being individually addressable within the matrix scheme.

One or more embodiments may relate to an electronic device (e.g. a memory, such as a non-volatile memory in a SoC component) comprising a circuit as exemplified here.

One or more embodiments may relate to a method of using a circuit as exemplified herein, with the possibility of selectively activating (i.e. making conductive) the firing transistors of the cells of said plurality of cells:

- producing (see for example VPROG, RI, R2, 121, 122 in Figure 5) the activation of the anti-fuse capacitor and of the further anti-fuse capacitor of the respective cell (i.e. of the cell comprising the firing transistor considered) with a voltage applied between one of said first electric lines and one of said second electric lines, and / or

- detecting (see for example 123, 124, 125, 126, 127, 128 in Figure 5) the state (non-conductive / conductive) of the anti-fuse capacitor and of the further anti-fuse capacitor of the respective cell, detecting the current between said one of said first electric lines and said one of said second electric lines with said pull-up transistors of said plurality of cells deactivated.

Figure 6 is an exemplary block diagram of a semiconductor device such as a System-on-Chip or SoC system capable of incorporating one or more embodiments.

It can be, for example, a SoC 40 capable of being mounted on cards or boards 50 intended to be inserted in a final electronic product, not visible in the figures.

By way of example, Figure 6 illustrates a system comprising, according to per se known criteria, the following elements:

- digital input / output 41,

- processor or state machine 42,

- analog module 43,

- non-volatile memory (e.g. ROM, anti-fuse OTP, MTP or FLASH) 44,

- random access memory (RAM) 45,

- power management module 46,

- other peripherals (if any), e

- System BUS 48

One or more embodiments are suitable for example to be used to realize an antifuse OTP memory (block 44 in Figure 6) capable of being compatible e.g. with SoC products for the automotive sector, with the possibility of reducing the silicon area of the final product, thus reducing the cost of the final product.

Without prejudice to the basic principles, the construction details and the embodiments may vary, even significantly, with respect to what is illustrated here purely by way of non-limiting example without thereby departing from the scope of protection.

This scope of protection is defined by the attached claims.

Claims (13)

CLAIMS 1. Anti-fuse cell, comprising: - an anti-fuse capacitor (10) which can be activated with a breakdown voltage to create an electrically conductive path through the capacitor (10), a pull-up transistor (21) coupled to the anti-fuse capacitor (10) with the current of the pull-up transistor (21) in parallel with the anti-fuse capacitor (10), e - a shooting transistor -22 coupled to the pull-up transistor (21) with the current paths of the pull-up transistor (21) and of the shooting transistor (22) in cascade between them, - a further anti-fuse capacitor (10a), said anti-fuse capacitor (10) and said further anti-fuse capacitor (10a) being mutually coupled and activated with a breakdown voltage to create an electrically conductive path through them, in wherein said anti-fuse capacitor (10) and said further anti-fuse capacitor (10a) comprising bodies with different doping, of type N and type P. 2. Anti-fuse cell according to claim 1, wherein said anti-fuse capacitor (10) and said further anti-fuse capacitor (10a) comprise a dielectric layer which can be broken by said breakdown voltage. Anti-fuse cell according to claim 2, wherein said anti-fuse capacitor (10) and said further anti-fuse capacitor (10a) comprise a MOS capacitor with said breakable dielectric layer comprising a gate oxide. 4. Anti-fuse cell according to any one of the preceding claims, wherein said pull-up transistor (21) and said firing transistor (22) comprise field effect transistors, preferably MOS. 5. Anti-fuse cell according to claim 4, wherein said pull-up transistor (21) comprises a pMOS transistor. 6. Anti-fuse cell according to claim 4 or claim 5, wherein said firing transistor (22) comprises an nMOS transistor. 7. Anti-fuse cell according to any one of the preceding claims, wherein said anti-fuse capacitor (10) and said further anti-fuse capacitor (10a) comprise gates with the same doping, preferably of the P type. Anti-fuse cell according to any one of the preceding claims, wherein said anti-fuse capacitor (10) and said further anti-fuse capacitor (10a) comprise identical gate stack structures. Anti-fuse cell according to any one of the preceding claims, wherein said anti-fuse capacitor (10) and said further anti-fuse capacitor (10a) are arranged in parallel to each other. 10. circuit comprising a plurality of antifuse cells according to any one of claims 1 to 9, wherein: - the control electrodes of the pullup transistors (21) of the cells of said plurality of cells are coupled to a common pull-up line (PUP), - the firing transistors (22) of the cells of said plurality of cells are coupled in matrix form with: the control electrodes of the firing transistors (22) coupled with a plurality of first electrical lines (Wn1, Wn2), and - the current paths of the firing transistors (22) coupled with a plurality of second electric lines (BL1, BL2), whereby each firing transistor (22) is interposed between one of said first electric lines (Wnl, Wn2) and one of said second electric lines (BL1, BL2). Electronic device comprising a circuit according to claim 10, preferably as a non-volatile memory component (44). Electronic device according to claim 11, wherein said electronic device comprises a system of the System-on-Chip type (40). A method of using a circuit according to claim 10, the method comprising selectively activating the firing transistors (22) of the cells of said plurality of cells: - producing (VPROG, RI, R2, 121, 122) the activation of the anti-fuse capacitor (10) and of the further anti-fuse capacitor (10a) of the respective cell with a voltage applied between one of said first electric lines ( Wnl, Wn2) and one of said second power lines (BL1, BL2), and / or - detecting (123, 124, 125, 126, 127, 128) the state of the anti-fuse capacitor (10) and of the further anti-fuse capacitor (10a) of the respective cell by detecting the current between said one of said first electric lines (Wn1, Wn2) and said one of said second electric lines (BL1, BL2) with said pull-up transistors (21) of said plurality of cells deactivated.