IT1405457B1 - Framework per la progettazione di circuiti integrati comprendente funzionalita' di analisi automatica - Google Patents

Framework per la progettazione di circuiti integrati comprendente funzionalita' di analisi automatica

Info

Publication number
IT1405457B1
IT1405457B1 ITVI2010A000166A ITVI20100166A IT1405457B1 IT 1405457 B1 IT1405457 B1 IT 1405457B1 IT VI2010A000166 A ITVI2010A000166 A IT VI2010A000166A IT VI20100166 A ITVI20100166 A IT VI20100166A IT 1405457 B1 IT1405457 B1 IT 1405457B1
Authority
IT
Italy
Prior art keywords
framework
design
integrated circuits
circuits including
automatic analysis
Prior art date
Application number
ITVI2010A000166A
Other languages
English (en)
Inventor
Marco Verga
Paolo Cacciagrano
Antonio Bogani
Luciana Paciaroni
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to ITVI2010A000166A priority Critical patent/IT1405457B1/it
Priority to US13/158,656 priority patent/US8458643B2/en
Publication of ITVI20100166A1 publication Critical patent/ITVI20100166A1/it
Application granted granted Critical
Publication of IT1405457B1 publication Critical patent/IT1405457B1/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Manufacture Of Tobacco Products (AREA)
  • Manufacture Of Macromolecular Shaped Articles (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
ITVI2010A000166A 2010-06-11 2010-06-11 Framework per la progettazione di circuiti integrati comprendente funzionalita' di analisi automatica IT1405457B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
ITVI2010A000166A IT1405457B1 (it) 2010-06-11 2010-06-11 Framework per la progettazione di circuiti integrati comprendente funzionalita' di analisi automatica
US13/158,656 US8458643B2 (en) 2010-06-11 2011-06-13 Integrated circuit design framework comprising automatic analysis functionality

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITVI2010A000166A IT1405457B1 (it) 2010-06-11 2010-06-11 Framework per la progettazione di circuiti integrati comprendente funzionalita' di analisi automatica

Publications (2)

Publication Number Publication Date
ITVI20100166A1 ITVI20100166A1 (it) 2011-12-12
IT1405457B1 true IT1405457B1 (it) 2014-01-10

Family

ID=43530379

Family Applications (1)

Application Number Title Priority Date Filing Date
ITVI2010A000166A IT1405457B1 (it) 2010-06-11 2010-06-11 Framework per la progettazione di circuiti integrati comprendente funzionalita' di analisi automatica

Country Status (2)

Country Link
US (1) US8458643B2 (it)
IT (1) IT1405457B1 (it)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8631372B2 (en) 2012-02-10 2014-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. System and method of electromigration mitigation in stacked IC designs
CN103853861B (zh) * 2012-11-30 2016-12-21 国际商业机器公司 评估3d ic的电源供应的方法和装置
US9244453B2 (en) 2013-06-05 2016-01-26 General Electric Company Dynamic wizard execution
US10452793B2 (en) 2014-08-26 2019-10-22 International Business Machines Corporation Multi-dimension variable predictive modeling for analysis acceleration
US10387596B2 (en) * 2014-08-26 2019-08-20 International Business Machines Corporation Multi-dimension variable predictive modeling for yield analysis acceleration
CN107220105A (zh) * 2017-06-22 2017-09-29 中国人民解放军国防科学技术大学 并行离散事件仿真系统自动初始化实现方法
CN112465344B (zh) * 2020-11-26 2023-10-24 中船重工鹏力（南京）智能装备系统有限公司 一种基于车间自动化产线仿真系统参数的初始化方法
CN117150990A (zh) * 2023-09-06 2023-12-01 江苏芯海技术开发有限公司 一种增强的可视化集成电路设计平台

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6574779B2 (en) * 2001-04-12 2003-06-03 International Business Machines Corporation Hierarchical layout method for integrated circuits
US6983434B1 (en) * 2003-02-13 2006-01-03 Hewlett-Packard Development Company, L.P. Differential via pair impedance adjustment tool
US7206731B2 (en) * 2003-06-02 2007-04-17 Agilent Technologies, Inc. Electromagnetic/circuit co-simulation and co-optimization with parametric layout components
US20050055650A1 (en) * 2003-09-05 2005-03-10 Intersil Americas Inc. Automatic layout fill generation
US7617467B2 (en) * 2006-12-14 2009-11-10 Agere Systems Inc. Electrostatic discharge device verification in an integrated circuit
JP2008210983A (ja) * 2007-02-26 2008-09-11 Matsushita Electric Ind Co Ltd 信頼性設計支援方法
US20090031264A1 (en) * 2007-07-24 2009-01-29 Dan Rittman System and method for finding electromigration, self heat and voltage drop violations of an integrated circuit when its design and electrical characterization are incomplete
JP2009282638A (ja) * 2008-05-20 2009-12-03 Nec Electronics Corp レイアウト設計システム、レイアウト設計方法、及びプログラム

Also Published As

Publication number Publication date
US20120079438A1 (en) 2012-03-29
ITVI20100166A1 (it) 2011-12-12
US8458643B2 (en) 2013-06-04

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