IT1402921B1 - Circuito di pilotaggio di una porta d'accesso al test - Google Patents

Circuito di pilotaggio di una porta d'accesso al test

Info

Publication number
IT1402921B1
IT1402921B1 ITMI2010A002265A ITMI20102265A IT1402921B1 IT 1402921 B1 IT1402921 B1 IT 1402921B1 IT MI2010A002265 A ITMI2010A002265 A IT MI2010A002265A IT MI20102265 A ITMI20102265 A IT MI20102265A IT 1402921 B1 IT1402921 B1 IT 1402921B1
Authority
IT
Italy
Prior art keywords
test
access door
pilot circuit
pilot
circuit
Prior art date
Application number
ITMI2010A002265A
Other languages
English (en)
Inventor
Enrico Bruzzano
Antonio Anastasio
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to ITMI2010A002265A priority Critical patent/IT1402921B1/it
Priority to US13/240,163 priority patent/US8892387B2/en
Publication of ITMI20102265A1 publication Critical patent/ITMI20102265A1/it
Application granted granted Critical
Publication of IT1402921B1 publication Critical patent/IT1402921B1/it

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Elevator Door Apparatuses (AREA)
  • Pinball Game Machines (AREA)
ITMI2010A002265A 2010-12-10 2010-12-10 Circuito di pilotaggio di una porta d'accesso al test IT1402921B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
ITMI2010A002265A IT1402921B1 (it) 2010-12-10 2010-12-10 Circuito di pilotaggio di una porta d'accesso al test
US13/240,163 US8892387B2 (en) 2010-12-10 2011-09-22 Driving circuit of a test access port

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI2010A002265A IT1402921B1 (it) 2010-12-10 2010-12-10 Circuito di pilotaggio di una porta d'accesso al test

Publications (2)

Publication Number Publication Date
ITMI20102265A1 ITMI20102265A1 (it) 2012-06-11
IT1402921B1 true IT1402921B1 (it) 2013-09-27

Family

ID=43736921

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI2010A002265A IT1402921B1 (it) 2010-12-10 2010-12-10 Circuito di pilotaggio di una porta d'accesso al test

Country Status (2)

Country Link
US (1) US8892387B2 (it)
IT (1) IT1402921B1 (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7155646B2 (en) * 1999-02-10 2006-12-26 Texas Instruments Incorporated Tap and test controller with separate enable inputs
US7284170B2 (en) * 2004-01-05 2007-10-16 Texas Instruments Incorporated JTAG circuit transferring data between devices on TMS terminals
KR20150064452A (ko) * 2013-12-03 2015-06-11 에스케이하이닉스 주식회사 내장형 셀프 테스트 회로 및 이를 포함한 반도체 장치
US10267850B2 (en) * 2014-12-22 2019-04-23 Intel Corporation Reconfigurable test access port with finite state machine control
US10969455B2 (en) * 2018-10-16 2021-04-06 Rohde & Schwarz Gmbh & Co. Kg Test system and method for testing a device under test having several communication lanes
EP3961229B1 (en) * 2020-08-25 2024-02-28 STMicroelectronics S.r.l. Electronic device and corresponding self-test method

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860290A (en) * 1987-06-02 1989-08-22 Texas Instruments Incorporated Logic circuit having individually testable logic modules
US4862072A (en) * 1988-09-08 1989-08-29 General Electric Company Distributed access serial port test arrangement for integrated circuits
US5737342A (en) * 1996-05-31 1998-04-07 Quantum Corporation Method for in-chip testing of digital circuits of a synchronously sampled data detection channel
JP2001195899A (ja) * 2000-01-06 2001-07-19 Mitsubishi Electric Corp 半導体記憶装置
JP2003100100A (ja) * 2001-07-19 2003-04-04 Mitsubishi Electric Corp 半導体集積回路装置
TW200708750A (en) * 2005-07-22 2007-03-01 Koninkl Philips Electronics Nv Testable integrated circuit, system in package and test instruction set
CN102165328A (zh) * 2008-09-26 2011-08-24 Nxp股份有限公司 用于测试部分地组装的多管芯器件的方法、集成电路管芯和多管芯器件

Also Published As

Publication number Publication date
ITMI20102265A1 (it) 2012-06-11
US8892387B2 (en) 2014-11-18
US20120150477A1 (en) 2012-06-14

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