IT1313393B1 - Metodo e circuito digitale di regolazione ad anello chiuso del dutycycle di un segnale di clock. - Google Patents

Metodo e circuito digitale di regolazione ad anello chiuso del dutycycle di un segnale di clock.

Info

Publication number
IT1313393B1
IT1313393B1 IT1999VA000023A ITVA990023A IT1313393B1 IT 1313393 B1 IT1313393 B1 IT 1313393B1 IT 1999VA000023 A IT1999VA000023 A IT 1999VA000023A IT VA990023 A ITVA990023 A IT VA990023A IT 1313393 B1 IT1313393 B1 IT 1313393B1
Authority
IT
Italy
Prior art keywords
dutycycle
circuit
clock signal
closed ring
regulation method
Prior art date
Application number
IT1999VA000023A
Other languages
English (en)
Inventor
Francesco Cretti
Nuccio Villa
Raffaele Izzo
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT1999VA000023A priority Critical patent/IT1313393B1/it
Publication of ITVA990023A0 publication Critical patent/ITVA990023A0/it
Priority to US09/653,739 priority patent/US6326827B1/en
Publication of ITVA990023A1 publication Critical patent/ITVA990023A1/it
Application granted granted Critical
Publication of IT1313393B1 publication Critical patent/IT1313393B1/it

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Television Signal Processing For Recording (AREA)
IT1999VA000023A 1999-09-03 1999-09-03 Metodo e circuito digitale di regolazione ad anello chiuso del dutycycle di un segnale di clock. IT1313393B1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT1999VA000023A IT1313393B1 (it) 1999-09-03 1999-09-03 Metodo e circuito digitale di regolazione ad anello chiuso del dutycycle di un segnale di clock.
US09/653,739 US6326827B1 (en) 1999-09-03 2000-09-01 Method and a relative digital circuit of feedback regulation of the duty cycle of a clock signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT1999VA000023A IT1313393B1 (it) 1999-09-03 1999-09-03 Metodo e circuito digitale di regolazione ad anello chiuso del dutycycle di un segnale di clock.

Publications (3)

Publication Number Publication Date
ITVA990023A0 ITVA990023A0 (it) 1999-09-03
ITVA990023A1 ITVA990023A1 (it) 2001-03-03
IT1313393B1 true IT1313393B1 (it) 2002-07-23

Family

ID=11423535

Family Applications (1)

Application Number Title Priority Date Filing Date
IT1999VA000023A IT1313393B1 (it) 1999-09-03 1999-09-03 Metodo e circuito digitale di regolazione ad anello chiuso del dutycycle di un segnale di clock.

Country Status (2)

Country Link
US (1) US6326827B1 (it)
IT (1) IT1313393B1 (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6326687B1 (en) 1998-09-01 2001-12-04 Micron Technology, Inc. IC package with dual heat spreaders
US6687844B1 (en) * 2000-09-28 2004-02-03 Intel Corporation Method for correcting clock duty cycle skew by adjusting a delayed clock signal according to measured differences in time intervals between phases of original clock signal
US6518809B1 (en) 2001-08-01 2003-02-11 Cypress Semiconductor Corp. Clock circuit with self correcting duty cycle
US6771136B1 (en) 2001-12-10 2004-08-03 Cypress Semiconductor Corp. System and method for restoring the mark and space ratio of a clocking signal output from an oscillator
DE10214304B4 (de) * 2002-03-28 2004-10-21 Infineon Technologies Ag Verfahren und Vorrichtung zur Erzeugung zweier Signale mit einem vorbestimmten Abstand sich entsprechender Signalflanken zueinander
US6882196B2 (en) * 2002-07-18 2005-04-19 Sun Microsystems, Inc. Duty cycle corrector
US7131034B2 (en) * 2002-11-12 2006-10-31 Sun Microsystems, Inc. On-chip measurement of signal state duration
US7036098B2 (en) * 2003-06-30 2006-04-25 Sun Microsystems, Inc. On-chip signal state duration measurement and adjustment
FR2916288B1 (fr) * 2007-05-18 2009-08-21 Commissariat Energie Atomique Dispositif d'alimentation d'un circuit electronique et circuit electronique

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5926053A (en) * 1995-12-15 1999-07-20 National Semiconductor Corporation Selectable clock generation mode
US5757218A (en) * 1996-03-12 1998-05-26 International Business Machines Corporation Clock signal duty cycle correction circuit and method
US6205191B1 (en) * 1997-07-21 2001-03-20 Rambus Inc. Method and apparatus for synchronizing a control signal

Also Published As

Publication number Publication date
ITVA990023A1 (it) 2001-03-03
ITVA990023A0 (it) 1999-09-03
US6326827B1 (en) 2001-12-04

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