IT1275254B - Sistema informatico che mantiene coerenza di cache per tutto il sistema durante transazioni di comunicazione differite - Google Patents

Sistema informatico che mantiene coerenza di cache per tutto il sistema durante transazioni di comunicazione differite

Info

Publication number
IT1275254B
IT1275254B ITMI950388A ITMI950388A IT1275254B IT 1275254 B IT1275254 B IT 1275254B IT MI950388 A ITMI950388 A IT MI950388A IT MI950388 A ITMI950388 A IT MI950388A IT 1275254 B IT1275254 B IT 1275254B
Authority
IT
Italy
Prior art keywords
maints
cache coherence
communication transactions
entire system
deferred communication
Prior art date
Application number
ITMI950388A
Other languages
English (en)
Inventor
V Sarangdhar Nitin
Han Wang Wen
Michael W Rhodehamel
James M Brayton
Amit Merchant
Matthew A Fisch
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of ITMI950388A0 publication Critical patent/ITMI950388A0/it
Publication of ITMI950388A1 publication Critical patent/ITMI950388A1/it
Application granted granted Critical
Publication of IT1275254B publication Critical patent/IT1275254B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Iron Core Of Rotating Electric Machines (AREA)
ITMI950388A 1994-03-01 1995-03-01 Sistema informatico che mantiene coerenza di cache per tutto il sistema durante transazioni di comunicazione differite IT1275254B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/205,023 US5682516A (en) 1994-03-01 1994-03-01 Computer system that maintains system wide cache coherency during deferred communication transactions

Publications (3)

Publication Number Publication Date
ITMI950388A0 ITMI950388A0 (it) 1995-03-01
ITMI950388A1 ITMI950388A1 (it) 1996-09-01
IT1275254B true IT1275254B (it) 1997-07-31

Family

ID=22760475

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI950388A IT1275254B (it) 1994-03-01 1995-03-01 Sistema informatico che mantiene coerenza di cache per tutto il sistema durante transazioni di comunicazione differite

Country Status (5)

Country Link
US (1) US5682516A (it)
GB (1) GB2287161B (it)
IT (1) IT1275254B (it)
NO (1) NO312610B1 (it)
SG (1) SG47655A1 (it)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5778438A (en) * 1995-12-06 1998-07-07 Intel Corporation Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests
US5673413A (en) * 1995-12-15 1997-09-30 International Business Machines Corporation Method and apparatus for coherency reporting in a multiprocessing system
US5963721A (en) * 1995-12-29 1999-10-05 Texas Instruments Incorporated Microprocessor system with capability for asynchronous bus transactions
WO1997034237A2 (en) * 1996-03-15 1997-09-18 Sun Microsystems, Inc. Split transaction snooping bus and method of arbitration
US5923857A (en) * 1996-09-06 1999-07-13 Intel Corporation Method and apparatus for ordering writeback data transfers on a bus
US5764932A (en) * 1996-12-23 1998-06-09 Intel Corporation Method and apparatus for implementing a dual processing protocol between processors
US5961621A (en) * 1997-03-28 1999-10-05 Intel Corporation Mechanism for efficiently processing deferred order-dependent memory access transactions in a pipelined system
US6292705B1 (en) 1998-09-29 2001-09-18 Conexant Systems, Inc. Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system
US6633945B1 (en) 1997-12-07 2003-10-14 Conexant Systems, Inc. Fully connected cache coherent multiprocessing systems
US6516442B1 (en) 1997-12-07 2003-02-04 Conexant Systems, Inc. Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor system
US6065077A (en) 1997-12-07 2000-05-16 Hotrail, Inc. Apparatus and method for a cache coherent shared memory multiprocessing system
US6418537B1 (en) 1997-12-07 2002-07-09 Conexant Systems, Inc. Accurate timing calibration for each of multiple high-speed clocked receivers using a single DLL
US6292906B1 (en) * 1997-12-17 2001-09-18 Intel Corporation Method and apparatus for detecting and compensating for certain snoop errors in a system with multiple agents having cache memories
US7071946B2 (en) * 1997-12-30 2006-07-04 Micron Technology, Inc. Accelerated graphics port for a multiple memory controller computer system
US6157398A (en) * 1997-12-30 2000-12-05 Micron Technology, Inc. Method of implementing an accelerated graphics port for a multiple memory controller computer system
US6223238B1 (en) 1998-03-31 2001-04-24 Micron Electronics, Inc. Method of peer-to-peer mastering over a computer bus
US6073198A (en) 1998-03-31 2000-06-06 Micron Electronics, Inc. System for peer-to-peer mastering over a computer bus
US6112283A (en) * 1998-08-06 2000-08-29 Intel Corporation Out-of-order snooping for multiprocessor computer systems
JP3676934B2 (ja) * 1998-12-15 2005-07-27 株式会社日立製作所 プロセッサおよびマルチプロセッサシステム
US7555603B1 (en) * 1998-12-16 2009-06-30 Intel Corporation Transaction manager and cache for processing agent
US6469988B1 (en) 1999-07-08 2002-10-22 Conexant Systems, Inc. Low-level circuit implementation of signal flow graphs for real-time signal processing of high-speed digital signals
US6487621B1 (en) 1999-08-17 2002-11-26 Compaq Information Technologies Group, L.P. Architecture, system and method for ensuring an ordered transaction on at least one of a plurality of multi-processor buses that experience a hit-to-modified snoop cycle
US6557048B1 (en) * 1999-11-01 2003-04-29 Advanced Micro Devices, Inc. Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof
US6636914B1 (en) * 1999-11-05 2003-10-21 Apple Computer, Inc. Method and apparatus for arbitration and fairness on a full-duplex bus using dual phases
US6848003B1 (en) * 1999-11-09 2005-01-25 International Business Machines Corporation Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response
US6721813B2 (en) * 2001-01-30 2004-04-13 Advanced Micro Devices, Inc. Computer system implementing a system and method for tracking the progress of posted write transactions
US7127562B2 (en) * 2003-06-11 2006-10-24 International Business Machines Corporation Ensuring orderly forward progress in granting snoop castout requests
US9727468B2 (en) * 2004-09-09 2017-08-08 Intel Corporation Resolving multi-core shared cache access conflicts
US7392353B2 (en) * 2004-12-03 2008-06-24 International Business Machines Corporation Prioritization of out-of-order data transfers on shared data bus
US8949545B2 (en) * 2008-12-04 2015-02-03 Freescale Semiconductor, Inc. Memory interface device and methods thereof
US9477600B2 (en) 2011-08-08 2016-10-25 Arm Limited Apparatus and method for shared cache control including cache lines selectively operable in inclusive or non-inclusive mode
US9411748B2 (en) 2011-12-20 2016-08-09 Intel Corporation Secure replay protected storage
WO2013095387A1 (en) 2011-12-20 2013-06-27 Intel Corporation Secure replay protected storage
US8793442B2 (en) * 2012-02-08 2014-07-29 International Business Machines Corporation Forward progress mechanism for stores in the presence of load contention in a system favoring loads
US10922265B2 (en) * 2017-06-27 2021-02-16 Intel Corporation Techniques to control remote memory access in a compute environment
US10970215B1 (en) 2019-12-03 2021-04-06 International Business Machines Corporation Cache snooping mode extending coherence protection for certain requests

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755930A (en) * 1985-06-27 1988-07-05 Encore Computer Corporation Hierarchical cache memory system and method
US5265235A (en) * 1990-11-30 1993-11-23 Xerox Corporation Consistency protocols for shared memory multiprocessors
US5191649A (en) * 1990-12-21 1993-03-02 Intel Corporation Multiprocessor computer system with data bus and ordered and out-of-order split data transactions
US5426765A (en) * 1991-08-30 1995-06-20 Compaq Computer Corporation Multiprocessor cache abitration
GB2268859B (en) * 1992-07-16 1995-09-20 Northern Telecom Ltd Network system

Also Published As

Publication number Publication date
NO950780L (no) 1995-09-04
GB9500334D0 (en) 1995-03-01
NO312610B1 (no) 2002-06-03
US5682516A (en) 1997-10-28
GB2287161B (en) 1998-02-25
GB2287161A (en) 1995-09-06
NO950780D0 (no) 1995-02-28
ITMI950388A1 (it) 1996-09-01
SG47655A1 (en) 1998-04-17
ITMI950388A0 (it) 1995-03-01

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Legal Events

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0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19980327