IT1258985B - Circuito d'interfaccia a microcontrollore tra un apparecchio elettrico e una linea bifilare con rivelatore di picco nello stadio ricevente - Google Patents

Circuito d'interfaccia a microcontrollore tra un apparecchio elettrico e una linea bifilare con rivelatore di picco nello stadio ricevente

Info

Publication number
IT1258985B
IT1258985B ITMI921455A ITMI921455A IT1258985B IT 1258985 B IT1258985 B IT 1258985B IT MI921455 A ITMI921455 A IT MI921455A IT MI921455 A ITMI921455 A IT MI921455A IT 1258985 B IT1258985 B IT 1258985B
Authority
IT
Italy
Prior art keywords
interface circuit
peak detector
receiving stage
electric appliance
wire line
Prior art date
Application number
ITMI921455A
Other languages
English (en)
Inventor
Daniele Novati
Original Assignee
Bticino Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bticino Spa filed Critical Bticino Spa
Priority to ITMI921455A priority Critical patent/IT1258985B/it
Publication of ITMI921455A0 publication Critical patent/ITMI921455A0/it
Priority to ES93201596T priority patent/ES2131553T3/es
Priority to EP93201596A priority patent/EP0574080B1/en
Priority to DE69323796T priority patent/DE69323796T2/de
Publication of ITMI921455A1 publication Critical patent/ITMI921455A1/it
Application granted granted Critical
Publication of IT1258985B publication Critical patent/IT1258985B/it

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40013—Details regarding a bus controller
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Small-Scale Networks (AREA)

Abstract

E' descritto un circuito d'interfaccia tra un apparecchio elettrico (PS) e una linea (L) di comunicazione di dati in forma seriale che comprende un microcontrollore (MC) e mezzi circuitali di ricezione (RIC) e di trasmissione (TR) atti ad accoppiare alla linea (L), rispettivamente, i terminali di ingresso dati (RX) e di uscita dati (TX) del microcontrollore. Per poter utilizzare un microcontrollore (MC) privo della funzione di "interrupt", il circuito comprende un rivelatore di picco (D3, C6) nello stadio di ricezione (RIC).
ITMI921455A 1992-06-12 1992-06-12 Circuito d'interfaccia a microcontrollore tra un apparecchio elettrico e una linea bifilare con rivelatore di picco nello stadio ricevente IT1258985B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
ITMI921455A IT1258985B (it) 1992-06-12 1992-06-12 Circuito d'interfaccia a microcontrollore tra un apparecchio elettrico e una linea bifilare con rivelatore di picco nello stadio ricevente
ES93201596T ES2131553T3 (es) 1992-06-12 1993-06-04 Circuito de interfaz entre un microcontrolador y una linea de dos hilos con un detector de pico en la etapa receptora.
EP93201596A EP0574080B1 (en) 1992-06-12 1993-06-04 Interface circuit between a microcontroller and a two-wire line with a peak detector in the receiving stage
DE69323796T DE69323796T2 (de) 1992-06-12 1993-06-04 Schnittstellenschaltung zwischen einem Mikrokontroller und einer Zweidrahtleitung mit einem Spitzenspannungsdetektor in der Empfangsstufe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITMI921455A IT1258985B (it) 1992-06-12 1992-06-12 Circuito d'interfaccia a microcontrollore tra un apparecchio elettrico e una linea bifilare con rivelatore di picco nello stadio ricevente

Publications (3)

Publication Number Publication Date
ITMI921455A0 ITMI921455A0 (it) 1992-06-12
ITMI921455A1 ITMI921455A1 (it) 1993-12-12
IT1258985B true IT1258985B (it) 1996-03-11

Family

ID=11363506

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI921455A IT1258985B (it) 1992-06-12 1992-06-12 Circuito d'interfaccia a microcontrollore tra un apparecchio elettrico e una linea bifilare con rivelatore di picco nello stadio ricevente

Country Status (4)

Country Link
EP (1) EP0574080B1 (it)
DE (1) DE69323796T2 (it)
ES (1) ES2131553T3 (it)
IT (1) IT1258985B (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1392076B1 (it) 2008-12-04 2012-02-09 Bticino Spa Sistema elettronico di comunicazione videocitofonica e/o di automazione domestica a dimensionamento ottimizzato

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4516248A (en) * 1983-01-21 1985-05-07 E-Systems, Inc. Variable threshold receiver
DE3601243A1 (de) * 1986-01-17 1987-07-23 Bosch Gmbh Robert Lokales netzwerk fuer einchip-rechner
DE3931539A1 (de) * 1989-09-21 1991-04-04 Siemens Ag Anordnung zum anschluss von endgeraeten an eine busleitung

Also Published As

Publication number Publication date
ES2131553T3 (es) 1999-08-01
EP0574080B1 (en) 1999-03-10
ITMI921455A0 (it) 1992-06-12
DE69323796D1 (de) 1999-04-15
EP0574080A1 (en) 1993-12-15
DE69323796T2 (de) 1999-11-11
ITMI921455A1 (it) 1993-12-12

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19950630