IT1250345B - System of automatic checking of electronic modules - Google Patents
System of automatic checking of electronic modulesInfo
- Publication number
- IT1250345B IT1250345B ITTO910892A ITTO910892A IT1250345B IT 1250345 B IT1250345 B IT 1250345B IT TO910892 A ITTO910892 A IT TO910892A IT TO910892 A ITTO910892 A IT TO910892A IT 1250345 B IT1250345 B IT 1250345B
- Authority
- IT
- Italy
- Prior art keywords
- resources
- test
- circuit
- resource
- memorised
- Prior art date
Links
- 230000015654 memory Effects 0.000 abstract 4
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
A checking system 1 is described, comprising an electric circuit 5 having a plurality of resources 10 for generating test signals, for the power supply of the circuit, for measuring electrical quantities on the circuit, and for the selective connection of predetermined points of the circuit itself. Each resource is associated with its own memory 11 which memorises the configurations of the resource in different checking tests, and specifically the configuration of each phase of each test is memorised in its own memory location 30. The resources 10 are brought together in consistent groups and the resources of each group are activated in parallel with each other by a control unit 12 which simultaneously addresses the memories 11 associated with their resources, controlled on the basis of the test phase being performed at each moment. Therefore, the marshalling of the various configurations of the resources in the phases of a test only requires sequential scanning of the memory locations of each resource to read the memorised configuration. <IMAGE>
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITTO910892A IT1250345B (en) | 1991-11-20 | 1991-11-20 | System of automatic checking of electronic modules |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ITTO910892A IT1250345B (en) | 1991-11-20 | 1991-11-20 | System of automatic checking of electronic modules |
Publications (3)
Publication Number | Publication Date |
---|---|
ITTO910892A0 ITTO910892A0 (en) | 1991-11-20 |
ITTO910892A1 ITTO910892A1 (en) | 1993-05-21 |
IT1250345B true IT1250345B (en) | 1995-04-07 |
Family
ID=11409730
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ITTO910892A IT1250345B (en) | 1991-11-20 | 1991-11-20 | System of automatic checking of electronic modules |
Country Status (1)
Country | Link |
---|---|
IT (1) | IT1250345B (en) |
-
1991
- 1991-11-20 IT ITTO910892A patent/IT1250345B/en active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
ITTO910892A0 (en) | 1991-11-20 |
ITTO910892A1 (en) | 1993-05-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4484329A (en) | Apparatus for the dynamic in-circuit element-to-element comparison testing of electronic digital circuit elements | |
DE58908747D1 (en) | ADDRESSING ARRANGEMENT. | |
DE3786059D1 (en) | ELECTRONIC SYSTEM FOR MOTOR VEHICLES. | |
GB2226644B (en) | Memory testing circuit | |
GB2235073B (en) | Semiconductor memory device with test circuit | |
AU1459888A (en) | Scan test apparatus for digital systems having dynamic random access memory | |
GB8528483D0 (en) | Fault testing random access memory system | |
EP0547682A3 (en) | ||
DE3586397T2 (en) | SEMICONDUCTOR MEMORY WITH TEST PATTERN GENERATOR. | |
EP0485976A3 (en) | Fault analysis apparatus for memories having redundancy circuits | |
TW359824B (en) | Stress test apparatus and method for semiconductor memory device | |
IT1250345B (en) | System of automatic checking of electronic modules | |
GB2121550B (en) | Test system memory architecture for passing parameters and testing dynamic components | |
EP0239916A3 (en) | Refresh address counter test control circuit for dynamic random access memory system | |
FR2605112B1 (en) | DEVICE AND METHOD FOR GENERATING TEST VECTORS AND TEST METHOD FOR INTEGRATED CIRCUIT | |
KR930015989U (en) | Memory device test mode circuit | |
ES2056847T3 (en) | PROCEDURE FOR TESTING LINE NETWORKS. | |
ATE308136T1 (en) | PCB ARRANGEMENT | |
TW362191B (en) | Sequence control circuit | |
EP0281867A3 (en) | Semiconductor memory device with address generator | |
FR2663774B1 (en) | CIRCUIT FOR TESTING ELECTRICALLY PROGRAMMABLE MEMORY CELLS. | |
GB2307051B (en) | An equipment for testing electronic circuitry | |
JPS5478052A (en) | Function generator | |
HUT52257A (en) | Circuit arrangement for generating high speed sample, favourably for testing memory circuits | |
CA1197322A (en) | Apparatus for the dynamic in-circuit testing of electronic digital circuit elements |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
0001 | Granted | ||
TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19951129 |