IT1168874B - Computer system with bus cycle sharing - Google Patents

Abstract

The computer terminal system includes a CPU, a direct memory access (DMA) controller, a RAM terminal display units and various other units all coupled to a system bus. The CPU includes bus arbitration logic which assigns time slots on the system bus in accordance with predetermined priority rules. To achieve max. bus usage, a unit having a short bus cycle can utilise the bus during a portion of a longer bus cycle, being utilised by another unit, when that other unit is not transferring information over the bus. For example, the processor bus cycle equals two memory cycles, and the processor always accesses the memory during the second half of the processor cycle. Hence another cycle, e.g. a chip refresh cycle, can be activated concurrently with the first half of the processor cycle.