IT1166764B - Struttura semiconduttrice con miglior isolamento di vetro al fosfosilicato - Google Patents

Struttura semiconduttrice con miglior isolamento di vetro al fosfosilicato

Info

Publication number
IT1166764B
IT1166764B IT22104/79A IT2210479A IT1166764B IT 1166764 B IT1166764 B IT 1166764B IT 22104/79 A IT22104/79 A IT 22104/79A IT 2210479 A IT2210479 A IT 2210479A IT 1166764 B IT1166764 B IT 1166764B
Authority
IT
Italy
Prior art keywords
phosphosilicate glass
glass insulation
semiconductive structure
semiconductive
insulation
Prior art date
Application number
IT22104/79A
Other languages
English (en)
Other versions
IT7922104A0 (it
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT7922104A0 publication Critical patent/IT7922104A0/it
Application granted granted Critical
Publication of IT1166764B publication Critical patent/IT1166764B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823406—Combination of charge coupled devices, i.e. CCD, or BBD
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/133—Reflow oxides and glasses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Formation Of Insulating Films (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
IT22104/79A 1978-05-01 1979-04-24 Struttura semiconduttrice con miglior isolamento di vetro al fosfosilicato IT1166764B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/901,901 US4191603A (en) 1978-05-01 1978-05-01 Making semiconductor structure with improved phosphosilicate glass isolation

Publications (2)

Publication Number Publication Date
IT7922104A0 IT7922104A0 (it) 1979-04-24
IT1166764B true IT1166764B (it) 1987-05-06

Family

ID=25415023

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22104/79A IT1166764B (it) 1978-05-01 1979-04-24 Struttura semiconduttrice con miglior isolamento di vetro al fosfosilicato

Country Status (6)

Country Link
US (1) US4191603A (it)
EP (1) EP0005166B1 (it)
JP (1) JPS54144185A (it)
CA (1) CA1115856A (it)
DE (1) DE2964588D1 (it)
IT (1) IT1166764B (it)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4261772A (en) * 1979-07-06 1981-04-14 American Microsystems, Inc. Method for forming voltage-invariant capacitors for MOS type integrated circuit device utilizing oxidation and reflow techniques
US4299024A (en) * 1980-02-25 1981-11-10 Harris Corporation Fabrication of complementary bipolar transistors and CMOS devices with poly gates
JPS56146246A (en) * 1980-04-14 1981-11-13 Toshiba Corp Manufacture of semiconductor integrated circuit
US4433008A (en) * 1982-05-11 1984-02-21 Rca Corporation Doped-oxide diffusion of phosphorus using borophosphosilicate glass
US4499653A (en) * 1983-11-03 1985-02-19 Westinghouse Electric Corp. Small dimension field effect transistor using phosphorous doped silicon glass reflow process
US4515668A (en) * 1984-04-25 1985-05-07 Honeywell Inc. Method of forming a dielectric layer comprising a gettering material
US4557950A (en) * 1984-05-18 1985-12-10 Thermco Systems, Inc. Process for deposition of borophosphosilicate glass
US4606936A (en) * 1985-04-12 1986-08-19 Harris Corporation Stress free dielectric isolation technology
US4808555A (en) * 1986-07-10 1989-02-28 Motorola, Inc. Multiple step formation of conductive material layers
US4732658A (en) * 1986-12-03 1988-03-22 Honeywell Inc. Planarization of silicon semiconductor devices
US5084418A (en) * 1988-12-27 1992-01-28 Texas Instruments Incorporated Method of making an array device with buried interconnects
US5304831A (en) * 1990-12-21 1994-04-19 Siliconix Incorporated Low on-resistance power MOS technology
US5404040A (en) * 1990-12-21 1995-04-04 Siliconix Incorporated Structure and fabrication of power MOSFETs, including termination structures
DE4300806C1 (de) * 1993-01-14 1993-12-23 Siemens Ag Verfahren zur Herstellung von vertikalen MOS-Transistoren
US5963840A (en) 1996-11-13 1999-10-05 Applied Materials, Inc. Methods for depositing premetal dielectric layer at sub-atmospheric and high temperature conditions
US7670920B2 (en) * 2007-04-09 2010-03-02 Texas Instruments Incorporated Methods and apparatus for forming a polysilicon capacitor
US9484451B2 (en) * 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
US9431249B2 (en) 2011-12-01 2016-08-30 Vishay-Siliconix Edge termination for super junction MOSFET devices
US9614043B2 (en) 2012-02-09 2017-04-04 Vishay-Siliconix MOSFET termination trench
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9508596B2 (en) 2014-06-20 2016-11-29 Vishay-Siliconix Processes used in fabricating a metal-insulator-semiconductor field effect transistor
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
WO2016028944A1 (en) 2014-08-19 2016-02-25 Vishay-Siliconix Super-junction metal oxide semiconductor field effect transistor

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2040180B2 (de) * 1970-01-22 1977-08-25 Intel Corp, Mountain View, Calif. (V.St.A.) Verfahren zur verhinderung von mechanischen bruechen einer duennen, die oberflaeche eines halbleiterkoerpers ueberdeckende isolierschichten ueberziehenden elektrisch leitenden schicht
US3897282A (en) * 1972-10-17 1975-07-29 Northern Electric Co Method of forming silicon gate device structures with two or more gate levels
US3915767A (en) * 1973-02-05 1975-10-28 Honeywell Inc Rapidly responsive transistor with narrowed base
US4028150A (en) * 1973-05-03 1977-06-07 Ibm Corporation Method for making reliable MOSFET device
GB1503017A (en) * 1974-02-28 1978-03-08 Tokyo Shibaura Electric Co Method of manufacturing semiconductor devices
US4075045A (en) * 1976-02-09 1978-02-21 International Business Machines Corporation Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps
DE2705611A1 (de) * 1977-02-10 1978-08-17 Siemens Ag Verfahren zum bedecken einer auf einem substrat befindlichen ersten schicht oder schichtenfolge mit einer weiteren zweiten schicht durch aufsputtern

Also Published As

Publication number Publication date
EP0005166B1 (de) 1983-01-26
US4191603A (en) 1980-03-04
JPS54144185A (en) 1979-11-10
EP0005166A1 (de) 1979-11-14
JPS6213814B2 (it) 1987-03-28
DE2964588D1 (en) 1983-03-03
IT7922104A0 (it) 1979-04-24
CA1115856A (en) 1982-01-05

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