IT1132025B - Circuito di sincronizzazione ad anello digitale - Google Patents

Circuito di sincronizzazione ad anello digitale

Info

Publication number
IT1132025B
IT1132025B IT23789/80A IT2378980A IT1132025B IT 1132025 B IT1132025 B IT 1132025B IT 23789/80 A IT23789/80 A IT 23789/80A IT 2378980 A IT2378980 A IT 2378980A IT 1132025 B IT1132025 B IT 1132025B
Authority
IT
Italy
Prior art keywords
synchronization circuit
digital ring
ring synchronization
digital
circuit
Prior art date
Application number
IT23789/80A
Other languages
English (en)
Other versions
IT8023789A0 (it
Inventor
Leslie Alan Baxter
Peter Cummiskey
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of IT8023789A0 publication Critical patent/IT8023789A0/it
Application granted granted Critical
Publication of IT1132025B publication Critical patent/IT1132025B/it

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/422—Synchronisation for ring networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Small-Scale Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
IT23789/80A 1979-07-31 1980-07-29 Circuito di sincronizzazione ad anello digitale IT1132025B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/062,425 US4306304A (en) 1979-07-31 1979-07-31 Digital loop synchronization circuit

Publications (2)

Publication Number Publication Date
IT8023789A0 IT8023789A0 (it) 1980-07-29
IT1132025B true IT1132025B (it) 1986-06-25

Family

ID=22042404

Family Applications (1)

Application Number Title Priority Date Filing Date
IT23789/80A IT1132025B (it) 1979-07-31 1980-07-29 Circuito di sincronizzazione ad anello digitale

Country Status (7)

Country Link
US (1) US4306304A (it)
EP (1) EP0033337B1 (it)
JP (1) JPS56501030A (it)
CA (1) CA1126833A (it)
DE (1) DE3067683D1 (it)
IT (1) IT1132025B (it)
WO (1) WO1981000498A1 (it)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024613B2 (ja) * 1980-03-10 1985-06-13 日本電気株式会社 デ−タ伝送装置
JPS5745757A (en) * 1980-09-03 1982-03-15 Hitachi Ltd Ring type communication system of equal level
CA1169156A (en) * 1981-05-11 1984-06-12 Chris Stollberger Apparatus for conforming the length of a data stream to a transmission line
ZA83892B (en) * 1982-02-19 1983-11-30 Int Computers Ltd Data transmission systems
US4535448A (en) * 1982-12-10 1985-08-13 At&T Bell Laboratories Dual bus communication system
EP0112426B1 (fr) * 1982-12-28 1987-03-11 International Business Machines Corporation Système de synchronisation pour réseau de communication multiplex en boucle fermée
US4595921A (en) * 1983-08-11 1986-06-17 Wang Laboratories, Inc. Method of polling to ascertain service needs
US4779087A (en) * 1985-02-13 1988-10-18 Fujitsu Limited Loop transmission system with frame synchronization control
US4858232A (en) * 1988-05-20 1989-08-15 Dsc Communications Corporation Distributed switching system
US10884451B2 (en) * 2018-05-01 2021-01-05 DeGirum Corporation System and methods for completing a cascaded clock ring bus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3681759A (en) * 1970-08-06 1972-08-01 Collins Radio Co Data loop synchronizing apparatus
US3732374A (en) * 1970-12-31 1973-05-08 Ibm Communication system and method
US3919484A (en) * 1974-03-01 1975-11-11 Rca Corp Loop controller for a loop data communications system
US4071706A (en) * 1976-09-13 1978-01-31 Rca Corporation Data packets distribution loop
US4158748A (en) * 1977-06-27 1979-06-19 Motorola, Inc. Apparatus for digital data synchronization

Also Published As

Publication number Publication date
CA1126833A (en) 1982-06-29
US4306304A (en) 1981-12-15
IT8023789A0 (it) 1980-07-29
WO1981000498A1 (en) 1981-02-19
DE3067683D1 (en) 1984-06-07
JPS56501030A (it) 1981-07-23
EP0033337B1 (en) 1984-05-02
EP0033337A1 (en) 1981-08-12
EP0033337A4 (en) 1982-01-08

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