IT1078800B - Processo per formare strati elettricamente isolanti su substrati non planari a circuito integrato - Google Patents

Processo per formare strati elettricamente isolanti su substrati non planari a circuito integrato

Info

Publication number
IT1078800B
IT1078800B IT27569/76A IT2756976A IT1078800B IT 1078800 B IT1078800 B IT 1078800B IT 27569/76 A IT27569/76 A IT 27569/76A IT 2756976 A IT2756976 A IT 2756976A IT 1078800 B IT1078800 B IT 1078800B
Authority
IT
Italy
Prior art keywords
integrated circuit
electrically insulating
insulating layers
planar substrates
circuit non
Prior art date
Application number
IT27569/76A
Other languages
English (en)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT1078800B publication Critical patent/IT1078800B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
IT27569/76A 1975-10-14 1976-09-24 Processo per formare strati elettricamente isolanti su substrati non planari a circuito integrato IT1078800B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/621,899 US4007103A (en) 1975-10-14 1975-10-14 Planarizing insulative layers by resputtering

Publications (1)

Publication Number Publication Date
IT1078800B true IT1078800B (it) 1985-05-08

Family

ID=24492123

Family Applications (1)

Application Number Title Priority Date Filing Date
IT27569/76A IT1078800B (it) 1975-10-14 1976-09-24 Processo per formare strati elettricamente isolanti su substrati non planari a circuito integrato

Country Status (7)

Country Link
US (1) US4007103A (it)
JP (1) JPS5247679A (it)
CA (1) CA1067038A (it)
DE (1) DE2636971C2 (it)
FR (1) FR2328285A1 (it)
GB (1) GB1497779A (it)
IT (1) IT1078800B (it)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4151010A (en) * 1978-06-30 1979-04-24 International Business Machines Corporation Forming adjacent impurity regions in a semiconductor by oxide masking
JPS5511312A (en) * 1978-07-10 1980-01-26 Hitachi Ltd Manufacturing method of semiconductor device
US4410622A (en) * 1978-12-29 1983-10-18 International Business Machines Corporation Forming interconnections for multilevel interconnection metallurgy systems
JPS57204133A (en) * 1981-06-10 1982-12-14 Hitachi Ltd Manufacture of semiconductor integrated circuit
JPS5895821A (ja) * 1981-11-30 1983-06-07 Mitsubishi Electric Corp 平行平板型プラズマｃｖｄ法
CA1169022A (en) * 1982-04-19 1984-06-12 Kevin Duncan Integrated circuit planarizing process
US4541169A (en) * 1984-10-29 1985-09-17 International Business Machines Corporation Method for making studs for interconnecting metallization layers at different levels in a semiconductor chip
US5182235A (en) * 1985-02-20 1993-01-26 Mitsubishi Denki Kabushiki Kaisha Manufacturing method for a semiconductor device having a bias sputtered insulating film
KR900005785B1 (ko) * 1985-05-13 1990-08-11 닛뽄덴신덴와 가부시끼가이샤 평탄성 박막의 제조방법
US4761332A (en) * 1985-06-24 1988-08-02 International Business Machines Corporation Planarized ceramic substrates
US4891112A (en) * 1985-11-12 1990-01-02 Eastman Kodak Company Sputtering method for reducing hillocking in aluminum layers formed on substrates
US4690746A (en) * 1986-02-24 1987-09-01 Genus, Inc. Interlayer dielectric process
US4732658A (en) * 1986-12-03 1988-03-22 Honeywell Inc. Planarization of silicon semiconductor devices
US4756810A (en) * 1986-12-04 1988-07-12 Machine Technology, Inc. Deposition and planarizing methods and apparatus
JPS63234534A (ja) * 1987-03-24 1988-09-29 Oki Electric Ind Co Ltd 半導体素子の製造方法
US5215933A (en) * 1990-05-11 1993-06-01 Kabushiki Kaisha Toshiba Method of manufacturing nonvolatile semiconductor memory device
JP3048072B2 (ja) * 1991-05-25 2000-06-05 ローム株式会社 酸化膜の成膜方法及びその装置
JPH07153745A (ja) * 1993-12-01 1995-06-16 Nec Corp 半導体装置の製造方法
US5928960A (en) * 1996-10-24 1999-07-27 International Business Machines Corporation Process for reducing pattern factor effects in CMP planarization
US6593241B1 (en) * 1998-05-11 2003-07-15 Applied Materials Inc. Method of planarizing a semiconductor device using a high density plasma system

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3474021A (en) * 1966-01-12 1969-10-21 Ibm Method of forming openings using sequential sputtering and chemical etching
US3804738A (en) * 1973-06-29 1974-04-16 Ibm Partial planarization of electrically insulative films by resputtering

Also Published As

Publication number Publication date
CA1067038A (en) 1979-11-27
DE2636971A1 (de) 1977-04-28
FR2328285B1 (it) 1978-06-30
GB1497779A (en) 1978-01-12
FR2328285A1 (fr) 1977-05-13
US4007103A (en) 1977-02-08
JPS5247679A (en) 1977-04-15
DE2636971C2 (de) 1984-05-24
JPS5535853B2 (it) 1980-09-17

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