IT1055399B - Memoria perfezionata - Google Patents

Memoria perfezionata

Info

Publication number
IT1055399B
IT1055399B IT20385/76A IT2038576A IT1055399B IT 1055399 B IT1055399 B IT 1055399B IT 20385/76 A IT20385/76 A IT 20385/76A IT 2038576 A IT2038576 A IT 2038576A IT 1055399 B IT1055399 B IT 1055399B
Authority
IT
Italy
Prior art keywords
improved memory
memory
improved
Prior art date
Application number
IT20385/76A
Other languages
English (en)
Italian (it)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT1055399B publication Critical patent/IT1055399B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/85—Active fault masking without idle spares

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Error Detection And Correction (AREA)
IT20385/76A 1975-03-20 1976-02-20 Memoria perfezionata IT1055399B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/560,421 US3958228A (en) 1975-03-20 1975-03-20 Fault tolerant least recently used algorithm logic

Publications (1)

Publication Number Publication Date
IT1055399B true IT1055399B (it) 1981-12-21

Family

ID=24237754

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20385/76A IT1055399B (it) 1975-03-20 1976-02-20 Memoria perfezionata

Country Status (7)

Country Link
US (1) US3958228A (US20030199744A1-20031023-C00003.png)
JP (1) JPS51114041A (US20030199744A1-20031023-C00003.png)
CA (1) CA1053804A (US20030199744A1-20031023-C00003.png)
DE (1) DE2610411C2 (US20030199744A1-20031023-C00003.png)
FR (2) FR2304963A1 (US20030199744A1-20031023-C00003.png)
GB (1) GB1484235A (US20030199744A1-20031023-C00003.png)
IT (1) IT1055399B (US20030199744A1-20031023-C00003.png)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226124A (en) * 1975-08-22 1977-02-26 Fujitsu Ltd Buffer memory control unit
NL7510904A (nl) * 1975-09-17 1977-03-21 Philips Nv Woordgroepsprioriteitsinrichting.
US4035778A (en) * 1975-11-17 1977-07-12 International Business Machines Corporation Apparatus for assigning space in a working memory as a function of the history of usage
US4229789A (en) * 1977-12-22 1980-10-21 Ncr Corporation System for transferring data between high speed and low speed memories
US4168541A (en) * 1978-09-25 1979-09-18 Sperry Rand Corporation Paired least recently used block replacement system
US4322795A (en) * 1980-01-24 1982-03-30 Honeywell Information Systems Inc. Cache memory utilizing selective clearing and least recently used updating
US4334289A (en) * 1980-02-25 1982-06-08 Honeywell Information Systems Inc. Apparatus for recording the order of usage of locations in memory
US4361878A (en) * 1980-10-27 1982-11-30 Control Data Corporation Degradable LRU circuit
US4355306A (en) * 1981-01-30 1982-10-19 International Business Machines Corporation Dynamic stack data compression and decompression system
JPS6049950B2 (ja) * 1981-08-27 1985-11-06 富士通株式会社 Ｌｒｕエラ−処理方式
US4422145A (en) * 1981-10-26 1983-12-20 International Business Machines Corporation Thrashing reduction in demand accessing of a data base through an LRU paging buffer pool
US4550278A (en) * 1982-07-21 1985-10-29 Mitsubishi Denki Kabushiki Kaisha Control device
US4607331A (en) * 1983-05-13 1986-08-19 Motorola, Inc. Method and apparatus for implementing an algorithm associated with stored information
ATE48195T1 (de) * 1984-08-10 1989-12-15 Siemens Ag Schaltungsanordnung zur prioritaetsbezogenen einordnung und registrierung einzelner speicherabschnitte bzw. baenke unter anwendung des lru-algorithmus.
US5140690A (en) * 1988-06-14 1992-08-18 Mitsubishi Denki Kabushiki Kaisha Least-recently-used circuit
JP2786209B2 (ja) * 1988-10-07 1998-08-13 株式会社日立製作所 忘却機能を有する知識データ管理方法
US4967414A (en) * 1989-01-06 1990-10-30 International Business Machines Corp. LRU error detection using the collection of read and written LRU bits
US5060136A (en) * 1989-01-06 1991-10-22 International Business Machines Corp. Four-way associative cache with dlat and separately addressable arrays used for updating certain bits without reading them out first
JP2979771B2 (ja) * 1991-09-12 1999-11-15 株式会社日立製作所 情報処理装置及びそのバス制御方法
FR2683924B1 (fr) * 1991-11-18 1997-01-03 Bull Sa Memoire integree, son procede de gestion et systeme informatique en resultant.
US5539893A (en) * 1993-11-16 1996-07-23 Unisys Corporation Multi-level memory and methods for allocating data most likely to be used to the fastest memory level
DE4407626C1 (de) * 1994-03-08 1995-05-24 Karl Michael Marks Verfahren und Einrichtung zur Steuerung der Datenverfügbarkeit in Zwischenspeichern bei Computern
US20010002851A1 (en) * 1995-04-14 2001-06-07 Takao Shimada Multimedia data processing system in network
US6571317B2 (en) * 2001-05-01 2003-05-27 Broadcom Corporation Replacement data error detector
JP4616421B2 (ja) 2008-11-11 2011-01-19 オリンパスメディカルシステムズ株式会社 撮像装置および内視鏡

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588829A (en) * 1968-11-14 1971-06-28 Ibm Integrated memory system with block transfer to a buffer store

Also Published As

Publication number Publication date
US3958228A (en) 1976-05-18
DE2610411A1 (de) 1976-10-07
FR2304963A1 (fr) 1976-10-15
FR116049A (US20030199744A1-20031023-C00003.png)
GB1484235A (en) 1977-09-01
FR2304963B1 (US20030199744A1-20031023-C00003.png) 1979-06-01
JPS51114041A (en) 1976-10-07
JPS5413344B2 (US20030199744A1-20031023-C00003.png) 1979-05-30
CA1053804A (en) 1979-05-01
DE2610411C2 (de) 1985-07-11

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