IT1051045B - Disposizione circuitale per decodificare segnali di lettura forni ti da memoria a strato magnetico - Google Patents
Disposizione circuitale per decodificare segnali di lettura forni ti da memoria a strato magneticoInfo
- Publication number
- IT1051045B IT1051045B IT3032275A IT3032275A IT1051045B IT 1051045 B IT1051045 B IT 1051045B IT 3032275 A IT3032275 A IT 3032275A IT 3032275 A IT3032275 A IT 3032275A IT 1051045 B IT1051045 B IT 1051045B
- Authority
- IT
- Italy
- Prior art keywords
- ovens
- magnetic layer
- reading signals
- circuit provision
- decode
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
- G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Manipulation Of Pulses (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Digital Magnetic Recording (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19742460534 DE2460534B2 (de) | 1974-12-20 | 1974-12-20 | Schaltungsanordnung zur decodierung von von magnetschichtspeichern gelieferten lesesignalen |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IT1051045B true IT1051045B (it) | 1981-04-21 |
Family
ID=5934093
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT3032275A IT1051045B (it) | 1974-12-20 | 1975-12-16 | Disposizione circuitale per decodificare segnali di lettura forni ti da memoria a strato magnetico |
Country Status (8)
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| HU183139B (en) * | 1980-05-14 | 1984-04-28 | Magyar Optikai Muevek | Electronic decoding circuit arrangement for systems with self-synchronization |
-
1974
- 1974-12-20 DE DE19742460534 patent/DE2460534B2/de active Granted
-
1975
- 1975-11-07 AT AT848075A patent/AT353515B/de not_active IP Right Cessation
- 1975-12-05 CH CH1582475A patent/CH597724A5/xx not_active IP Right Cessation
- 1975-12-16 IT IT3032275A patent/IT1051045B/it active
- 1975-12-17 FR FR7538640A patent/FR2295514A1/fr active Granted
- 1975-12-17 GB GB5154175A patent/GB1518700A/en not_active Expired
- 1975-12-18 NL NL7514781A patent/NL7514781A/xx not_active Application Discontinuation
- 1975-12-19 BE BE162942A patent/BE836875A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| DE2460534C3 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1978-08-03 |
| GB1518700A (en) | 1978-07-19 |
| BE836875A (fr) | 1976-06-21 |
| FR2295514A1 (fr) | 1976-07-16 |
| FR2295514B3 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1979-10-05 |
| DE2460534B2 (de) | 1977-12-01 |
| CH597724A5 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1978-04-14 |
| NL7514781A (nl) | 1976-06-22 |
| AT353515B (de) | 1979-11-26 |
| ATA848075A (de) | 1979-04-15 |
| DE2460534A1 (de) | 1976-07-01 |
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