IT1038100B - PERFECTED MEMORY SPECIAL FOR DATA PROCESSING SYSTEMS - Google Patents

PERFECTED MEMORY SPECIAL FOR DATA PROCESSING SYSTEMS

Info

Publication number
IT1038100B
IT1038100B IT23304/75A IT2330475A IT1038100B IT 1038100 B IT1038100 B IT 1038100B IT 23304/75 A IT23304/75 A IT 23304/75A IT 2330475 A IT2330475 A IT 2330475A IT 1038100 B IT1038100 B IT 1038100B
Authority
IT
Italy
Prior art keywords
perfected
data processing
processing systems
memory special
special
Prior art date
Application number
IT23304/75A
Other languages
Italian (it)
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of IT1038100B publication Critical patent/IT1038100B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
    • H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
    • H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
    • H01L27/0733—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with capacitors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
IT23304/75A 1974-06-28 1975-05-14 PERFECTED MEMORY SPECIAL FOR DATA PROCESSING SYSTEMS IT1038100B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2431079A DE2431079C3 (en) 1974-06-28 1974-06-28 Dynamic semiconductor memory with two-transistor memory elements

Publications (1)

Publication Number Publication Date
IT1038100B true IT1038100B (en) 1979-11-20

Family

ID=5919184

Family Applications (1)

Application Number Title Priority Date Filing Date
IT23304/75A IT1038100B (en) 1974-06-28 1975-05-14 PERFECTED MEMORY SPECIAL FOR DATA PROCESSING SYSTEMS

Country Status (6)

Country Link
JP (1) JPS5428252B2 (en)
CH (1) CH581885A5 (en)
DE (1) DE2431079C3 (en)
FR (1) FR2276659A1 (en)
GB (1) GB1502334A (en)
IT (1) IT1038100B (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5853512B2 (en) * 1976-02-13 1983-11-29 株式会社東芝 Method for manufacturing semiconductor memory device
JPS5922316B2 (en) * 1976-02-24 1984-05-25 株式会社東芝 dynamic memory device
US4040016A (en) * 1976-03-31 1977-08-02 International Business Machines Corporation Twin nodes capacitance memory
US4103342A (en) * 1976-06-17 1978-07-25 International Business Machines Corporation Two-device memory cell with single floating capacitor
CA1164710A (en) * 1978-05-09 1984-04-03 Edward J. Reardon, Jr. Phototropic photosensitive compositions containing fluoran colorformer
DE2837877A1 (en) * 1978-08-30 1980-03-06 Siemens Ag MOS-INTEGRATED SEMICONDUCTOR MEMORY AND METHOD FOR THE PRODUCTION THEREOF
DE2855118C2 (en) * 1978-12-20 1981-03-26 IBM Deutschland GmbH, 70569 Stuttgart Dynamic FET memory
DE3173745D1 (en) * 1981-10-30 1986-03-20 Ibm Deutschland Fet memory
JP5034133B2 (en) * 2000-02-29 2012-09-26 富士通セミコンダクター株式会社 Semiconductor memory device
JP4707244B2 (en) 2000-03-30 2011-06-22 ルネサスエレクトロニクス株式会社 Semiconductor memory device and semiconductor device
TWI359422B (en) 2008-04-15 2012-03-01 Faraday Tech Corp 2t sram and associated cell structure

Also Published As

Publication number Publication date
FR2276659B1 (en) 1980-01-04
JPS5428252B2 (en) 1979-09-14
JPS513824A (en) 1976-01-13
GB1502334A (en) 1978-03-01
DE2431079C3 (en) 1979-12-13
DE2431079B2 (en) 1979-04-26
CH581885A5 (en) 1976-11-15
FR2276659A1 (en) 1976-01-23
DE2431079A1 (en) 1976-02-12

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